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qcacld-3.0: Relocate all the files under target folder

Browse source 
Relocate all the files under target folder to a new
fw-api repository. fw-api repository is created to automate
the interface interface change propagation. FW CLs will be
automatically propagated to the fw-api repository.

Change-Id: Ib5533cac57ae3364323b30d54d12b620a178f03a
CRs-Fixed: 1093452
This commit is contained in:
Krishna Kumaar Natarajan 2016-12-02 10:25:58 -08:00 • committed by qcabuildsw
commit 6835e77b39
36 changed files with 0 additions and 42292 deletions
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71
target/inc/a_osapi.h
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/* ============================================================================== */
/* This file contains the definitions of the basic atheros data types. */
/* It is used to map the data types in atheros files to a platform specific */
/* type. */
/* */
/* Author(s): ="Atheros" */
/* ============================================================================== */
#ifndef _A_OSAPI_H_
#define _A_OSAPI_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "osapi_linux.h"
#endif
/*=== the following primitives have the same definition for all platforms ===*/
#define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \
typedef char assertion_name[(predicate) ? 1 : -1]
/*
* If N is a power of 2, then N and N-1 are orthogonal
* (N-1 has all the least-significant bits set which are zero in N)
* so N ^ (N-1) = (N << 1) - 1
*/
#define A_COMPILE_TIME_ASSERT_IS_PWR2(assertion_name, value) \
A_COMPILE_TIME_ASSERT (assertion_name, \
(((value) ^ ((value)-1)) == ((value) << 1) - 1))
#ifndef __ubicom32__
#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
os_malloc_CONSISTENT(osdev, size, pa, context, retry)
#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
OS_FREE_CONSISTENT(osdev, size, vaddr, pa, context)
#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context)
#else
#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
os_malloc_NONCONSISTENT(osdev, size, pa, context, retry)
#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
OS_FREE_NONCONSISTENT(osdev, size, vaddr, pa, context)
#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context) \
OS_SYNC_SINGLE(osdev, pa, size, dir, context)
#endif /* ubicom32 */
#endif /* _OSAPI_H_ */

97
target/inc/a_usb_defs.h
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* Shared USB definitions
*
*
*
*
*/
#ifndef __A_USB_DEFS_H__
#define __A_USB_DEFS_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* USB endpoint definitions */
#define USB_EP_ADDR_APP_CTRL_IN 0x81
#define USB_EP_ADDR_APP_DATA_IN 0x82
#define USB_EP_ADDR_APP_DATA2_IN 0x83
#define USB_EP_ADDR_APP_INT_IN 0x84
#define USB_EP_ADDR_APP_CTRL_OUT 0x01
#define USB_EP_ADDR_APP_DATA_LP_OUT 0x02
#define USB_EP_ADDR_APP_DATA_MP_OUT 0x03
#define USB_EP_ADDR_APP_DATA_HP_OUT 0x04
#define USB_CONTROL_REQ_SEND_BMI_CMD 1
#define USB_CONTROL_REQ_RECV_BMI_RESP 2
#define USB_CONTROL_REQ_DIAG_CMD 3
#define USB_CONTROL_REQ_DIAG_RESP 4
/* #define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64 */
#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 252
#define HIF_BMI_MAX_TRANSFER_SIZE USB_CONTROL_MAX_BMI_TRANSFER_SIZE
/* 512 Bytes Maxp for High Speed for BULK EP */
#define USB_HS_BULK_MAXP_SIZE 0x200
/* 64 Bytes Maxp for Full Speed for BULK EP */
#define USB_FS_BULK_MAXP_SIZE 0x40
/* diagnostic command defnitions */
#define USB_CTRL_DIAG_CC_READ 0
#define USB_CTRL_DIAG_CC_WRITE 1
#define USB_CTRL_DIAG_CC_WARM_RESET 2
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
A_UINT32 Value;
A_UINT32 _pad[1];
} POSTPACK USB_CTRL_DIAG_CMD_WRITE;
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
} POSTPACK USB_CTRL_DIAG_CMD_READ;
typedef PREPACK struct {
A_UINT32 ReadValue;
} POSTPACK USB_CTRL_DIAG_RESP_READ;
#define USB_CTRL_MAX_DIAG_CMD_SIZE (sizeof(USB_CTRL_DIAG_CMD_WRITE))
#define USB_CTRL_MAX_DIAG_RESP_SIZE (sizeof(USB_CTRL_DIAG_RESP_READ))
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif

59
target/inc/apb_athr_wlan_map.h
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _APB_ATHR_WLAN_MAP_H_
#define _APB_ATHR_WLAN_MAP_H_
#define RTC_SOC_BASE_ADDRESS 0x00004000
#define RTC_WMAC_BASE_ADDRESS 0x00005000
#define MAC_COEX_BASE_ADDRESS 0x00006000
#define BT_COEX_BASE_ADDRESS 0x00007000
#define SOC_PCIE_BASE_ADDRESS 0x00008000
#define SOC_CORE_BASE_ADDRESS 0x00009000
#define WLAN_UART_BASE_ADDRESS 0x0000c000
#define WLAN_SI_BASE_ADDRESS 0x00010000
#define WLAN_GPIO_BASE_ADDRESS 0x00014000
#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
#define WLAN_MAC_BASE_ADDRESS 0x00020000
#define EFUSE_BASE_ADDRESS 0x00030000
#define FPGA_REG_BASE_ADDRESS 0x00039000
#define WLAN_UART2_BASE_ADDRESS 0x00054c00
#define CE_WRAPPER_BASE_ADDRESS 0x00057000
#define CE0_BASE_ADDRESS 0x00057400
#define CE1_BASE_ADDRESS 0x00057800
#define CE2_BASE_ADDRESS 0x00057c00
#define CE3_BASE_ADDRESS 0x00058000
#define CE4_BASE_ADDRESS 0x00058400
#define CE5_BASE_ADDRESS 0x00058800
#define CE6_BASE_ADDRESS 0x00058c00
#define CE7_BASE_ADDRESS 0x00059000
#define DBI_BASE_ADDRESS 0x00060000
#define WLAN_MBOX_BASE_ADDRESS 0x00068000
#define WLAN_DBG_UART_BASE_ADDRESS 0x00069000
#define USB_DMA_BASE_ADDRESS 0x0006a000
#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */

83
target/inc/athdefs.h
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/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __ATHDEFS_H__
#define __ATHDEFS_H__
/*
* This file contains definitions that may be used across both
* Host and Target software. Nothing here is module-dependent
* or platform-dependent.
*/
/*
* Generic error codes that can be used by hw, sta, ap, sim, dk
* and any other environments. Since these are enums, feel free to
* add any more codes that you need.
*/
typedef enum {
A_ERROR = -1, /* Generic error return */
A_OK = 0, /* success */
/* Following values start at 1 */
A_DEVICE_NOT_FOUND, /* not able to find PCI device */
A_NO_MEMORY, /* not able to allocate memory, not available */
A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
A_NO_FREE_DESC, /* no free descriptors available */
A_BAD_ADDRESS, /* address does not match descriptor */
A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
A_REGS_NOT_MAPPED, /* registers not correctly mapped */
A_EPERM, /* Not superuser */
A_EACCES, /* Access denied */
A_ENOENT, /* No such entry, search failed, etc. */
A_EEXIST, /* The object already exists (can't create) */
A_EFAULT, /* Bad address fault */
A_EBUSY, /* Object is busy */
A_EINVAL, /* Invalid parameter */
A_EMSGSIZE, /* Inappropriate message buffer length */
A_ECANCELED, /* Operation canceled */
A_ENOTSUP, /* Operation not supported */
A_ECOMM, /* Communication error on send */
A_EPROTO, /* Protocol error */
A_ENODEV, /* No such device */
A_EDEVNOTUP, /* device is not UP */
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED, /* Object was consumed */
A_CLONE, /* The buffer is cloned */
A_USB_ERROR, /* Rome USB Target error */
} A_STATUS;
#define A_SUCCESS(x) (x == A_OK)
#define A_FAILED(x) (!A_SUCCESS(x))
#endif /* __ATHDEFS_H__ */

35
target/inc/athendpack.h
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifdef VXWORKS
#endif /* VXWORKS */
#if defined(LINUX) || defined(__linux__)
#endif /* LINUX */
#ifdef QNX
#endif /* QNX */

44
target/inc/bin_sig.h
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/*
* Copyright (c) 2012,2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef BIN_SIGN_H_
#define BIN_SIGN_H_
/* Signed binary MetaData */
typedef struct {
unsigned int magic_num;
unsigned int total_len;
unsigned int rampatch_len;
unsigned int product_id;
unsigned int patch_ver;
unsigned short sign_format_ver;
unsigned short sign_algorithm;
unsigned char reserved[8];
} SIGN_HEADER_T;
#endif /* BIN_SIGN_H_ */

385
target/inc/bmi_msg.h
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/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __BMI_MSG_H__
#define __BMI_MSG_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Bootloader Messaging Interface (BMI)
*
* BMI is a very simple messaging interface used during initialization
* to read memory, write memory, execute code, and to define an
* application entry PC.
*
* It is used to download an application to AR6K, to provide
* patches to code that is already resident on AR6K, and generally
* to examine and modify state. The Host has an opportunity to use
* BMI only once during bootup. Once the Host issues a BMI_DONE
* command, this opportunity ends.
*
* The Host writes BMI requests to mailbox0, and reads BMI responses
* from mailbox0. BMI requests all begin with a command
* (see below for specific commands), and are followed by
* command-specific data.
*
* Flow control:
* The Host can only issue a command once the Target gives it a
* "BMI Command Credit", using AR6K Counter #4. As soon as the
* Target has completed a command, it issues another BMI Command
* Credit (so the Host can issue the next command).
*
* BMI handles all required Target-side cache flushing.
*/
/* Maximum data size used for BMI transfers */
#define BMI_DATASZ_MAX 256
/* BMI Commands */
#define BMI_NO_COMMAND 0
#define BMI_DONE 1
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* Response format: none
*/
#define BMI_READ_MEMORY 2
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* Response format:
* A_UINT8 data[length]
*/
#define BMI_WRITE_MEMORY 3
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
/*
* Capbility to write "segmented files" is provided for two reasons
* 1) backwards compatibility for certain situations where Hosts
* have limited flexibility
* 2) because it's darn convenient.
*
* A segmented file consists of a file header followed by an arbitrary number
* of segments. Each segment contains segment metadata -- a Target address and
* a length -- followed by "length" bytes of data. A segmented file ends with
* a segment that specifies length=BMI_SGMTFILE_DONE. When a segmented file
* is sent to the Target, firmware writes each segment to the specified address.
*
* Special cases:
* 1) If a segment's metadata indicates length=BMI_SGMTFILE_EXEC, then the
* specified address is used as a function entry point for a brief function
* with prototype "(void *)(void)". That function is called immediately.
* After execution of the function completes, firmware continues with the
* next segment. No data is expected when length=BMI_SGMTFILE_EXEC.
*
* 2) If a segment's metadata indicates length=BMI_SGMTFILE_BEGINADDR, then
* the specified address is established as the application start address
* so that a subsequent BMI_DONE jumps there.
*
* 3) If a segment's metadata indicates length=BMI_SGMTFILE_BDDATA, then
* the specified address is used as the (possibly compressed) length of board
* data, which is loaded into the proper Target address as specified by
* hi_board_data. In addition, the hi_board_data_initialized flag is set.
*
* A segmented file is sent to the Target using a sequence of 1 or more
* BMI_WRITE_MEMORY commands. The first such command must have
* address=BMI_SEGMENTED_WRITE_ADDR. Subsequent BMI_WRITE_MEMORY commands
* can use an arbitrary address. In each BMI_WRITE_MEMORY command, the
* length specifies the number of data bytes transmitted (except for the
* special cases listed above).
*
* Alternatively, a segmented file may be sent to the Target using a
* BMI_LZ_STREAM_START command with address=BMI_SEGMENTED_WRITE_ADDR
* followed by a series of BMI_LZ_DATA commands that each send the next portion
* of the segmented file.
*
* The data segments may be lz77 compressed. In this case, the segmented file
* header flag, BMI_SGMTFILE_FLAG_COMPRESS, must be set. Note that segmented
* file METAdata is never compressed; only the data segments themselves are
* compressed. There is no way to mix compressed and uncompressed data segments
* in a single segmented file. Compressed (or uncompressed) segments are handled
* by both BMI_WRITE_MEMORY and by BMI_LZ_DATA commands. (Compression is an
* attribute of the segmented file rather than of the command used to transmit
* it.)
*/
#define BMI_SEGMENTED_WRITE_ADDR 0x1234
/* File header for a segmented file */
struct bmi_segmented_file_header {
A_UINT32 magic_num;
A_UINT32 file_flags;
};
#define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */
#define BMI_SGMTFILE_FLAG_COMPRESS 1
/* Metadata for a segmented file segment */
struct bmi_segmented_metadata {
A_UINT32 addr;
A_UINT32 length;
};
/* Special values for bmi_segmented_metadata.length (all have high bit set) */
#define BMI_SGMTFILE_DONE 0xffffffff /* end of segmented data */
#define BMI_SGMTFILE_BDDATA 0xfffffffe /* Board Data segment */
#define BMI_SGMTFILE_BEGINADDR 0xfffffffd /* set beginning address */
#define BMI_SGMTFILE_EXEC 0xfffffffc /* immediate function execution */
#define BMI_EXECUTE 4
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* Response format:
* A_UINT32 return value
*/
/*
* Note: In order to support the segmented file feature
* (see BMI_WRITE_MEMORY), when the address specified in a
* BMI_EXECUTE command matches (same physical address)
* BMI_SEGMENTED_WRITE_ADDR, it is ignored. Instead, execution
* begins at the address specified by hi_app_start.
*/
#define BMI_SET_APP_START 5
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* Response format: none
*/
#define BMI_READ_SOC_REGISTER 6
#define BMI_READ_SOC_WORD 6
/*
* Semantics: Read a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* Response format:
* A_UINT32 value
*/
#define BMI_WRITE_SOC_REGISTER 7
#define BMI_WRITE_SOC_WORD 7
/*
* Semantics: Write a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
*
* Response format: none
*/
#define BMI_GET_TARGET_ID 8
#define BMI_GET_TARGET_INFO 8
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
*
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
*
* Response format2 (intermediate firmware, during transition):
* A_UINT32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*
* Response format3 (newest firmware)
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
/* size of this structure */
A_UINT32 target_info_byte_count;
A_UINT32 target_ver;
A_UINT32 target_type;
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_UNKNOWN 0
#define TARGET_TYPE_AR6001 1
#define TARGET_TYPE_AR6002 2
#define TARGET_TYPE_AR6003 3
#define TARGET_TYPE_AR6004 5
#define TARGET_TYPE_AR6006 6
#define TARGET_TYPE_AR9888 7
#define TARGET_TYPE_AR6320 8
#define TARGET_TYPE_AR900B 9
/* For attach Peregrine 2.0 board target_reg_tbl only */
#define TARGET_TYPE_AR9888V2 10
/* For attach Rome1.0 target_reg_tbl only*/
#define TARGET_TYPE_AR6320V1 11
/* For Rome2.0/2.1 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V2 12
/* For Rome3.0 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V3 13
/* For Tufello1.0 target_reg_tbl ID*/
#define TARGET_TYPE_QCA9377V1 14
/* cascade */
#define TARGET_TYPE_QCA9984 15
/* dakota */
#define TARGET_TYPE_IPQ4019 16
/* besra */
#define TARGET_TYPE_QCA9888 17
/* For Adrastea target */
#define TARGET_TYPE_ADRASTEA 19
extern void target_register_tbl_attach(A_UINT32 target_type);
#define BMI_ROMPATCH_INSTALL 9
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
*/
#define BMI_ROMPATCH_UNINSTALL 10
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
*
* Response format: none
*/
#define BMI_ROMPATCH_ACTIVATE 11
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_ROMPATCH_DEACTIVATE 12
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_LZ_STREAM_START 13
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
* be sufficiently large to hold the uncompressed
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_LZ_DATA 14
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* at most BMI_DATASZ_MAX
* A_UINT8 CompressedData[length]
* Response format: none
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_NVRAM_PROCESS 15
#define BMI_NVRAM_SEG_NAME_SZ 16
/*
* Semantics: Cause Target to search NVRAM (if any) for a
* segment with the specified name and process it according
* to NVRAM metadata.
* Request format:
* A_UINT32 command (BMI_NVRAM_PROCESS)
* A_UCHAR name[BMI_NVRAM_SEG_NAME_SZ] name (LE format)
* Response format:
* A_UINT32 0, if nothing was executed;
* otherwise the value returned from the
* last NVRAM segment that was executed
*/
#define BMI_SIGN_STREAM_START 17
/*
* Semantics: Trigger target start/end binary signature verification
* flow.
* Request format:
* A_UINT32 command (BMI_SIGN_STREAM_START)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
/* TBDXXX: Need a better place for these */
#define BMI_CE_NUM_TO_TARG 0
#define BMI_CE_NUM_TO_HOST 1
#endif /* __BMI_MSG_H__ */

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/*
* Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __CEPCI_H__
#define __CEPCI_H__
/*
* Support for Copy Engine over PCI.
* Structures shared between Host software and Target firmware.
*/
/*
* Total number of PCIe MSI interrupts requested for all interrupt sources.
* PCIe standard forces this to be a power of 2.
* Some Host OS's limit MSI requests that can be granted to 8
* so for now we abide by this limit and avoid requesting more
* than that.
*/
#define MSI_NUM_REQUEST_LOG2 3
#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
/*
* Granted MSIs are assigned as follows:
* Firmware uses the first
* Remaining MSIs, if any, are used by Copy Engines
* This mapping is known to both Target firmware and Host software.
* It may be changed as long as Host and Target are kept in sync.
*/
#define MSI_ASSIGN_FW 0 /* 1 MSI for firmware (errors, etc.) */
#define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */
#define MSI_ASSIGN_CE_MAX 7
/*
* PCI-specific Target state. Much of this may be of interest
* to the Host so HOST_INTEREST->hi_interconnect_state points
* here (and all members are 32-bit quantities in order to
* facilitate Host access). In particular, Host software is
* required to initialize pipe_cfg_addr and svc_to_pipe_map.
*/
struct pcie_state_s {
uint32_t pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
uint32_t svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
uint32_t MSI_requested; /* number of MSI interrupts requested */
uint32_t MSI_granted; /* number of MSI interrupts granted */
uint32_t MSI_addr; /* Message Signalled Interrupt address */
uint32_t MSI_data; /* Base data */
uint32_t MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
uint32_t power_mgmt_method; /* PCIE_PWR_METHOD_* */
uint32_t config_flags; /* PCIE_CONFIG_FLAG_* */
};
/*
* PCIE_CONFIG_FLAG definitions
*/
#if defined(AR900B)
#define CE_PKTLOG_PIPE 8 /* used by both host and target side */
#endif
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
#define PCIE_CONFIG_FLAG_CLK_GATING_L1 0x0000001
#define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002
#define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004
#define PCIE_CONFIG_FLAG_CLK_REQ_L1 0x0000008
#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
/*
* Configuration information for a Copy Engine pipe.
* Passed from Host to Target during startup (one per CE).
*/
struct CE_pipe_config {
uint32_t pipenum;
uint32_t pipedir;
uint32_t nentries;
uint32_t nbytes_max;
uint32_t flags;
uint32_t reserved;
};
#endif /* __CEPCI_H__ */

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/*
* Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _DBGLOG_H_
#define _DBGLOG_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#include "wlan_module_ids.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DBGLOG_TIMESTAMP_OFFSET 0
/* Bit 0-15. Contains bit 8-23 of the LF0 timer */
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF
#define DBGLOG_DBGID_OFFSET 0
#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */
/* Upper limit is width of mask */
#define DBGLOG_DBGID_NUM_MAX 256
#define DBGLOG_MODULEID_OFFSET 10
#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */
/* Upper limit is width of mask */
#define DBGLOG_MODULEID_NUM_MAX 32
#define DBGLOG_VDEVID_OFFSET 18
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25 */
#define DBGLOG_VDEVID_NUM_MAX 16
#define DBGLOG_NUM_ARGS_OFFSET 26
#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */
/* it is limited bcoz of limitations of corebsp MSG*() to accept max 9 arg */
#define DBGLOG_NUM_ARGS_MAX 9
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE
#define DBGLOG_GET_DBGID(arg) \
((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
#define DBGLOG_GET_MODULEID(arg) \
((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
#define DBGLOG_GET_VDEVID(arg) \
((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
#define DBGLOG_GET_NUMARGS(arg) \
((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
#define DBGLOG_GET_TIME_STAMP(arg) \
((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
/* Debug Log levels*/
enum DBGLOG_LOG_LVL {
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
DBGLOG_INFO_LVL_2,
DBGLOG_WARN,
DBGLOG_ERR,
DBGLOG_LVL_MAX
};
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
} POSTPACK;
PREPACK struct dbglog_hdr_s {
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
} POSTPACK;
#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_H_ */

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target/inc/dbglog_id.h
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154
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _EFUSE_REG_REG_H_
#define _EFUSE_REG_REG_H_
#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
#define EFUSE_WR_ENABLE_REG_V_MSB 0
#define EFUSE_WR_ENABLE_REG_V_LSB 0
#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
#define EFUSE_INT_ENABLE_REG_V_MSB 0
#define EFUSE_INT_ENABLE_REG_V_LSB 0
#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
#define EFUSE_INT_STATUS_REG_V_MSB 0
#define EFUSE_INT_STATUS_REG_V_LSB 0
#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
#define BITMASK_WR_REG_ADDRESS 0x0000000c
#define BITMASK_WR_REG_OFFSET 0x0000000c
#define BITMASK_WR_REG_V_MSB 31
#define BITMASK_WR_REG_V_LSB 0
#define BITMASK_WR_REG_V_MASK 0xffffffff
#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
#define VDDQ_SETTLE_TIME_REG_V_MSB 31
#define VDDQ_SETTLE_TIME_REG_V_LSB 0
#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
#define VDDQ_HOLD_TIME_REG_ADDRESS 0x00000014
#define VDDQ_HOLD_TIME_REG_OFFSET 0x00000014
#define VDDQ_HOLD_TIME_REG_V_MSB 31
#define VDDQ_HOLD_TIME_REG_V_LSB 0
#define VDDQ_HOLD_TIME_REG_V_MASK 0xffffffff
#define VDDQ_HOLD_TIME_REG_V_GET(x) (((x) & VDDQ_HOLD_TIME_REG_V_MASK) >> VDDQ_HOLD_TIME_REG_V_LSB)
#define VDDQ_HOLD_TIME_REG_V_SET(x) (((x) << VDDQ_HOLD_TIME_REG_V_LSB) & VDDQ_HOLD_TIME_REG_V_MASK)
#define RD_STROBE_PW_REG_ADDRESS 0x00000018
#define RD_STROBE_PW_REG_OFFSET 0x00000018
#define RD_STROBE_PW_REG_V_MSB 31
#define RD_STROBE_PW_REG_V_LSB 0
#define RD_STROBE_PW_REG_V_MASK 0xffffffff
#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
#define PG_STROBE_PW_REG_ADDRESS 0x0000001c
#define PG_STROBE_PW_REG_OFFSET 0x0000001c
#define PG_STROBE_PW_REG_V_MSB 31
#define PG_STROBE_PW_REG_V_LSB 0
#define PG_STROBE_PW_REG_V_MASK 0xffffffff
#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
#define PGENB_SETUP_HOLD_TIME_REG_ADDRESS 0x00000020
#define PGENB_SETUP_HOLD_TIME_REG_OFFSET 0x00000020
#define PGENB_SETUP_HOLD_TIME_REG_V_MSB 31
#define PGENB_SETUP_HOLD_TIME_REG_V_LSB 0
#define PGENB_SETUP_HOLD_TIME_REG_V_MASK 0xffffffff
#define PGENB_SETUP_HOLD_TIME_REG_V_GET(x) (((x) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) >> PGENB_SETUP_HOLD_TIME_REG_V_LSB)
#define PGENB_SETUP_HOLD_TIME_REG_V_SET(x) (((x) << PGENB_SETUP_HOLD_TIME_REG_V_LSB) & PGENB_SETUP_HOLD_TIME_REG_V_MASK)
#define STROBE_PULSE_INTERVAL_REG_ADDRESS 0x00000024
#define STROBE_PULSE_INTERVAL_REG_OFFSET 0x00000024
#define STROBE_PULSE_INTERVAL_REG_V_MSB 31
#define STROBE_PULSE_INTERVAL_REG_V_LSB 0
#define STROBE_PULSE_INTERVAL_REG_V_MASK 0xffffffff
#define STROBE_PULSE_INTERVAL_REG_V_GET(x) (((x) & STROBE_PULSE_INTERVAL_REG_V_MASK) >> STROBE_PULSE_INTERVAL_REG_V_LSB)
#define STROBE_PULSE_INTERVAL_REG_V_SET(x) (((x) << STROBE_PULSE_INTERVAL_REG_V_LSB) & STROBE_PULSE_INTERVAL_REG_V_MASK)
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_ADDRESS 0x00000028
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_OFFSET 0x00000028
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MSB 31
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB 0
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK 0xffffffff
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_GET(x) (((x) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) >> CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB)
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_SET(x) (((x) << CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK)
#define EFUSE_INTF0_ADDRESS 0x00000800
#define EFUSE_INTF0_OFFSET 0x00000800
#define EFUSE_INTF0_R_MSB 31
#define EFUSE_INTF0_R_LSB 0
#define EFUSE_INTF0_R_MASK 0xffffffff
#define EFUSE_INTF0_R_GET(x) (((x) & EFUSE_INTF0_R_MASK) >> EFUSE_INTF0_R_LSB)
#define EFUSE_INTF0_R_SET(x) (((x) << EFUSE_INTF0_R_LSB) & EFUSE_INTF0_R_MASK)
#define EFUSE_INTF1_ADDRESS 0x00001000
#define EFUSE_INTF1_OFFSET 0x00001000
#define EFUSE_INTF1_R_MSB 31
#define EFUSE_INTF1_R_LSB 0
#define EFUSE_INTF1_R_MASK 0xffffffff
#define EFUSE_INTF1_R_GET(x) (((x) & EFUSE_INTF1_R_MASK) >> EFUSE_INTF1_R_LSB)
#define EFUSE_INTF1_R_SET(x) (((x) << EFUSE_INTF1_R_LSB) & EFUSE_INTF1_R_MASK)
#ifndef __ASSEMBLER__
typedef struct efuse_reg_reg_s {
volatile unsigned int efuse_wr_enable_reg;
volatile unsigned int efuse_int_enable_reg;
volatile unsigned int efuse_int_status_reg;
volatile unsigned int bitmask_wr_reg;
volatile unsigned int vddq_settle_time_reg;
volatile unsigned int vddq_hold_time_reg;
volatile unsigned int rd_strobe_pw_reg;
volatile unsigned int pg_strobe_pw_reg;
volatile unsigned int pgenb_setup_hold_time_reg;
volatile unsigned int strobe_pulse_interval_reg;
volatile unsigned int csb_addr_load_setup_hold_reg;
unsigned char pad0[2004]; /* pad to 0x800 */
volatile unsigned int efuse_intf0[512];
volatile unsigned int efuse_intf1[512];
} efuse_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _EFUSE_REG_H_ */

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/*
* Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _ENET__H_
#define _ENET__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
#define ETHERNET_ADDR_LEN 6 /* bytes */
#define ETHERNET_TYPE_LEN 2 /* bytes - length of the Ethernet type field */
struct ethernet_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 ethertype[ETHERNET_TYPE_LEN];
};
#define ETHERNET_HDR_LEN (sizeof(struct ethernet_hdr_t))
#define ETHERNET_CRC_LEN 4 /* bytes - length of the Ethernet CRC */
#define ETHERNET_MAX_LEN 1518 /* bytes */
#define ETHERNET_MTU (ETHERNET_MAX_LEN - (ETHERNET_HDR_LEN + ETHERNET_CRC_LEN))
struct llc_snap_hdr_t {
A_UINT8 dsap;
A_UINT8 ssap;
A_UINT8 cntl;
A_UINT8 org_code[3];
A_UINT8 ethertype[2];
};
#define LLC_SNAP_HDR_LEN (sizeof(struct llc_snap_hdr_t))
#define LLC_SNAP_HDR_OFFSET_ETHERTYPE \
(offsetof(struct llc_snap_hdr_t, ethertype[0]))
#define ETHERTYPE_VLAN_LEN 4
struct ethernet_vlan_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 vlan_tpid[2];
A_UINT8 vlan_tci[2];
A_UINT8 ethertype[2];
};
#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
#ifndef ETHERTYPE_IPV4
#define ETHERTYPE_IPV4 0x0800 /* Internet Protocol, Version 4 (IPv4) */
#endif
#ifndef ETHERTYPE_AARP
#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */
#endif
#ifndef ETHERTYPE_IPX
#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */
#endif
#ifndef ETHERTYPE_ARP
#define ETHERTYPE_ARP 0x0806 /* Address Resolution Protocol (ARP) */
#endif
#ifndef ETHERTYPE_RARP
#define ETHERTYPE_RARP 0x8035 /* Reverse Address Resolution Protocol (RARP) */
#endif
#ifndef ETHERTYPE_VLAN
#define ETHERTYPE_VLAN 0x8100 /* VLAN TAG protocol */
#endif
#ifndef ETHERTYPE_SNMP
#define ETHERTYPE_SNMP 0x814C /* Simple Network Management Protocol (SNMP) */
#endif
#ifndef ETHERTYPE_IPV6
#define ETHERTYPE_IPV6 0x86DD /* Internet Protocol, Version 6 (IPv6) */
#endif
#ifndef ETHERTYPE_PAE
#define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */
#endif
#ifndef ETHERTYPE_WAI
#define ETHERTYPE_WAI 0x88B4 /* WAPI */
#endif
#ifndef ETHERTYPE_TDLS
#define ETHERTYPE_TDLS 0x890D /* TDLS */
#endif
#define LLC_SNAP_LSAP 0xaa
#define LLC_UI 0x3
#define RFC1042_SNAP_ORGCODE_0 0x00
#define RFC1042_SNAP_ORGCODE_1 0x00
#define RFC1042_SNAP_ORGCODE_2 0x00
#define BTEP_SNAP_ORGCODE_0 0x00
#define BTEP_SNAP_ORGCODE_1 0x00
#define BTEP_SNAP_ORGCODE_2 0xf8
#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)
#define IS_RFC1042(_llc) ((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
#define IS_BTEP(_llc) ((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
#endif /* _ENET__H_ */

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/*
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/* This file contains shared definitions for the host/target endpoint ping test */
#ifndef EPPING_TEST_H
#define EPPING_TEST_H
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
#endif
#define EPPING_RSVD_FILL 0xCC
#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
typedef PREPACK struct {
A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host */
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
A_UINT8 _pad[2]; /* padding for alignment */
A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
A_UINT16 Cmd_h; /* ping command (filled by host) */
A_UINT16 CmdFlags_h; /* optional flags */
A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
A_UINT16 DataLength; /* length of data */
A_UINT16 DataCRC; /* 16 bit CRC of data */
A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
} POSTPACK EPPING_HEADER;
#define EPPING_PING_MAGIC_0 0xAA
#define EPPING_PING_MAGIC_1 0x55
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3; }
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */
#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
/* test command parameters may be no more than 8 bytes */
typedef PREPACK struct {
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
A_UINT16 Flags; /* flags */
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
#define EPPING_CONT_RX_NO_DATA_FILL (1 << 3) /* target will not fill buffers */
A_UINT16 Context; /* flags */
} POSTPACK EPPING_CONT_RX_PARAMS;
#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* EPPING_TEST_H */

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target/inc/htc.h
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/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __HTC_H__
#define __HTC_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#ifdef ATHR_WIN_NWF
#pragma warning(disable:4214)
#endif
#undef MS
#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
#undef WO
#define WO(_f) ((_f ## _OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
#define HTC_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
#define HTC_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
#define HTC_WRITE32(_addr, _val) \
(*(A_UINT32 *)(_addr) = (_val))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#endif
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
/****** DANGER DANGER ***************
*
* The frame header length and message formats defined herein were
* selected to accommodate optimal alignment for target processing. This reduces code
* size and improves performance.
*
* Any changes to the header length may alter the alignment and cause exceptions
* on the target. When adding to the message structures insure that fields are
* properly aligned.
*
*/
/* HTC frame header */
typedef PREPACK struct _HTC_FRAME_HDR {
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT32 EndpointID : 8, Flags : 8, PayloadLen : 16; /* length of data (including trailer) that follows the header */
/***** end of 4-byte lookahead ****/
A_UINT32 ControlBytes0 : 8,/*used for CRC check if CRC_CHECK flag set*/
ControlBytes1 : 8, /*used for seq check if SEQ_CHECK flag set*/
reserved : 16; /*used by bundle processing in SDIO systems*/
/* message payload starts after the header */
} POSTPACK HTC_FRAME_HDR;
#define HTC_FRAME_HDR_ENDPOINTID_LSB 0
#define HTC_FRAME_HDR_ENDPOINTID_MASK 0x000000ff
#define HTC_FRAME_HDR_ENDPOINTID_OFFSET 0x00000000
#define HTC_FRAME_HDR_FLAGS_LSB 8
#define HTC_FRAME_HDR_FLAGS_MASK 0x0000ff00
#define HTC_FRAME_HDR_FLAGS_OFFSET 0x00000000
#define HTC_FRAME_HDR_PAYLOADLEN_LSB 16
#define HTC_FRAME_HDR_PAYLOADLEN_MASK 0xffff0000
#define HTC_FRAME_HDR_PAYLOADLEN_OFFSET 0x00000000
#define HTC_FRAME_HDR_CONTROLBYTES0_LSB 0
#define HTC_FRAME_HDR_CONTROLBYTES0_MASK 0x000000ff
#define HTC_FRAME_HDR_CONTROLBYTES0_OFFSET 0x00000004
#define HTC_FRAME_HDR_CONTROLBYTES1_LSB 8
#define HTC_FRAME_HDR_CONTROLBYTES1_MASK 0x0000ff00
#define HTC_FRAME_HDR_CONTROLBYTES1_OFFSET 0x00000004
#define HTC_FRAME_HDR_RESERVED_LSB 16
#define HTC_FRAME_HDR_RESERVED_MASK 0xffff0000
#define HTC_FRAME_HDR_RESERVED_OFFSET 0x00000004
/* frame header flags */
/* send direction */
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
#define HTC_FLAGS_SEQ_CHECK (1 << 2) /* seq check on rx side */
#define HTC_FLAGS_CRC_CHECK (1 << 3) /* CRC check on rx side */
/* receive direction */
#define HTC_FLAGS_RECV_1MORE_BLOCK (1 << 0) /* bit 0 bundle trailer present */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xFC) /* bits 7..2 */
#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 2
/*
* To be compatible with an older definition of a smaller (4-bit)
* bundle count field, the bundle count is stored in a segmented
* format - the 4 LSbs of the bundle count value are stored in bits 5:2
* of the BUNDLE_CNT field, which is bits 7:4 of the HTC_FLAGS word;
* the next 2 bits of the bundle count value are stored in bits 1:0 of
* the BUNDLE_CNT field, which is bits 3:2 of the HTC_FLAGS word.
*/
#define HTC_FLAGS_RECV_BUNDLE_CNT_SET(x) \
((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT)
#define HTC_FLAGS_RECV_BUNDLE_CNT_GET(x) \
((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> \
(HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4))
#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
#define HTC_HDR_ALIGNMENT_PADDING \
(((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#define HTC_MAX_TRAILER_LENGTH 255
#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR))
/* HTC control message IDs */
#define HTC_MSG_READY_ID 1
#define HTC_MSG_CONNECT_SERVICE_ID 2
#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
#define HTC_MSG_SETUP_COMPLETE_ID 4
#define HTC_MSG_SETUP_COMPLETE_EX_ID 5
#define HTC_MSG_SEND_SUSPEND_COMPLETE 6
#define HTC_MSG_NACK_SUSPEND 7
#define HTC_MSG_WAKEUP_FROM_SUSPEND_ID 8
#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
/* base message ID header */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
} POSTPACK HTC_UNKNOWN_MSG;
#define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0
#define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000
/* HTC ready message
* direction : target-to-host */
typedef PREPACK struct {
A_UINT32 MessageID : 16, /* ID */
CreditCount : 16; /* number of credits the target can offer */
A_UINT32 CreditSize : 16, /* size of each credit */
MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */
_Pad1 : 8;
} POSTPACK HTC_READY_MSG;
#define HTC_READY_MSG_MESSAGEID_LSB 0
#define HTC_READY_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_READY_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_READY_MSG_CREDITCOUNT_LSB 16
#define HTC_READY_MSG_CREDITCOUNT_MASK 0xffff0000
#define HTC_READY_MSG_CREDITCOUNT_OFFSET 0x00000000
#define HTC_READY_MSG_CREDITSIZE_LSB 0
#define HTC_READY_MSG_CREDITSIZE_MASK 0x0000ffff
#define HTC_READY_MSG_CREDITSIZE_OFFSET 0x00000004
#define HTC_READY_MSG_MAXENDPOINTS_LSB 16
#define HTC_READY_MSG_MAXENDPOINTS_MASK 0x00ff0000
#define HTC_READY_MSG_MAXENDPOINTS_OFFSET 0x00000004
/* extended HTC ready message */
typedef PREPACK struct {
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT32 HTCVersion : 8, MaxMsgsPerHTCBundle : 8, reserved : 16;
} POSTPACK HTC_READY_EX_MSG;
#define HTC_READY_EX_MSG_HTCVERSION_LSB 0
#define HTC_READY_EX_MSG_HTCVERSION_MASK 0x000000ff
#define HTC_READY_EX_MSG_HTCVERSION_OFFSET sizeof(HTC_READY_MSG)
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_LSB 8
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_MASK 0x0000ff00
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_OFFSET sizeof(HTC_READY_MSG)
#define HTC_VERSION_2P0 0x00
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
/* connect service
* direction : host-to-target */
typedef PREPACK struct {
/* service ID of the service to connect to */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 ConnectionFlags : 16, /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)
/* reduce credit dribbling when
the host needs credits */
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
/* disable credit flow control on a specific service */
#define HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL (1 << 3)
/* enable htc schedule on a specific service */
#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE (1 << 4)
ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_MSG;
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_LSB 0
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_LSB 16
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_LSB 0
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_LSB 16
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_MASK 0x00ff0000
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_OFFSET 0x00000004
#define HTC_SET_RECV_ALLOC_SHIFT 8
#define HTC_SET_RECV_ALLOC_MASK 0xFF00
#define HTC_CONNECT_FLAGS_SET_RECV_ALLOCATION(value) (((A_UINT8)value) << HTC_SET_RECV_ALLOC_SHIFT)
#define HTC_CONNECT_FLAGS_GET_RECV_ALLOCATION(value) (A_UINT8)(((value) & HTC_SET_RECV_ALLOC_MASK) >> HTC_SET_RECV_ALLOC_SHIFT)
/* connect response
* direction : target-to-host */
typedef PREPACK struct {
/* service ID that the connection request was made */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 Status : 8, /* service connection status */
EndpointID : 8, /* assigned endpoint ID */
MaxMsgSize : 16; /* maximum expected message size on this endpoint */
A_UINT32 ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8, reserved : 16;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_LSB 16
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_MASK 0x000000ff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_LSB 8
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_MASK 0x0000ff00
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_LSB 16
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_MASK 0x000000ff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
/* currently, no other fields */
} POSTPACK HTC_SETUP_COMPLETE_MSG;
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_LSB 0
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_OFFSET 0x00000000
/* extended setup completion message */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
A_UINT32 SetupFlags : 32;
A_UINT32 MaxMsgsPerBundledRecv : 8, Rsvd0 : 8, Rsvd1 : 8, Rsvd2 : 8;
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_MASK 0xffffffff
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_OFFSET 0x00000004
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_MASK 0x000000ff
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_LSB 8
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_MASK 0x0000ff00
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_LSB 16
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_MASK 0x00ff0000
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_LSB 24
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_MASK 0xff000000
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) /* enable recv bundling from target */
#define HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW (1 << 1) /* disable credit based flow control,
only supported on some interconnects */
/* connect response status codes */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
/* report record IDs */
#define HTC_RECORD_NULL 0
#define HTC_RECORD_CREDITS 1
#define HTC_RECORD_LOOKAHEAD 2
#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
typedef PREPACK struct {
A_UINT32 RecordID : 8, /* Record ID */
Length : 8, /* Length of record */
reserved : 16;
} POSTPACK HTC_RECORD_HDR;
#define HTC_RECORD_HDR_RECORDID_LSB 0
#define HTC_RECORD_HDR_RECORDID_MASK 0x000000ff
#define HTC_RECORD_HDR_RECORDID_OFFSET 0x00000000
#define HTC_RECORD_HDR_LENGTH_LSB 8
#define HTC_RECORD_HDR_LENGTH_MASK 0x0000ff00
#define HTC_RECORD_HDR_LENGTH_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 EndpointID : 8, /* Endpoint that owns these credits */
Credits : 8, /* credits to report since last report */
reserved : 16;
} POSTPACK HTC_CREDIT_REPORT;
#define HTC_CREDIT_REPORT_ENDPOINTID_LSB 0
#define HTC_CREDIT_REPORT_ENDPOINTID_MASK 0x000000ff
#define HTC_CREDIT_REPORT_ENDPOINTID_OFFSET 0x00000000
#define HTC_CREDIT_REPORT_CREDITS_LSB 8
#define HTC_CREDIT_REPORT_CREDITS_MASK 0x0000ff00
#define HTC_CREDIT_REPORT_CREDITS_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 PreValid : 8, /* pre valid guard */
reserved0 : 24;
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
A_UINT32 PostValid : 8, /* post valid guard */
reserved1 : 24;
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
} POSTPACK HTC_LOOKAHEAD_REPORT;
#define HTC_LOOKAHEAD_REPORT_PREVALID_LSB 0
#define HTC_LOOKAHEAD_REPORT_PREVALID_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_PREVALID_OFFSET 0x00000000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_POSTVALID_LSB 0
#define HTC_LOOKAHEAD_REPORT_POSTVALID_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_POSTVALID_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000000
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */

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/*
* Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __HTC_SERVICES_H__
#define __HTC_SERVICES_H__
/* Current service IDs */
typedef enum {
RSVD_SERVICE_GROUP = 0,
WMI_SERVICE_GROUP = 1,
NMI_SERVICE_GROUP = 2,
HTT_SERVICE_GROUP = 3,
CFG_NV_SERVICE_GROUP = 4,
WDI_IPA_SERVICE_GROUP = 5,
PACKET_LOG_SERVICE_GROUP = 6,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
} HTC_SERVICE_GROUP_IDS;
#define MAKE_SERVICE_ID(group,index) \
(int)(((int)group << 8) | (int)(index))
/* NOTE: service ID of 0x0000 is reserved and should never be used */
#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
#define WMI_MAX_SERVICES 5
#define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
#define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
#define HTT_DATA_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,0)
#define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,1)
#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2)
/* raw stream service (i.e. flash, tcmd, calibration apps) */
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
#define CFG_NV_SVC MAKE_SERVICE_ID(CFG_NV_SERVICE_GROUP,0)
#define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP,0)
#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP, 0)
/*
* Directions for interconnect pipe configuration.
* These definitions may be used during configuration and are shared
* between Host and Target.
*
* Pipe Directions are relative to the Host, so PIPEDIR_IN means
* "coming IN over air through Target to Host" as with a WiFi Rx operation.
* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
* over the interconnect.
*/
typedef A_UINT32 PIPEDIR;
#define PIPEDIR_NONE 0
#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
#define PIPEDIR_INOUT 3 /* bidirectional, target to target */
#define PIPEDIR_INOUT_T2T PIPEDIR_INOUT
#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
#define PIPEDIR_MATCH(d1, d2) (((PIPEDIR)(d1) & (PIPEDIR)(d2)) != 0)
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
A_UINT32 service_id;
A_UINT32 pipedir;
A_UINT32 pipenum;
};
#endif /*HTC_SERVICES_H_ */

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target/inc/htt.h
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target/inc/htt_common.h
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/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/**
* @file htt_common.h
*
* @details the public header file of HTT layer shared between host and firmware
*/
#ifndef _HTT_COMMON_H_
#define _HTT_COMMON_H_
enum htt_sec_type {
htt_sec_type_none,
htt_sec_type_wep128,
htt_sec_type_wep104,
htt_sec_type_wep40,
htt_sec_type_tkip,
htt_sec_type_tkip_nomic,
htt_sec_type_aes_ccmp,
htt_sec_type_wapi,
htt_sec_type_aes_ccmp_256,
htt_sec_type_aes_gcmp,
htt_sec_type_aes_gcmp_256,
/* keep this last! */
htt_num_sec_types
};
enum htt_rx_ind_mpdu_status {
HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
HTT_RX_IND_MPDU_STATUS_OK,
HTT_RX_IND_MPDU_STATUS_ERR_FCS,
HTT_RX_IND_MPDU_STATUS_ERR_DUP,
HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
/*
* MISC: discard for unspecified reasons.
* Leave this enum value last.
*/
HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
};
#define HTT_INVALID_PEER 0xffff
#define HTT_INVALID_VDEV 0xff
#define HTT_NON_QOS_TID 16
#define HTT_INVALID_TID 31
#define HTT_TX_EXT_TID_DEFAULT 0
#define HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST HTT_NON_QOS_TID
#define HTT_TX_EXT_TID_MGMT 17
#define HTT_TX_EXT_TID_INVALID HTT_INVALID_TID
#define HTT_TX_EXT_TID_NONPAUSE 19
#define HTT_TX_L3_CKSUM_OFFLOAD 1
#define HTT_TX_L4_CKSUM_OFFLOAD 2
/**
* @brief General specification of the tx frame contents
*
* @details
* For efficiency, the HTT packet type values correspond
* to the bit positions of the WAL packet type values, so the
* translation is a simple shift operation.
* The exception is the "mgmt" type, which specifies frame payload
* type rather than L2 header type.
*/
enum htt_pkt_type {
htt_pkt_type_raw = 0,
htt_pkt_type_native_wifi = 1,
htt_pkt_type_ethernet = 2,
htt_pkt_type_mgmt = 3,
htt_pkt_type_eth2 = 4,
/* keep this last */
htt_pkt_num_types
};
/*
* TX MSDU ID partition -
* FW supports bigger MSDU ID partition which is defined as
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* When both host and FW support new partition, FW uses
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* If host doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
* Handshaking is done through WMI_READY and WMI_INIT
*/
#define HTT_TX_HOST_MSDU_ID_SPACE_BEGIN 0
#define HTT_TX_IPA_MSDU_ID_SPACE_BEGIN 3000
#define TGT_RX2TX_MSDU_ID_SPACE_BEGIN 6000
/* 8192 = 0xr2000 */
#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192
/* 12288 = 0x3000 */
#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288
#endif /* _HTT_COMMON_H_ */

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target/inc/htt_isoc.h
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target/inc/ip_prot.h
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/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _IP_PROT__H_
#define _IP_PROT__H_
#define IP_PROTOCOL_ICMP 0x01 /* Internet Control Message Protocol */
#define IP_PROTOCOL_IGMP 0x02 /* Internet Group Management Protocol */
#define IP_PROTOCOL_IPV4 0x04 /* IPv4 (encapsulation) */
#define IP_PROTOCOL_TCP 0x06 /* Transmission Control Protocol */
#define IP_PROTOCOL_UDP 0x11 /* User Datagram Protocol */
#define IP_PROTOCOL_RDP 0x1B /* Reliable Datagram Protocol */
#define IP_PROTOCOL_IPV6 0x29 /* IPv6 (encapsulation) */
#define IP_PROTOCOL_IPV6_ROUTE 0x2B /* Routing Header for IPv6 */
#define IP_PROTOCOL_IPV6_FRAG 0x2C /* Fragment Header for IPv6 */
#define IP_PROTOCOL_RSVP 0x2E /* Resource Reservation Protocol */
#define IP_PROTOCOL_GRE 0x2F /* Generic Routing Encapsulation */
#define IP_PROTOCOL_MHRP 0x30 /* Mobile Host Routing Protocol */
#define IP_PROTOCOL_BNA 0x31 /* BNA */
#define IP_PROTOCOL_ESP 0x32 /* Encapsulating Security Payload */
#define IP_PROTOCOL_MOBILE 0x37 /* IP Mobility (Min Encap) */
#define IP_PROTOCOL_IPV6_ICMP 0x3A /* ICMP for IPv6 */
#define IP_PROTOCOL_IPV6_NONXT 0x3B /* No Next Header for IPv6 */
#define IP_PROTOCOL_IPV6_OPTS 0x3C /* Destination Options for IPv6 */
#define IP_PROTOCOL_IPCOMP 0x6C /* IP Payload Compression Protocol */
#define IP_PROTOCOL_L2TP 0x73 /* Layer Two Tunneling Protocol Version 3 */
#define IP_PROTOCOL_SMP 0x79 /* Simple Message Protocol */
#define IP_PROTOCOL_SCTP 0x84 /* Stream Control Transmission Protocol */
#define IP_PROTOCOL_SHIM6 0x8C /* Site Multihoming by IPv6 Intermediation */
/* IPv6 ICMP types */
#define IPV6_ICMP_TYPE_MLD 0x8F
#endif /* _IP_PROT__H_ */

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/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _IPV4__H_
#define _IPV4__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
#define IPV4_ADDR_LEN 4 /* bytes */
struct ipv4_hdr_t {
A_UINT8 ver_hdrlen; /* version and hdr length */
A_UINT8 tos; /* type of service */
A_UINT8 len[2]; /* total length */
A_UINT8 id[2];
A_UINT8 flags_fragoff[2]; /* flags and fragment offset field */
A_UINT8 ttl; /* time to live */
A_UINT8 protocol;
A_UINT8 hdr_checksum[2];
A_UINT8 src_addr[IPV4_ADDR_LEN];
A_UINT8 dst_addr[IPV4_ADDR_LEN];
};
#define IPV4_HDR_LEN (sizeof(struct ipv4_hdr_t))
#define IPV4_HDR_OFFSET_PROTOCOL (offsetof(struct ipv4_hdr_t, protocol))
#define IPV4_HDR_OFFSET_DST_ADDR (offsetof(struct ipv4_hdr_t, dst_addr[0]))
#endif /* _IPV4__H_ */

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target/inc/ol_fw_tx_dbg.h
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/*
* Copyright (c) 2012, 2014-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/**
* @file ol_fw_tx_dbg.h
*
* @details data structs used for uploading summary info about the FW's tx
*/
#ifndef _OL_FW_TX_DBG__H_
#define _OL_FW_TX_DBG__H_
/*
* Undef ATH_SUPPORT_FW_TX_DBG to remove the FW tx debug feature.
* Removing the FW tx debug feature saves a modest amount of program memory.
* The data memory allocation for the FW tx debug feature is controlled
* by the host --> target resource configuration parameters; even if
* ATH_SUPPORT_FW_TX_DBG is defined, no data memory will be allocated for
* the FW tx debug log unless the host --> target resource configuration
* specifies it.
*/
#define ATH_SUPPORT_FW_TX_DBG 1 /* enabled */
/* #undef ATH_SUPPORT_FW_TX_DBG / * disabled * / */
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#include <a_osapi.h> /* PREPACK, POSTPACK */
#endif
enum ol_fw_tx_dbg_log_mode {
ol_fw_tx_dbg_log_mode_wraparound, /* overwrite old data with new */
ol_fw_tx_dbg_log_mode_single, /* fill log once, then stop */
};
/*
* tx PPDU stats upload message header
*/
struct ol_fw_tx_dbg_ppdu_msg_hdr {
/* word 0 */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff
A_UINT8 mpdu_bytes_array_len; /* length of array of per-MPDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00
A_UINT8 msdu_bytes_array_len; /* length of array of per-MSDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000
A_UINT8 mpdu_msdus_array_len; /* length of array of per-MPDU MSDU counts */
A_UINT8 reserved;
/* word 1 */
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff
A_UINT32 microsec_per_tick; /* conversion for timestamp entries */
};
/*
* tx PPDU log element / stats upload message element
*/
struct ol_fw_tx_dbg_ppdu_base {
/* word 0 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff
A_UINT16 start_seq_num;
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000
A_UINT16 start_pn_lsbs;
/* word 1 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff
A_UINT32 num_bytes;
/* word 2 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff
A_UINT8 num_msdus;
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00
A_UINT8 num_mpdus;
A_UINT16
#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2
#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16
#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000
ext_tid : 5,
#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2
#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21
#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000
peer_id : 11;
/* word 3 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff
A_UINT32 timestamp_enqueue;
/* word 4 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff
A_UINT32 timestamp_completion;
/* word 5 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_lsbs;
/* word 6 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_msbs;
/* word 7 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_lsbs;
/* word 8 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_msbs;
/* word 9 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0
#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff
A_UINT8 rate_code;
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00
A_UINT8 rate_flags; /* includes dynamic bandwidth info */
#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9
#define OL_FW_TX_DBG_PPDU_TRIES_S 16
#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000
A_UINT8 tries;
#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9
#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24
#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000
A_UINT8 complete;
};
#endif /* _OL_FW_TX_DBG__H_ */

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target/inc/rtc_soc_reg.h
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target/inc/targaddrs.h
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/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __TARGADDRS_H__
#define __TARGADDRS_H__
#if defined(ATH_TARGET)
#include "soc_addrs.h"
#endif
#if !defined(ATH_TARGET)
#include "athstartpack.h"
#endif
/*
* SOC option bits, to enable/disable various features.
* By default, all option bits are 0.
* AR6004: These bits can be set in LOCAL_SCRATCH register 0.
* AR9888: These bits can be set in soc_core register SCRATCH_0.
*/
#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
/*
* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
* host_interest structure. It must match the address of the _host_interest
* symbol (see linker script).
*
* Host Interest is shared between Host and Target in order to coordinate
* between the two, and is intended to remain constant (with additions only
* at the end) across software releases.
*
* All addresses are available here so that it's possible to
* write a single binary that works with all Target Types.
* May be used in assembler code as well as C.
*/
#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
#define AR6003_HOST_INTEREST_ADDRESS 0x00540600
#define AR6004_HOST_INTEREST_ADDRESS 0x00400800
#define AR9888_HOST_INTEREST_ADDRESS 0x00400800
#define AR900B_HOST_INTEREST_ADDRESS 0x00400800
#define AR6320_HOST_INTEREST_ADDRESS 0x00400800
#define QCA9377_HOST_INTEREST_ADDRESS 0x00400800
#define AR6004_SOC_RESET_ADDRESS 0X00004000
#define AR6004_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
#if defined(AR6006_MEMORY_NEW_ARCH)
#define AR6006_HOST_INTEREST_ADDRESS 0x00428800
#else
#define AR6006_HOST_INTEREST_ADDRESS 0x00400800
#endif
#define AR6006_SOC_RESET_ADDRESS 0X00004000
#define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
#define HOST_INTEREST_MAX_SIZE 0x200
#if !defined(__ASSEMBLER__)
struct register_dump_s;
struct dbglog_hdr_s;
/*
* These are items that the Host may need to access
* via BMI or via the Diagnostic Window. The position
* of items in this structure must remain constant
* across firmware revisions!
*
* Types for each item must be fixed size across
* target and host platforms.
*
* More items may be added at the end.
*/
PREPACK64 struct host_interest_s {
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Save SW ROM version */
A_UINT32 hi_sw_rom_version; /* 0x0c */
/*
* General-purpose flag bits, similar to SOC_OPTION_* flags.
* Can be used by application rather than by OS.
*/
volatile A_UINT32 hi_option_flag; /* 0x10 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/* Start address of DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/* Host uses BE CPU or not */
A_UINT32 hi_be; /* 0x44 */
A_UINT32 hi_stack; /* normal stack *//* 0x48 */
A_UINT32 hi_err_stack; /* error stack *//* 0x4c */
A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
/*
* Indication of Board Data state:
* 0: board data is not yet initialized.
* 1: board data is initialized; unknown size
* >1: number of bytes of initialized board data (varies with board type)
*/
A_UINT32 hi_board_data_initialized; /* 0x58 */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
A_UINT32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
A_UINT32 hi_reset_flag_valid; /* 0xb8 */
A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
A_UINT32 hi_acs_flags; /* 0xc0 */
A_UINT32 hi_console_flags; /* 0xc4 */
A_UINT32 hi_nvram_state; /* 0xc8 */
volatile A_UINT32 hi_option_flag2; /* 0xcc */
/* If non-zero, override values sent to Host in WMI_READY event. */
A_UINT32 hi_sw_version_override; /* 0xd0 */
A_UINT32 hi_abi_version_override; /* 0xd4 */
/* Percentage of high priority RX traffic to total expected RX traffic -
* applicable only to ar6004 */
A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* test applications flags */
A_UINT32 hi_test_apps_related; /* 0xdc */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
A_UINT32 hi_cal_data; /* 0xe4 */
/* Number of packet log buffers */
volatile A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */
/* wow extension configuration */
A_UINT32 hi_wow_ext_config; /* 0xec */
A_UINT32 hi_pwr_save_flags; /* 0xf0 */
/* Spatial Multiplexing Power Save (SMPS) options */
A_UINT32 hi_smps_options; /* 0xf4 */
/* Interconnect-specific state */
A_UINT32 hi_interconnect_state; /* 0xf8 */
/* Coex configuration flags */
A_UINT32 hi_coex_config; /* 0xfc */
/* Early allocation support */
A_UINT32 hi_early_alloc; /* 0x100 */
/* FW swap field */
/* Bits of this 32bit word will be used to pass specific swap
instruction to FW */
/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
FW will not swap TX descriptor. Meaning packets are formed
on the target processor. */
/* Bit 1 -- TBD */
A_UINT32 hi_fw_swap; /* 0x104 */
/* global arenas pointer address, used by host driver debug */
A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */
/* allocated bytes of DRAM use by allocated */
A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */
/* remaining bytes of DRAM */
A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */
/* memory track count, configured by host */
A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */
/* minidump buffer */
A_UINT32 hi_minidump; /* 0x118 */
/* bdata's sig and key addr */
A_UINT32 hi_bd_sig_key; /* 0x11c */
} POSTPACK64;
/* bitmap for hi_test_apps_related */
#define HI_TEST_APPS_TESTSCRIPT_LOADED 0x00000001
#define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_NUM_DEV_LSB 0x200
#define HI_OPTION_NUM_DEV_MSB 0x800
#define HI_OPTION_DEV_MODE_LSB 0x1000
#define HI_OPTION_DEV_MODE_MSB 0x8000000
#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before
* sending WMI ready event to host */
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */
#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
/* 2 bits of hi_option flag are usedto represent 4 submodes */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
/* Num dev Mask */
#define HI_OPTION_NUM_DEV_MASK 0x7
#define HI_OPTION_NUM_DEV_SHIFT 0x9
/* firmware bridging */
#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
/* Fw Mode/SubMode Mask
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|||-------------------------------------------------------------------------------|
*/
#define HI_OPTION_FW_MODE_BITS 0x2
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0xC
#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
#define HI_OPTION_FW_SUBMODE_BITS 0x2
#define HI_OPTION_FW_SUBMODE_MASK 0x3
#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
/* hi_option_flag2 options */
#define HI_OPTION_OFFLOAD_AMSDU 0x01
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature */
#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
#define HI_OPTION_RF_KILL_SHIFT 0x2
#define HI_OPTION_RF_KILL_MASK 0x1
#define HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX 0x20
#define HTT_TGT_DEBUG_TX_COMPL_IDX_VALUE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
/* AR9888 1.0 only. Enable/disable CDC max perf support from host */
#define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20
#define CDC_MAX_PERF_WAR_ENABLED() \
(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
#define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU. */
#define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */
/* This bit is to enable BE low latency for some customers.
* The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).
*/
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100
#define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */
#define GPIO_WAKEUP_ENABLED() \
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
/* hi_reset_flag */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
#define HI_RESET_FLAG_WARM_RESET 0x20
/* define hi_fw_swap bits */
#define HI_DESC_IN_FW_BIT 0x01
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
#define ON_RESET_FLAGS_VALID() \
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_INVALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = 0)
#define ON_RESET_PRESERVE_APP_START() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_HOST_INTEREST() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
#define ON_RESET_PRESERVE_ROMDATA() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
#define ON_RESET_PRESERVE_BOOT_INFO() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
#define ON_RESET_WARM_RESET() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
/* host CPU endianness */
#define HOST_ON_BE_CPU() \
(HOST_INTEREST->hi_be)
/* AP nart no swap descriptor flag. Decsriptors are created
* on the target processor.
*/
#define DESC_IN_FW() \
(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
/* redefine for hi_acs_flags since no product ever use it
* NOTE:
* This flag was only used in AR6004 for a customer project that has
* been canceled, we are reusing it to avoid extending the Host interest
* area.
* BIT Range Meaning
* --------- ----------------------------------
* 0 HOST wants to swap MBOX usage
* 1 HOST supports HTT reduced tx completion
* 2 HOST supports HTT alternate credit size for data frames
* 15..3 reserved for HOST
* 16 FW set it before sending HTC_Ready to indicate MBOX swap is done
* 17 same as above but to indicate HTT reduced tx completion capability
* 31..18 reserved for FW
*/
/* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0)
/* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1)
/* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
/* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16)
/* FW support HTT reduced tx completion */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17)
/* CONSOLE FLAGS
*
* Bit Range Meaning
* --------- --------------------------------
* 2..0 UART ID (0 = Default)
* 3 Baud Select (0 = 9600, 1 = 115200)
* 30..4 Reserved
* 31 Enable Console
*
* */
#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
#define HI_CONSOLE_FLAGS_UART_SHIFT 0
#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
/* SM power save options */
#define HI_SMPS_ALLOW_MASK (0x00000001)
#define HI_SMPS_MODE_MASK (0x00000002)
#define HI_SMPS_MODE_STATIC (0x00000000)
#define HI_SMPS_MODE_DYNAMIC (0x00000002)
#define HI_SMPS_DISABLE_AUTO_MODE (0x00000004)
#define HI_SMPS_DATA_THRESH_MASK (0x000007f8)
#define HI_SMPS_DATA_THRESH_SHIFT (3)
#define HI_SMPS_RSSI_THRESH_MASK (0x0007f800)
#define HI_SMPS_RSSI_THRESH_SHIFT (11)
#define HI_SMPS_LOWPWR_CM_MASK (0x00380000)
#define HI_SMPS_LOWPWR_CM_SHIFT (15)
#define HI_SMPS_HIPWR_CM_MASK (0x03c00000)
#define HI_SMPS_HIPWR_CM_SHIFT (19)
#define HOST_INTEREST_SMPS_GET_MODE() (HOST_INTEREST->hi_smps_options & HI_SMPS_MODE_MASK)
#define HOST_INTEREST_SMPS_GET_DATA_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_DATA_THRESH_MASK) >> HI_SMPS_DATA_THRESH_SHIFT)
#define HOST_INTEREST_SMPS_SET_DATA_THRESH(x) (((x) << HI_SMPS_DATA_THRESH_SHIFT) & HI_SMPS_DATA_THRESH_MASK)
#define HOST_INTEREST_SMPS_GET_RSSI_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_RSSI_THRESH_MASK) >> HI_SMPS_RSSI_THRESH_SHIFT)
#define HOST_INTEREST_SMPS_SET_RSSI_THRESH(x) (((x) << HI_SMPS_RSSI_THRESH_SHIFT) & HI_SMPS_RSSI_THRESH_MASK)
#define HOST_INTEREST_SMPS_SET_LOWPWR_CM() ((HOST_INTEREST->hi_smps_options & HI_SMPS_LOWPWR_CM_MASK) >> HI_SMPS_LOWPWR_CM_SHIFT)
#define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT)
#define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE)
/* WOW Extension configuration
*
* Bit Range Meaning
* --------- --------------------------------
* 8..0 Size of each WOW pattern (max 511)
* 15..9 Number of patterns per list (max 127)
* 17..16 Number of lists (max 4)
* 30..18 Reserved
* 31 Enabled
*
* set values (except enable) to zeros for default settings
*
* */
#define HI_WOW_EXT_ENABLED_MASK (1 << 31)
#define HI_WOW_EXT_NUM_LIST_SHIFT 16
#define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT)
#define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9
#define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT)
#define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0
#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
#define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \
((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \
(((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \
(((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
#define HI_WOW_EXT_GET_NUM_LISTS(config) \
(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
/*
* Early allocation configuration
* Support RAM bank configuration before BMI done and this eases the memory
* allocation at very early stage
* Bit Range Meaning
* --------- ----------------------------------
* [0:3] number of bank assigned to be IRAM
* [4:15] reserved
* [16:31] magic number
*
* Note:
* 1. target firmware would check magic number and if it's a match, firmware
* would consider the bits[0:15] are valid and base on that to calculate
* the end of DRAM. Early allocation would be located at that area and
* may be reclaimed when necesary
* 2. if no magic number is found, early allocation would happen at "_end"
* symbol of ROM which is located before the app-data and might NOT be
* re-claimable. If this is adopted, link script should keep this in
* mind to avoid data corruption.
*/
#define HI_EARLY_ALLOC_MAGIC 0x6d8a
#define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000
#define HI_EARLY_ALLOC_MAGIC_SHIFT 16
#define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f
#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
#define HI_EARLY_ALLOC_VALID() \
((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
== (HI_EARLY_ALLOC_MAGIC))
#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
/*
* Intended for use by Host software, this macro returns the Target RAM
* address of any item in the host_interest structure.
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
*/
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
((HOST_INTEREST->hi_pktlog_num_buffers))
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
#define LF_TIMER_STABILIZATION_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
#define IS_AMSDU_OFFLAOD_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
#define HOST_INTEREST_DFS_IS_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
#define HOST_INTEREST_EARLY_CFG_DONE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
/*power save flag bit definitions*/
#define HI_PWR_SAVE_LPL_ENABLED 0x1
/*b1-b3 reserved*/
/*b4-b5 : dev0 LPL type : 0 - none
1- Reduce Pwr Search
2- Reduce Pwr Listen*/
/*b6-b7 : dev1 LPL type and so on for Max 8 devices*/
#define HI_PWR_SAVE_LPL_DEV0_LSB 4
#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
/*power save related utility macros*/
#define HI_LPL_ENABLED() \
((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
#define HI_DEV_LPL_TYPE_GET(_devix) \
(HOST_INTEREST->hi_pwr_save_flags & \
((HI_PWR_SAVE_LPL_DEV_MASK) << \
(HI_PWR_SAVE_LPL_DEV0_LSB + \
(_devix)*2)))
#define HOST_INTEREST_SMPS_IS_ALLOWED() \
((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6004_VTOP(vaddr) (vaddr)
#define AR6006_VTOP(vaddr) (vaddr)
#define AR9888_VTOP(vaddr) (vaddr)
#define AR6320_VTOP(vaddr) (vaddr)
#define AR900B_VTOP(vaddr) (vaddr)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
0)))))))
#define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
0)))))))
#define AR6002_BOARD_DATA_SZ 768
#define AR6002_BOARD_EXT_DATA_SZ 0
#define AR6003_BOARD_DATA_SZ 1024
/* Reserve 1024 bytes for extended board data */
#if defined(AR6002_REV43)
#define AR6003_BOARD_EXT_DATA_SZ 1024
#else
#define AR6003_BOARD_EXT_DATA_SZ 768
#endif
#define AR6004_BOARD_DATA_SZ 7168
#define AR6004_BOARD_EXT_DATA_SZ 0
#define AR9888_BOARD_DATA_SZ 7168
#define AR9888_BOARD_EXT_DATA_SZ 0
#define AR6320_BOARD_DATA_SZ 8192
#define AR6320_BOARD_EXT_DATA_SZ 0
#define QCA9377_BOARD_DATA_SZ 8192
#define QCA9377_BOARD_EXT_DATA_SZ 0
#define AR900B_BOARD_DATA_SZ 7168
#define AR900B_BOARD_EXT_DATA_SZ 0
#define AR6003_REV3_APP_START_OVERRIDE 0x946100
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74
#define AR6003_REV3_RAM_RESERVE_SIZE 4096
#define AR6004_REV1_BOARD_DATA_ADDRESS 0x423900
#define AR6004_REV1_RAM_RESERVE_SIZE 19456
#define AR6004_REV1_DATASET_PATCH_ADDRESS 0x425294
#define AR6004_REV2_BOARD_DATA_ADDRESS 0x426400
#define AR6004_REV2_RAM_RESERVE_SIZE 7168
#define AR6004_REV2_DATASET_PATCH_ADDRESS 0x435294
#define AR6004_REV5_BOARD_DATA_ADDRESS 0x436400
#define AR6004_REV5_RAM_RESERVE_SIZE 7168
#define AR6004_REV5_DATASET_PATCH_ADDRESS 0x437860
/* Reserve 4K for OTA test script */
#define AR6004_REV1_RAM_RESERVE_SIZE_FOR_TEST_SCRIPT 4096
#define AR6004_REV1_TEST_SCRIPT_ADDRESS 0x422900
/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
#define AR6003_FETCH_TARG_REGS_COUNT 64
#define AR6004_FETCH_TARG_REGS_COUNT 64
#define AR9888_FETCH_TARG_REGS_COUNT 64
#define AR6320_FETCH_TARG_REGS_COUNT 64
#define AR900B_FETCH_TARG_REGS_COUNT 64
#endif /* !__ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __TARGADDRS_H__ */

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target/inc/targcfg.h
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __TARGCFG_H__
#define __TARGCFG_H__
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#endif
typedef struct _targcfg_t {
A_UINT32 num_vdev;
A_UINT32 num_peers;
A_UINT32 num_peer_ast;
A_UINT32 num_peer_keys;
A_UINT32 num_peer_tid;
A_UINT32 num_mcast_keys;
A_UINT32 num_tx;
A_UINT32 num_rx;
A_UINT32 num_mgmt_tx;
A_UINT32 num_mgmt_rx;
A_UINT32 tx_chain_mask;
A_UINT32 rx_chain_mask;
A_UINT32 override; /* Override target with the values supplied above */
} targcfg_t;
#endif /* __TARGCFG_H__ */

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target/inc/wal_rx_desc.h
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/*
* Copyright (c) 2011-2012, 2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WAL_RX_DESC__H_
#define _WAL_RX_DESC__H_
#if defined(ATH_TARGET)
#include <athdefs.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
/*
* As this header is used by host also,
* and host will access target registers by target reg tbl,
* so disable direct-reference here for host.
*
*/
#if !defined(ATH_PERF_PWR_OFFLOAD)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
#include <hw/interface/rx_location_info.h>
#include <hw/interface/rx_pkt_end.h>
#include <hw/interface/rx_phy_ppdu_end.h>
#include <hw/interface/rx_timing_offset.h>
#include <hw/interface/rx_location_info.h>
#include <hw/tlv/rx_attention.h>
#include <hw/tlv/rx_frag_info.h>
#include <hw/tlv/rx_msdu_start.h>
#include <hw/tlv/rx_msdu_end.h>
#include <hw/tlv/rx_mpdu_start.h>
#include <hw/tlv/rx_mpdu_end.h>
#include <hw/tlv/rx_ppdu_start.h>
#include <hw/tlv/rx_ppdu_end.h>
#else
/* HW rx descriptor definitions */
#include <mac_descriptors/rx_attention.h>
#include <mac_descriptors/rx_frag_info.h>
#include <mac_descriptors/rx_msdu_start.h>
#include <mac_descriptors/rx_msdu_end.h>
#include <mac_descriptors/rx_mpdu_start.h>
#include <mac_descriptors/rx_mpdu_end.h>
#include <mac_descriptors/rx_ppdu_start.h>
#include <mac_descriptors/rx_ppdu_end.h>
#endif
/*
* This struct defines the basic descriptor information, which is
* written by the 11ac HW MAC into the WAL's rx status descriptor
* ring.
*/
struct hw_rx_desc_base {
struct rx_attention attention;
struct rx_frag_info frag_info;
struct rx_mpdu_start mpdu_start;
struct rx_msdu_start msdu_start;
struct rx_msdu_end msdu_end;
struct rx_mpdu_end mpdu_end;
struct rx_ppdu_start ppdu_start;
struct rx_ppdu_end ppdu_end;
};
#endif
#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
/*
* This struct defines the basic MSDU rx descriptor created by FW.
*/
struct fw_rx_desc_base {
union {
struct {
A_UINT8 discard:1,
forward:1,
any_err:1,
dup_err:1,
ipa_ind:1,
inspect:1,
extension:2;
} bits;
A_UINT8 val;
} u;
};
#define FW_RX_DESC_DISCARD_M 0x1
#define FW_RX_DESC_DISCARD_S 0
#define FW_RX_DESC_FORWARD_M 0x2
#define FW_RX_DESC_FORWARD_S 1
#define FW_RX_DESC_ANY_ERR_M 0x4
#define FW_RX_DESC_ANY_ERR_S 2
#define FW_RX_DESC_DUP_ERR_M 0x8
#define FW_RX_DESC_DUP_ERR_S 3
#define FW_RX_DESC_INSPECT_M 0x20
#define FW_RX_DESC_INSPECT_S 5
#define FW_RX_DESC_EXT_M 0xc0
#define FW_RX_DESC_EXT_S 6
#define FW_RX_DESC_CNT_2_BYTES(_fw_desc_cnt) (_fw_desc_cnt)
enum {
FW_RX_DESC_EXT_NONE = 0,
FW_RX_DESC_EXT_LRO_ONLY,
FW_RX_DESC_EXT_LRO_AND_OTHER,
FW_RX_DESC_EXT_OTHER
};
#define FW_RX_DESC_DISCARD_GET(_var) \
(((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
#define FW_RX_DESC_DISCARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
#define FW_RX_DESC_FORWARD_GET(_var) \
(((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
#define FW_RX_DESC_FORWARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
#define FW_RX_DESC_INSPECT_GET(_var) \
(((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
#define FW_RX_DESC_INSPECT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
#define FW_RX_DESC_EXT_GET(_var) \
(((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
#define FW_RX_DESC_EXT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_EXT_S))
/*
* This struct defines TCP_CHKSUM_OFFLOAD bit fields which are needed by host.
*/
struct fw_rx_msdu_info {
union {
/*
* The "bits" struct defines the flags in fw_rx_msdu_info used
* during regular operation.
*/
struct {
A_UINT8 tcp_udp_chksum_fail:1, /* for tcp checksum offload use */
ip_chksum_fail:1,
ipv6_proto:1,
tcp_proto:1,
udp_proto:1,
ip_frag:1,
first_wakeup:1,
reserved:1;
} bits;
/*
* The "mon" struct defines the flags in fw_rx_msdu_info used
* during monitor mode.
*/
struct {
A_UINT8 last_frag:1,
reserved:7;
} mon;
A_UINT8 val;
} u;
};
/* regular operation flags */
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M 0x1
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S 0
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M 0x2
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S 1
#define FW_RX_MSDU_INFO_IPV6_PROTO_M 0x4
#define FW_RX_MSDU_INFO_IPV6_PROTO_S 2
#define FW_RX_MSDU_INFO_TCP_PROTO_M 0x8
#define FW_RX_MSDU_INFO_TCP_PROTO_S 3
#define FW_RX_MSDU_INFO_UDP_PROTO_M 0x10
#define FW_RX_MSDU_INFO_UDP_PROTO_S 4
#define FW_RX_MSDU_INFO_IP_FRAG_M 0x20
#define FW_RX_MSDU_INFO_IP_FRAG_S 5
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_S 6
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IPV6_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
#define FW_RX_MSDU_INFO_IPV6_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
#define FW_RX_MSDU_INFO_TCP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
#define FW_RX_MSDU_INFO_TCP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
#define FW_RX_MSDU_INFO_UDP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
#define FW_RX_MSDU_INFO_UDP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
#define FW_RX_MSDU_INFO_IP_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
#define FW_RX_MSDU_INFO_IP_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
/* monitor mode flags */
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_M 0x1
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_S 0
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
#endif /* _WAL_RX_DESC__H_ */

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/*
* Copyright (c) 2004-2010, 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __WLAN_DEFS_H__
#define __WLAN_DEFS_H__
/* A_COMPILE_TIME_ASSERT */
#include <a_osapi.h>
/*
* This file contains WLAN definitions that may be used across both
* Host and Target software.
*/
/*
* MAX_SPATIAL_STREAM should be defined in a fwconfig_xxx.h file,
* but for now provide a default value here in case it's not defined
* in the fwconfig_xxx.h file.
*/
#define NUM_SPATIAL_STREAM 2
#ifndef MAX_SPATIAL_STREAM
#define MAX_SPATIAL_STREAM 3
#endif
/*
* MAX_SPATIAL_STREAM_ANY -
* what is the largest number of spatial streams that any target supports
*/
#define MAX_SPATIAL_STREAM_ANY 4
#ifndef CONFIG_160MHZ_SUPPORT
#define CONFIG_160MHZ_SUPPORT 0
#endif
#ifndef SUPPORT_11AX
#define SUPPORT_11AX 0 /* 11ax not supported by default */
#endif
/* defines to set Packet extension values which can be 0 us, 8 us or 16 us */
/* NOTE: Below values cannot be changed without breaking WMI Compatibility */
#define MAX_HE_NSS 8
#define MAX_HE_MODULATION 8
#define MAX_HE_RU 4
#define HE_MODULATION_NONE 7
#define HE_PET_0_USEC 0
#define HE_PET_8_USEC 1
#define HE_PET_16_USEC 2
typedef enum {
MODE_11A = 0, /* 11a Mode */
MODE_11G = 1, /* 11b/g Mode */
MODE_11B = 2, /* 11b Mode */
MODE_11GONLY = 3, /* 11g only Mode */
MODE_11NA_HT20 = 4, /* 11a HT20 mode */
MODE_11NG_HT20 = 5, /* 11g HT20 mode */
MODE_11NA_HT40 = 6, /* 11a HT40 mode */
MODE_11NG_HT40 = 7, /* 11g HT40 mode */
MODE_11AC_VHT20 = 8,
MODE_11AC_VHT40 = 9,
MODE_11AC_VHT80 = 10,
MODE_11AC_VHT20_2G = 11,
MODE_11AC_VHT40_2G = 12,
MODE_11AC_VHT80_2G = 13,
#if CONFIG_160MHZ_SUPPORT
MODE_11AC_VHT80_80 = 14,
MODE_11AC_VHT160 = 15,
#endif
#if SUPPORT_11AX
MODE_11AX_HE20 = 16,
MODE_11AX_HE40 = 17,
MODE_11AX_HE80 = 18,
MODE_11AX_HE80_80 = 19,
MODE_11AX_HE160 = 20,
MODE_11AX_HE20_2G = 21,
MODE_11AX_HE40_2G = 22,
MODE_11AX_HE80_2G = 23,
#endif
/*
* MODE_UNKNOWN should not be used within the host / target interface.
* Thus, it is permissible for ODE_UNKNOWN to be conditionally-defined,
* taking different values when compiling for different targets.
*/
MODE_UNKNOWN,
MODE_UNKNOWN_NO_160MHZ_SUPPORT = 14, /* not needed? */
/* MODE_UNKNOWN_NO_11AX_SUPPORT = 16,*/ /* not needed? */
/* MODE_UNKNOWN_11AX_SUPPORT = 24,*/ /* not needed? */
MODE_UNKNOWN_160MHZ_SUPPORT = MODE_UNKNOWN, /* not needed? */
#ifdef ATHR_WIN_NWF
PHY_MODE_MAX = MODE_UNKNOWN,
PHY_MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT,
PHY_MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT,
#else
MODE_MAX = MODE_UNKNOWN,
MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT,
MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT,
#endif
} WLAN_PHY_MODE;
#if CONFIG_160MHZ_SUPPORT == 0
A_COMPILE_TIME_ASSERT(
mode_unknown_value_consistency_Check,
MODE_UNKNOWN == MODE_UNKNOWN_NO_160MHZ_SUPPORT);
#else
A_COMPILE_TIME_ASSERT(
mode_unknown_value_consistency_Check,
MODE_UNKNOWN == MODE_UNKNOWN_160MHZ_SUPPORT);
#endif
typedef enum {
VHT_MODE_NONE = 0, /* NON VHT Mode, e.g., HT, DSSS, CCK */
VHT_MODE_20M = 1,
VHT_MODE_40M = 2,
VHT_MODE_80M = 3,
VHT_MODE_160M = 4
} VHT_OPER_MODE;
typedef enum {
WLAN_11A_CAPABILITY = 1,
WLAN_11G_CAPABILITY = 2,
WLAN_11AG_CAPABILITY = 3,
} WLAN_CAPABILITY;
#if (NUM_SPATIAL_STREAM > 3)
#define A_RATEMASK A_UINT64
#else
#define A_RATEMASK A_UINT32
#endif
#define A_RATEMASK_NUM_OCTET (sizeof (A_RATEMASK))
#define A_RATEMASK_NUM_BITS ((sizeof (A_RATEMASK)) << 3)
#if CONFIG_160MHZ_SUPPORT != 0
#define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \
((mode) == MODE_11AC_VHT40) || \
((mode) == MODE_11AC_VHT80) || \
((mode) == MODE_11AC_VHT80_80) || \
((mode) == MODE_11AC_VHT160))
#else
#define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \
((mode) == MODE_11AC_VHT40) || \
((mode) == MODE_11AC_VHT80))
#endif
#define IS_MODE_HE(mode) (((mode) == MODE_11AX_HE20) || \
((mode) == MODE_11AX_HE40) || \
((mode) == MODE_11AX_HE80) || \
((mode) == MODE_11AX_HE80_80) || \
((mode) == MODE_11AX_HE160) || \
((mode) == MODE_11AX_HE20_2G) || \
((mode) == MODE_11AX_HE40_2G) || \
((mode) == MODE_11AX_HE80_2G))
#define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \
((mode) == MODE_11AC_VHT40_2G) || \
((mode) == MODE_11AC_VHT80_2G))
#define IS_MODE_11A(mode) (((mode) == MODE_11A) || \
((mode) == MODE_11NA_HT20) || \
((mode) == MODE_11NA_HT40) || \
(IS_MODE_VHT(mode)))
#define IS_MODE_11B(mode) ((mode) == MODE_11B)
#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \
((mode) == MODE_11GONLY) || \
((mode) == MODE_11NG_HT20) || \
((mode) == MODE_11NG_HT40) || \
(IS_MODE_VHT_2G(mode)))
#define IS_MODE_11GN(mode) (((mode) == MODE_11NG_HT20) || \
((mode) == MODE_11NG_HT40))
#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
enum {
/* 11a channels */
REGDMN_MODE_11A = 0x00000001,
/* 11a turbo-only channels */
REGDMN_MODE_TURBO = 0x00000002,
/* 11b channels */
REGDMN_MODE_11B = 0x00000004,
/* 11g channels (OFDM only) */
REGDMN_MODE_PUREG = 0x00000008,
/* XXX historical */
REGDMN_MODE_11G = 0x00000008,
/* 11g+Turbo channels */
REGDMN_MODE_108G = 0x00000020,
/* 11a+Turbo channels */
REGDMN_MODE_108A = 0x00000040,
/* XR channels */
REGDMN_MODE_XR = 0x00000100,
/* 11A half rate channels */
REGDMN_MODE_11A_HALF_RATE = 0x00000200,
/* 11A quarter rate channels */
REGDMN_MODE_11A_QUARTER_RATE = 0x00000400,
/* 11N-G HT20 channels */
REGDMN_MODE_11NG_HT20 = 0x00000800,
/* 11N-A HT20 channels */
REGDMN_MODE_11NA_HT20 = 0x00001000,
/* 11N-G HT40 + channels */
REGDMN_MODE_11NG_HT40PLUS = 0x00002000,
/* 11N-G HT40 - channels */
REGDMN_MODE_11NG_HT40MINUS = 0x00004000,
/* 11N-A HT40 + channels */
REGDMN_MODE_11NA_HT40PLUS = 0x00008000,
/* 11N-A HT40 - channels */
REGDMN_MODE_11NA_HT40MINUS = 0x00010000,
/* 5Ghz, VHT20 */
REGDMN_MODE_11AC_VHT20 = 0x00020000,
/* 5Ghz, VHT40 + channels */
REGDMN_MODE_11AC_VHT40PLUS = 0x00040000,
/* 5Ghz VHT40 - channels */
REGDMN_MODE_11AC_VHT40MINUS = 0x00080000,
/* 5Ghz, VHT80 channels */
REGDMN_MODE_11AC_VHT80 = 0x000100000,
REGDMN_MODE_11AC_VHT20_2G = 0x000200000, /* 2Ghz, VHT20 */
REGDMN_MODE_11AC_VHT40_2G = 0x000400000, /* 2Ghz, VHT40 */
REGDMN_MODE_11AC_VHT80_2G = 0x000800000, /* 2Ghz, VHT80 */
REGDMN_MODE_11AC_VHT160 = 0x001000000, /* 5Ghz, VHT160 */
REGDMN_MODE_11AC_VHT40_2GPLUS = 0x002000000, /* 2Ghz, VHT40+ */
REGDMN_MODE_11AC_VHT40_2GMINUS = 0x004000000, /* 2Ghz, VHT40- */
REGDMN_MODE_11AC_VHT80_80 = 0x008000000, /* 5GHz, VHT80+80 */
};
#define REGDMN_MODE_ALL (0xFFFFFFFF) /* REGDMN_MODE_ALL is defined out of the enum
* to prevent the ARM compile "warning #66:
* enumeration value is out of int range"
* Anyway, this is a BIT-OR of all possible values.
*/
#define REGDMN_CAP1_CHAN_HALF_RATE 0x00000001
#define REGDMN_CAP1_CHAN_QUARTER_RATE 0x00000002
#define REGDMN_CAP1_CHAN_HAL49GHZ 0x00000004
/* regulatory capabilities */
#define REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
#define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
#define REGDMN_EEPROM_EEREGCAP_EN_KK_U2 0x0100
#define REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
#define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
#define REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_HAL_REG_CAPABILITIES */
A_UINT32 eeprom_rd; /* regdomain value specified in EEPROM */
A_UINT32 eeprom_rd_ext; /* regdomain */
A_UINT32 regcap1; /* CAP1 capabilities bit map. */
A_UINT32 regcap2; /* REGDMN EEPROM CAP. */
A_UINT32 wireless_modes; /* REGDMN MODE */
A_UINT32 low_2ghz_chan;
A_UINT32 high_2ghz_chan;
A_UINT32 low_5ghz_chan;
A_UINT32 high_5ghz_chan;
} HAL_REG_CAPABILITIES;
/*
* Used to update rate-control logic with the status of the tx-completion.
* In host-based implementation of the rate-control feature, this struture is used to
* create the payload for HTT message/s from target to host.
*/
typedef struct {
A_UINT8 rateCode;
A_UINT8 flags;
} RATE_CODE;
typedef struct {
RATE_CODE ptx_rc; /* rate code, bw, chain mask sgi */
A_UINT8 reserved[2];
A_UINT32 flags; /* Encodes information such as excessive
retransmission, aggregate, some info
from .11 frame control,
STBC, LDPC, (SGI and Tx Chain Mask
are encoded in ptx_rc->flags field),
AMPDU truncation (BT/time based etc.),
RTS/CTS attempt */
A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */
A_UINT32 num_retries; /* Total # of transmission attempt for this rate */
A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */
A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */
A_UINT32 time_stamp; /* ACK timestamp (helps determine age) */
A_UINT32 is_probe; /* Valid if probing. Else, 0 */
A_UINT32 ba_win_size; /* b'7..b0, block Ack Window size, b'31..b8 Resvd */
A_UINT32 failed_ba_bmap_0_31; /* failed BA bitmap 0..31 */
A_UINT32 failed_ba_bmap_32_63; /* failed BA bitmap 32..63 */
A_UINT32 bmap_tried_0_31; /* enqued bitmap 0..31 */
A_UINT32 bmap_tried_32_63; /* enqued bitmap 32..63 */
} RC_TX_DONE_PARAMS;
#define RC_SET_TX_DONE_INFO(_dst, _rc, _f, _nq, _nr, _nf, _rssi, _ts) \
do { \
(_dst).ptx_rc.rateCode = (_rc).rateCode; \
(_dst).ptx_rc.flags = (_rc).flags; \
(_dst).flags = (_f); \
(_dst).num_enqued = (_nq); \
(_dst).num_retries = (_nr); \
(_dst).num_failed = (_nf); \
(_dst).ack_rssi = (_rssi); \
(_dst).time_stamp = (_ts); \
} while (0)
#define RC_SET_TXBF_DONE_INFO(_dst, _f) \
do { \
(_dst).flags |= (_f); \
} while (0)
/* NOTE: NUM_DYN_BW and NUM_SCHED_ENTRIES cannot be changed without breaking WMI Compatibility */
#define NUM_SCHED_ENTRIES 2
#define NUM_DYN_BW_MAX 4
/* Some products only use 20/40/80; some use 20/40/80/160 */
#ifndef NUM_DYN_BW
/* default: support up through 80 MHz */
#define NUM_DYN_BW 3
#endif
#define NUM_DYN_BW_MASK 0x3
#define PROD_SCHED_BW_ENTRIES (NUM_SCHED_ENTRIES * NUM_DYN_BW)
typedef A_UINT8 A_RATE;
#if NUM_DYN_BW > 4
/* Extend rate table module first*/
#error "Extend rate table module first"
#endif
#define MAX_PEERS 32
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
typedef struct {
A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_UINT16 flags[NUM_SCHED_ENTRIES][NUM_DYN_BW];
A_RATE rix[NUM_SCHED_ENTRIES][NUM_DYN_BW];
A_UINT8 tpc[NUM_SCHED_ENTRIES][NUM_DYN_BW];
A_UINT32 antmask[NUM_SCHED_ENTRIES];
A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_UINT16 txbf_cv_len;
A_UINT32 txbf_cv_ptr;
A_UINT16 txbf_flags;
A_UINT16 txbf_cv_size;
A_UINT8 txbf_nc_idx;
A_UINT8 tries[NUM_SCHED_ENTRIES];
A_UINT8 bw_mask[NUM_SCHED_ENTRIES];
A_UINT8 max_bw[NUM_SCHED_ENTRIES];
A_UINT8 num_sched_entries;
A_UINT8 paprd_mask;
A_UINT8 rts_rix;
A_UINT8 sh_pream;
A_UINT8 min_spacing_1_4_us;
A_UINT8 fixed_delims;
A_UINT8 bw_in_service;
A_RATE probe_rix;
A_UINT8 num_valid_rates;
A_UINT8 rtscts_tpc;
A_UINT8 dd_profile;
} RC_TX_RATE_SCHEDULE;
#else
typedef struct {
A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_UINT32 antmask[NUM_SCHED_ENTRIES];
A_UINT32 txbf_cv_ptr;
A_UINT16 txbf_cv_len;
A_UINT8 tries[NUM_SCHED_ENTRIES];
A_UINT8 num_valid_rates;
A_UINT8 paprd_mask;
A_UINT8 rts_rix;
A_UINT8 sh_pream;
A_UINT8 min_spacing_1_4_us;
A_UINT8 fixed_delims;
A_UINT8 bw_in_service;
A_RATE probe_rix;
} RC_TX_RATE_SCHEDULE;
#endif
typedef struct {
A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES];
A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES];
#ifdef DYN_TPC_ENABLE
A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES];
#endif
#ifdef SECTORED_ANTENNA
A_UINT32 antmask[NUM_SCHED_ENTRIES];
#endif
A_UINT8 tries[NUM_SCHED_ENTRIES];
A_UINT8 num_valid_rates;
A_UINT8 rts_rix;
A_UINT8 sh_pream;
A_UINT8 bw_in_service;
A_RATE probe_rix;
A_UINT8 dd_profile;
} RC_TX_RATE_INFO;
/*
* Temporarily continue to provide the WHAL_RC_INIT_RC_MASKS def in wlan_defsh
* for older targets.
* The WHAL_RX_INIT_RC_MASKS macro def needs to be moved into ratectrl_11ac.h
* for all targets, but until this is complete, the WHAL_RC_INIT_RC_MASKS def
* will be maintained here in its old location.
*/
#if CONFIG_160MHZ_SUPPORT == 0
#define WHAL_RC_INIT_RC_MASKS(_rm) do { \
_rm[WHAL_RC_MASK_IDX_NON_HT] = A_RATEMASK_OFDM_CCK; \
_rm[WHAL_RC_MASK_IDX_HT_20] = A_RATEMASK_HT_20; \
_rm[WHAL_RC_MASK_IDX_HT_40] = A_RATEMASK_HT_40; \
_rm[WHAL_RC_MASK_IDX_VHT_20] = A_RATEMASK_VHT_20; \
_rm[WHAL_RC_MASK_IDX_VHT_40] = A_RATEMASK_VHT_40; \
_rm[WHAL_RC_MASK_IDX_VHT_80] = A_RATEMASK_VHT_80; \
} while (0)
#endif
/**
* strucutre describing host memory chunk.
*/
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */
/** id of the request that is passed up in service ready */
A_UINT32 req_id;
/** the physical address the memory chunk */
A_UINT32 ptr;
/** size of the chunk */
A_UINT32 size;
} wlan_host_memory_chunk;
#define NUM_UNITS_IS_NUM_VDEVS 0x1
#define NUM_UNITS_IS_NUM_PEERS 0x2
#define NUM_UNITS_IS_NUM_ACTIVE_PEERS 0x4
/* request host to allocate memory contiguously */
#define REQ_TO_HOST_FOR_CONT_MEMORY 0x8
/**
* structure used by FW for requesting host memory
*/
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_wlan_host_mem_req */
/** ID of the request */
A_UINT32 req_id;
/** size of the of each unit */
A_UINT32 unit_size;
/**
* flags to indicate that
* the number units is dependent
* on number of resources(num vdevs num peers .. etc)
*/
A_UINT32 num_unit_info;
/*
* actual number of units to allocate . if flags in the num_unit_info
* indicate that number of units is tied to number of a particular
* resource to allocate then num_units filed is set to 0 and host
* will derive the number units from number of the resources it is
* requesting.
*/
A_UINT32 num_units;
} wlan_host_mem_req;
typedef enum {
IGNORE_DTIM = 0x01,
NORMAL_DTIM = 0x02,
STICK_DTIM = 0x03,
AUTO_DTIM = 0x04,
} BEACON_DTIM_POLICY;
/* During test it is observed that 6 * 400 = 2400 can
* be alloced in addition to CFG_TGT_NUM_MSDU_DESC.
* If there is any change memory requirement, this number
* needs to be revisited. */
#define TOTAL_VOW_ALLOCABLE 2400
#define VOW_DESC_GRAB_MAX 800
#define VOW_GET_NUM_VI_STA(vow_config) (((vow_config) & 0xffff0000) >> 16)
#define VOW_GET_DESC_PER_VI_STA(vow_config) ((vow_config) & 0x0000ffff)
/***TODO!!! Get these values dynamically in WMI_READY event and use it to calculate the mem req*/
/* size in bytes required for msdu descriptor. If it changes, this should be updated. LARGE_AP
* case is not considered. LARGE_AP is disabled when VoW is enabled.*/
#define MSDU_DESC_SIZE 20
/* size in bytes required to support a peer in target.
* This obtained by considering Two tids per peer.
* peer structure = 168 bytes
* tid = 96 bytes (per sta 2 means we need 192 bytes)
* peer_cb = 16 * 2
* key = 52 * 2
* AST = 12 * 2
* rate, reorder.. = 384
* smart antenna = 50
*/
#define MEMORY_REQ_FOR_PEER 800
/*
* NB: it is important to keep all the fields in the structure dword long
* so that it is easy to handle the statistics in BE host.
*/
struct wlan_dbg_tx_stats {
/* Num HTT cookies queued to dispatch list */
A_INT32 comp_queued;
/* Num HTT cookies dispatched */
A_INT32 comp_delivered;
/* Num MSDU queued to WAL */
A_INT32 msdu_enqued;
/* Num MPDU queue to WAL */
A_INT32 mpdu_enqued;
/* Num MSDUs dropped by WMM limit */
A_INT32 wmm_drop;
/* Num Local frames queued */
A_INT32 local_enqued;
/* Num Local frames done */
A_INT32 local_freed;
/* Num queued to HW */
A_INT32 hw_queued;
/* Num PPDU reaped from HW */
A_INT32 hw_reaped;
/* Num underruns */
A_INT32 underrun;
#if defined(AR900B)
/* HW Paused. */
A_UINT32 hw_paused;
#endif
/* Num PPDUs cleaned up in TX abort */
A_INT32 tx_abort;
/* Num MPDUs requed by SW */
A_INT32 mpdus_requed;
/* excessive retries */
A_UINT32 tx_ko;
#if defined(AR900B)
A_UINT32 tx_xretry;
#endif
/* data hw rate code */
A_UINT32 data_rc;
/* Scheduler self triggers */
A_UINT32 self_triggers;
/* frames dropped due to excessive sw retries */
A_UINT32 sw_retry_failure;
/* illegal rate phy errors */
A_UINT32 illgl_rate_phy_err;
/* wal pdev continous xretry */
A_UINT32 pdev_cont_xretry;
/* wal pdev continous xretry */
A_UINT32 pdev_tx_timeout;
/* wal pdev resets */
A_UINT32 pdev_resets;
/* frames dropped due to non-availability of stateless TIDs */
A_UINT32 stateless_tid_alloc_failure;
/* PhY/BB underrun */
A_UINT32 phy_underrun;
/* MPDU is more than txop limit */
A_UINT32 txop_ovf;
#if defined(AR900B)
/* Number of Sequences posted */
A_UINT32 seq_posted;
/* Number of Sequences failed queueing */
A_UINT32 seq_failed_queueing;
/* Number of Sequences completed */
A_UINT32 seq_completed;
/* Number of Sequences restarted */
A_UINT32 seq_restarted;
/* Number of MU Sequences posted */
A_UINT32 mu_seq_posted;
/* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */
A_INT32 mpdus_sw_flush;
/* Num MPDUs filtered by HW, all filter condition (TTL expired) */
A_INT32 mpdus_hw_filter;
/* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */
A_INT32 mpdus_truncated;
/* Num MPDUs that was tried but didn't receive ACK or BA */
A_INT32 mpdus_ack_failed;
/* Num MPDUs that was dropped du to expiry. */
A_INT32 mpdus_expired;
/* Num mc drops */
/* A_UINT32 mc_drop; */
#endif
};
struct wlan_dbg_rx_stats {
/* Cnts any change in ring routing mid-ppdu */
A_INT32 mid_ppdu_route_change;
/* Total number of statuses processed */
A_INT32 status_rcvd;
/* Extra frags on rings 0-3 */
A_INT32 r0_frags;
A_INT32 r1_frags;
A_INT32 r2_frags;
A_INT32 r3_frags;
/* MSDUs / MPDUs delivered to HTT */
A_INT32 htt_msdus;
A_INT32 htt_mpdus;
/* MSDUs / MPDUs delivered to local stack */
A_INT32 loc_msdus;
A_INT32 loc_mpdus;
/* AMSDUs that have more MSDUs than the status ring size */
A_INT32 oversize_amsdu;
/* Number of PHY errors */
A_INT32 phy_errs;
/* Number of PHY errors drops */
A_INT32 phy_err_drop;
/* Number of mpdu errors - FCS, MIC, ENC etc. */
A_INT32 mpdu_errs;
#if defined(AR900B)
/* Number of rx overflow errors. */
A_INT32 rx_ovfl_errs;
#endif
};
struct wlan_dbg_mem_stats {
A_UINT32 iram_free_size;
A_UINT32 dram_free_size;
};
struct wlan_dbg_peer_stats {
A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
};
typedef struct {
A_UINT32 mcs[10];
A_UINT32 sgi[10];
A_UINT32 nss[4];
A_UINT32 nsts;
A_UINT32 stbc[10];
A_UINT32 bw[3];
A_UINT32 pream[6];
A_UINT32 ldpc;
A_UINT32 txbf;
A_UINT32 mgmt_rssi;
A_UINT32 data_rssi;
A_UINT32 rssi_chain0;
A_UINT32 rssi_chain1;
A_UINT32 rssi_chain2;
#if defined(AR900B)
A_UINT32 rssi_chain3;
#endif
} wlan_dbg_rx_rate_info_t;
typedef struct {
A_UINT32 mcs[10];
A_UINT32 sgi[10];
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
A_UINT32 nss[4];
#else
A_UINT32 nss[3];
#endif
A_UINT32 stbc[10];
A_UINT32 bw[3];
A_UINT32 pream[4];
A_UINT32 ldpc;
A_UINT32 rts_cnt;
A_UINT32 ack_rssi;
} wlan_dbg_tx_rate_info_t ;
#define WLAN_MAX_MCS 10
typedef struct {
A_UINT32 mcs[WLAN_MAX_MCS];
A_UINT32 sgi[WLAN_MAX_MCS];
A_UINT32 nss[MAX_SPATIAL_STREAM_ANY];
A_UINT32 nsts;
A_UINT32 stbc[WLAN_MAX_MCS];
A_UINT32 bw[NUM_DYN_BW_MAX];
A_UINT32 pream[6];
A_UINT32 ldpc;
A_UINT32 txbf;
A_UINT32 mgmt_rssi;
A_UINT32 data_rssi;
A_UINT32 rssi_chain0;
A_UINT32 rssi_chain1;
A_UINT32 rssi_chain2;
A_UINT32 rssi_chain3;
A_UINT32 reserved[8];
} wlan_dbg_rx_rate_info_v2_t ;
typedef struct {
A_UINT32 mcs[WLAN_MAX_MCS];
A_UINT32 sgi[WLAN_MAX_MCS];
A_UINT32 nss[MAX_SPATIAL_STREAM_ANY];
A_UINT32 stbc[WLAN_MAX_MCS];
A_UINT32 bw[NUM_DYN_BW_MAX];
A_UINT32 pream[4];
A_UINT32 ldpc;
A_UINT32 rts_cnt;
A_UINT32 ack_rssi;
A_UINT32 reserved[8];
} wlan_dbg_tx_rate_info_v2_t ;
#define WHAL_DBG_PHY_ERR_MAXCNT 18
#define WHAL_DBG_SIFS_STATUS_MAXCNT 8
#define WHAL_DBG_SIFS_ERR_MAXCNT 8
#define WHAL_DBG_CMD_RESULT_MAXCNT 11
#define WHAL_DBG_CMD_STALL_ERR_MAXCNT 4
#define WHAL_DBG_FLUSH_REASON_MAXCNT 40
typedef enum {
WIFI_URRN_STATS_FIRST_PKT,
WIFI_URRN_STATS_BETWEEN_MPDU,
WIFI_URRN_STATS_WITHIN_MPDU,
WHAL_MAX_URRN_STATS
} wifi_urrn_type_t;
typedef struct wlan_dbg_txbf_snd_stats {
A_UINT32 cbf_20[4];
A_UINT32 cbf_40[4];
A_UINT32 cbf_80[4];
A_UINT32 sounding[9];
A_UINT32 cbf_160[4];
} wlan_dbg_txbf_snd_stats_t;
typedef struct wlan_dbg_wifi2_error_stats {
A_UINT32 urrn_stats[WHAL_MAX_URRN_STATS];
A_UINT32 flush_errs[WHAL_DBG_FLUSH_REASON_MAXCNT];
A_UINT32 schd_stall_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT];
A_UINT32 schd_cmd_result[WHAL_DBG_CMD_RESULT_MAXCNT];
A_UINT32 sifs_status[WHAL_DBG_SIFS_STATUS_MAXCNT];
A_UINT8 phy_errs[WHAL_DBG_PHY_ERR_MAXCNT];
A_UINT32 rx_rate_inval;
} wlan_dbg_wifi2_error_stats_t;
typedef struct wlan_dbg_wifi2_error2_stats {
A_UINT32 schd_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT];
A_UINT32 sifs_errs[WHAL_DBG_SIFS_ERR_MAXCNT];
} wlan_dbg_wifi2_error2_stats_t;
#define WLAN_DBG_STATS_SIZE_TXBF_VHT 10
#define WLAN_DBG_STATS_SIZE_TXBF_HT 8
#define WLAN_DBG_STATS_SIZE_TXBF_OFDM 8
#define WLAN_DBG_STATS_SIZE_TXBF_CCK 7
typedef struct wlan_dbg_txbf_data_stats {
A_UINT32 tx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT];
A_UINT32 rx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT];
A_UINT32 tx_txbf_ht[WLAN_DBG_STATS_SIZE_TXBF_HT];
A_UINT32 tx_txbf_ofdm[WLAN_DBG_STATS_SIZE_TXBF_OFDM];
A_UINT32 tx_txbf_cck[WLAN_DBG_STATS_SIZE_TXBF_CCK];
} wlan_dbg_txbf_data_stats_t;
struct wlan_dbg_tx_mu_stats {
A_UINT32 mu_sch_nusers_2;
A_UINT32 mu_sch_nusers_3;
A_UINT32 mu_mpdus_queued_usr[4];
A_UINT32 mu_mpdus_tried_usr[4];
A_UINT32 mu_mpdus_failed_usr[4];
A_UINT32 mu_mpdus_requeued_usr[4];
A_UINT32 mu_err_no_ba_usr[4];
A_UINT32 mu_mpdu_underrun_usr[4];
A_UINT32 mu_ampdu_underrun_usr[4];
};
struct wlan_dbg_tx_selfgen_stats {
A_UINT32 su_ndpa;
A_UINT32 su_ndp;
A_UINT32 mu_ndpa;
A_UINT32 mu_ndp;
A_UINT32 mu_brpoll_1;
A_UINT32 mu_brpoll_2;
A_UINT32 mu_bar_1;
A_UINT32 mu_bar_2;
A_UINT32 cts_burst;
A_UINT32 su_ndp_err;
A_UINT32 su_ndpa_err;
A_UINT32 mu_ndp_err;
A_UINT32 mu_brp1_err;
A_UINT32 mu_brp2_err;
};
typedef struct wlan_dbg_sifs_resp_stats {
A_UINT32 ps_poll_trigger; /* num ps-poll trigger frames */
A_UINT32 uapsd_trigger; /* num uapsd trigger frames */
A_UINT32 qb_data_trigger[2]; /* num data trigger frames; idx 0: explicit and idx 1: implicit */
A_UINT32 qb_bar_trigger[2]; /* num bar trigger frames; idx 0: explicit and idx 1: implicit */
A_UINT32 sifs_resp_data; /* num ppdus transmitted at SIFS interval */
A_UINT32 sifs_resp_err; /* num ppdus failed to meet SIFS resp timing */
} wlan_dgb_sifs_resp_stats_t;
/** wlan_dbg_wifi2_error_stats_t is not grouped with the
* following structure as it is allocated differently and only
* belongs to whal
*/
typedef struct wlan_dbg_stats_wifi2 {
wlan_dbg_txbf_snd_stats_t txbf_snd_info;
wlan_dbg_txbf_data_stats_t txbf_data_info;
struct wlan_dbg_tx_selfgen_stats tx_selfgen;
struct wlan_dbg_tx_mu_stats tx_mu;
wlan_dgb_sifs_resp_stats_t sifs_resp_info;
} wlan_dbg_wifi2_stats_t;
typedef struct {
wlan_dbg_rx_rate_info_t rx_phy_info;
wlan_dbg_tx_rate_info_t tx_rate_info;
} wlan_dbg_rate_info_t;
typedef struct {
wlan_dbg_rx_rate_info_v2_t rx_phy_info;
wlan_dbg_tx_rate_info_v2_t tx_rate_info;
} wlan_dbg_rate_info_v2_t;
struct wlan_dbg_stats {
struct wlan_dbg_tx_stats tx;
struct wlan_dbg_rx_stats rx;
#if defined(AR900B)
struct wlan_dbg_mem_stats mem;
#endif
struct wlan_dbg_peer_stats peer;
};
#define DBG_STATS_MAX_HWQ_NUM 10
#define DBG_STATS_MAX_TID_NUM 20
#define DBG_STATS_MAX_CONG_NUM 16
struct wlan_dbg_txq_stats {
A_UINT16 num_pkts_queued[DBG_STATS_MAX_HWQ_NUM];
A_UINT16 tid_hw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */
A_UINT16 tid_sw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */
};
struct wlan_dbg_tidq_stats {
A_UINT32 wlan_dbg_tid_txq_status;
struct wlan_dbg_txq_stats txq_st;
};
typedef enum {
WHAL_REG_EXT_FCC_MIDBAND = 0,
WHAL_REG_EXT_JAPAN_MIDBAND = 1,
WHAL_REG_EXT_FCC_DFS_HT40 = 2,
WHAL_REG_EXT_JAPAN_NONDFS_HT40 = 3,
WHAL_REG_EXT_JAPAN_DFS_HT40 = 4,
WHAL_REG_EXT_FCC_CH_144 = 5,
} WHAL_REG_EXT_BITMAP;
#endif /* __WLANDEFS_H__ */

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/*
* Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WLAN_MODULE_IDS_H_
#define _WLAN_MODULE_IDS_H_
/* Wlan module ids , global across all the modules */
typedef enum {
WLAN_MODULE_ID_MIN = 0,
WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
WLAN_MODULE_WMI, /* 0x1 */
WLAN_MODULE_STA_PWRSAVE, /* 0x2 */
WLAN_MODULE_WHAL, /* 0x3 */
WLAN_MODULE_COEX, /* 0x4 */
WLAN_MODULE_ROAM, /* 0x5 */
WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */
WLAN_MODULE_RESMGR, /* 0x7 */
WLAN_MODULE_VDEV_MGR, /* 0x8 */
WLAN_MODULE_SCAN, /* 0x9 */
WLAN_MODULE_RATECTRL, /* 0xa */
WLAN_MODULE_AP_PWRSAVE, /* 0xb */
WLAN_MODULE_BLOCKACK, /* 0xc */
WLAN_MODULE_MGMT_TXRX, /* 0xd */
WLAN_MODULE_DATA_TXRX, /* 0xe */
WLAN_MODULE_HTT, /* 0xf */
WLAN_MODULE_HOST, /* 0x10 */
WLAN_MODULE_BEACON, /* 0x11 */
WLAN_MODULE_OFFLOAD, /* 0x12 */
WLAN_MODULE_WAL, /* 0x13 */
WAL_MODULE_DE, /* 0x14 */
WLAN_MODULE_PCIELP, /* 0x15 */
WLAN_MODULE_RTT, /* 0x16 */
WLAN_MODULE_RESOURCE, /* 0x17 */
WLAN_MODULE_DCS, /* 0x18 */
WLAN_MODULE_CACHEMGR, /* 0x19 */
WLAN_MODULE_ANI, /* 0x1a */
WLAN_MODULE_P2P, /* 0x1b */
WLAN_MODULE_CSA, /* 0x1c */
WLAN_MODULE_NLO, /* 0x1d */
WLAN_MODULE_CHATTER, /* 0x1e */
WLAN_MODULE_WOW, /* 0x1f */
WLAN_MODULE_WAL_VDEV, /* 0x20 */
WLAN_MODULE_WAL_PDEV, /* 0x21 */
WLAN_MODULE_TEST, /* 0x22 */
WLAN_MODULE_STA_SMPS, /* 0x23 */
WLAN_MODULE_SWBMISS, /* 0x24 */
WLAN_MODULE_WMMAC, /* 0x25 */
WLAN_MODULE_TDLS, /* 0x26 */
WLAN_MODULE_HB, /* 0x27 */
WLAN_MODULE_TXBF, /* 0x28 */
WLAN_MODULE_BATCH_SCAN, /* 0x29 */
WLAN_MODULE_THERMAL_MGR, /* 0x2a */
WLAN_MODULE_PHYERR_DFS, /* 0x2b */
WLAN_MODULE_RMC, /* 0x2c */
WLAN_MODULE_STATS, /* 0x2d */
WLAN_MODULE_NAN, /* 0x2e */
WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */
WLAN_MODULE_HIF_UART, /* 0x30 */
WLAN_MODULE_LPI, /* 0x31 */
WLAN_MODULE_EXTSCAN, /* 0x32 */
WLAN_MODULE_UNIT_TEST, /* 0x33 */
WLAN_MODULE_MLME, /* 0x34 */
WLAN_MODULE_SUPPL, /* 0x35 */
WLAN_MODULE_ERE, /* 0x36 */
WLAN_MODULE_OCB, /* 0x37 */
WLAN_MODULE_RSSI_MONITOR, /* 0x38 */
WLAN_MODULE_WPM, /* 0x39 */
WLAN_MODULE_CSS, /* 0x3a */
WLAN_MODULE_PPS, /* 0x3b */
WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */
WLAN_MODULE_MAWC, /* 0x3d */
WLAN_MODULE_CMC_QMIC, /* 0x3e */
WLAN_MODULE_EGAP, /* 0x3f */
WLAN_MODULE_NAN20, /* 0x40 */
WLAN_MODULE_QBOOST, /* 0x41 */
WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */
WLAN_MODULE_HALPHY, /* 0x43 */
WAL_MODULE_ENQ, /* 0x44 */
WLAN_MODULE_ID_MAX,
WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
} WLAN_MODULE_ID;
#endif /* _WLAN_MODULE_IDS_H_ */

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/*
* Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __WLAN_TGT_DEF_CONFIG_H__
#define __WLAN_TGT_DEF_CONFIG_H__
/*
* set of default target config , that can be over written by platform
*/
/*
* default limit of 8 VAPs per device.
*/
/* Rome PRD support 4 vdevs */
#define CFG_TGT_NUM_VDEV 4
/*
* We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize hash collisions.
* TODO: This scaling factor would be taken care inside the WAL in the future.
*/
#define CFG_TGT_NUM_PEER_AST 2
/* # of WDS entries to support.
*/
#define CFG_TGT_WDS_ENTRIES 0
/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B
*/
#define CFG_TGT_DEFAULT_DMA_BURST_SIZE 0
/* Fixed delimiters to be inserted after every MPDU
*/
#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM 0
/*
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_AST_SKID_LIMIT 16
/*
* total number of peers per device.
*/
#define CFG_TGT_NUM_PEERS 14
/*
* In offload mode target supports features like WOW, chatter and other
* protocol offloads. In order to support them some functionalities like
* reorder buffering, PN checking need to be done in target. This determines
* maximum number of peers suported by target in offload mode
*/
/*
* The current firmware implementation requires the number of offload peers
* should be (number of vdevs + 1).
* The reason for this is the firmware clubbed the self peer and offload peer
* in the same pool. So if the firmware wanted to support n vdevs then the
* number of offload peer must be n+1 of which n buffers will be used for
* self peer and the remaining 1 is used for offload peer to support chatter
* mode for single STA.
* Technically the macro should be 1 however the current firmware requires n+1.
* TODO: This MACRO need to be modified in the future, if the firmware modified
* to allocate buffers for self peer and offload peer independently.
*/
#define CFG_TGT_NUM_OFFLOAD_PEERS (CFG_TGT_NUM_VDEV+1)
/*
* Number of reorder buffers used in offload mode
*/
#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS 4
/*
* keys per peer node
*/
#define CFG_TGT_NUM_PEER_KEYS 2
/*
* total number of data TX and RX TIDs
*/
#define CFG_TGT_NUM_TIDS (2 * (CFG_TGT_NUM_PEERS + CFG_TGT_NUM_VDEV + 2))
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
*/
#define CFG_TGT_DEFAULT_TX_CHAIN_MASK 0x7
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
*/
#define CFG_TGT_DEFAULT_RX_CHAIN_MASK 0x7
/* 100 ms for video, best-effort, and background */
#define CFG_TGT_RX_TIMEOUT_LO_PRI 100
/* 40 ms for voice*/
#define CFG_TGT_RX_TIMEOUT_HI_PRI 40
/* AR9888 unified is default in ethernet mode */
#define CFG_TGT_RX_DECAP_MODE (0x2)
/* Decap to native Wifi header */
#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1)
/* Decap to raw mode header */
#define CFG_TGT_RX_DECAP_MODE_RAW (0x0)
/* maximum number of pending scan requests */
#define CFG_TGT_DEFAULT_SCAN_MAX_REQS 0x4
/* maximum number of VDEV that could use BMISS offload */
#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV 0x3
/* maximum number of VDEV offload Roaming to support */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV 0x3
/* maximum number of AP profiles pushed to offload Roaming */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES 0x8
/* maximum number of VDEV offload GTK to support */
#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV 0x3
/* default: mcast->ucast disabled if ATH_SUPPORT_MCAST2UCAST not defined */
#ifndef ATH_SUPPORT_MCAST2UCAST
#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0
#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0
#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0 /* disabled */
#else
/* (for testing) small multicast group membership table enabled */
#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 4
#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 16
#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 2
#endif
#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 32
/*
* Specify how much memory the target should allocate for a debug log of
* tx PPDU meta-information (how large the PPDU was, when it was sent,
* whether it was successful, etc.)
* The size of the log records is configurable, from a minimum of 28 bytes
* to a maximum of about 300 bytes. A typical configuration would result
* in each log record being about 124 bytes.
* Thus, 1KB of log space can hold about 30 small records, 3 large records,
* or about 8 typical-sized records.
*/
#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024 /* bytes */
/* target based fragment timeout and MPDU duplicate detection */
#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
/* Default VoW configuration
*/
#define CFG_TGT_DEFAULT_VOW_CONFIG 0
/*
* total number of descriptors to use in the target
*/
#define CFG_TGT_NUM_MSDU_DESC (1024 + 32)
/*
* Maximum number of frag table entries
*/
#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 10
/*
* Maximum number of VDEV that beacon tx offload will support
*/
#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 3
/*
* number of vdevs that can support tdls
*/
#define CFG_TGT_NUM_TDLS_VDEVS 1
/*
* number of peers that each Tdls vdev can track
*/
#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES 32
/*
* number of TDLS concurrent sleep STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS 1
/*
* number of TDLS concurrent buffer STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS 1
/*
* ht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_HT_MASK 0x8080
/*
* vht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_VHT_MASK 0x80200
/*
* threshold to enable GTX
*/
#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD 3
/*
* margin to move back when per > margin + threshold
*/
#define CFG_TGT_DEFAULT_GTX_PER_MARGIN 2
/*
* step for every move
*/
#define CFG_TGT_DEFAULT_GTX_TPC_STEP 1
/*
* lowest TPC
*/
#define CFG_TGT_DEFAULT_GTX_TPC_MIN 0
/*
* enable all BW 20/40/80/160
*/
#define CFG_TGT_DEFAULT_GTX_BW_MASK 0xf
/*
* number of vdevs that can support OCB
*/
#define CFG_TGT_NUM_OCB_VDEVS 1
/*
* maximum number of channels that can do OCB
*/
#define CFG_TGT_NUM_OCB_CHANNELS 2
/*
* maximum number of channels in an OCB schedule
*/
#define CFG_TGT_NUM_OCB_SCHEDULES 2
#endif /*__WLAN_TGT_DEF_CONFIG_H__ */

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __WLAN_TGT_DEF_CONFIG_H__
#define __WLAN_TGT_DEF_CONFIG_H__
/*
* TODO: please help to consider if we need a seperate config file from LL case.
*/
/*
* set of default target config , that can be over written by platform
*/
#ifdef QCA_SUPPORT_INTEGRATED_SOC
#define CFG_TGT_NUM_VDEV 3 /*STA, P2P device, P2P GO/Cli*/
#else
/*
* default limit of VAPs per device.
*/
#define CFG_TGT_NUM_VDEV 3
#endif
/*
* We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize
* hash collisions.
* TODO: This scaling factor would be taken care inside the WAL in the future.
*/
#define CFG_TGT_NUM_PEER_AST 2
/* # of WDS entries to support.
*/
#define CFG_TGT_WDS_ENTRIES 2
/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B
*/
#define CFG_TGT_DEFAULT_DMA_BURST_SIZE 0
/* Fixed delimiters to be inserted after every MPDU
*/
#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM 0
/*
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_AST_SKID_LIMIT 6
/*
* total number of peers per device.
* currently set to 8 to bring up IP3.9 for memory size problem
*/
#define CFG_TGT_NUM_PEERS 8
/*
* max number of peers per device.
*/
#define CFG_TGT_NUM_PEERS_MAX 8
/*
* In offload mode target supports features like WOW, chatter and other
* protocol offloads. In order to support them some functionalities like
* reorder buffering, PN checking need to be done in target. This determines
* maximum number of peers suported by target in offload mode
*/
#define CFG_TGT_NUM_OFFLOAD_PEERS 0
/*
* Number of reorder buffers used in offload mode
*/
#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS 0
/*
* keys per peer node
*/
#define CFG_TGT_NUM_PEER_KEYS 2
/*
* total number of TX/RX data TIDs
*/
#define CFG_TGT_NUM_TIDS (2 * (CFG_TGT_NUM_PEERS + \
CFG_TGT_NUM_VDEV))
/*
* max number of Tx TIDS
*/
#define CFG_TGT_NUM_TIDS_MAX (2 * (CFG_TGT_NUM_PEERS_MAX + \
CFG_TGT_NUM_VDEV))
/*
* number of multicast keys.
*/
#define CFG_TGT_NUM_MCAST_KEYS 8
/*
* A value of 3 would probably suffice - one for the control stack, one for
* the data stack, and one for debugging.
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_PDEV_HANDLERS 8
/*
* A value of 3 would probably suffice - one for the control stack, one for
* the data stack, and one for debugging.
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_VDEV_HANDLERS 4
/*
* set this to 8:
* one for WAL interals (connection pause)
* one for the control stack,
* one for the data stack
* and one for debugging
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_HANDLERS 14
/*
* set this to 3: one for the control stack, one for
* the data stack, and one for debugging.
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_PEER_HANDLERS 32
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
* this is rome
*/
#define CFG_TGT_DEFAULT_TX_CHAIN_MASK 0x3
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
* this is rome
*/
#define CFG_TGT_DEFAULT_RX_CHAIN_MASK 0x3
/* 100 ms for video, best-effort, and background */
#define CFG_TGT_RX_TIMEOUT_LO_PRI 100
/* 40 ms for voice*/
#define CFG_TGT_RX_TIMEOUT_HI_PRI 40
/* AR9888 unified is default in ethernet mode */
#define CFG_TGT_RX_DECAP_MODE (0x2)
/* Decap to native Wifi header */
#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1)
/* Decap to raw mode header */
#define CFG_TGT_RX_DECAP_MODE_RAW (0x0)
/* maximum number of pending scan requests */
#define CFG_TGT_DEFAULT_SCAN_MAX_REQS 0x4
/* maximum number of scan event handlers */
#define CFG_TGT_DEFAULT_SCAN_MAX_HANDLERS 0x4
/* maximum number of VDEV that could use BMISS offload */
#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV 0x2
/* maximum number of VDEV offload Roaming to support */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV 0x2
/* maximum number of AP profiles pushed to offload Roaming */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES 0x8
/* maximum number of VDEV offload GTK to support */
#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV 0x2
/* default: mcast->ucast disabled */
#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0
#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0
#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0 /* disabled */
/*
* Specify how much memory the target should allocate for a debug log of
* tx PPDU meta-information (how large the PPDU was, when it was sent,
* whether it was successful, etc.)
* The size of the log records is configurable, from a minimum of 28 bytes
* to a maximum of about 300 bytes. A typical configuration would result
* in each log record being about 124 bytes.
* Thus, 1KB of log space can hold about 30 small records, 3 large records,
* or about 8 typical-sized records.
*/
#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024 /* bytes */
/* target based fragment timeout and MPDU duplicate detection */
#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
/* Default VoW configuration
*/
#define CFG_TGT_DEFAULT_VOW_CONFIG 0
/*
* total number of descriptors to use in the target
*/
#ifndef HIF_SDIO
#define CFG_TGT_NUM_MSDU_DESC (32)
#else
#define CFG_TGT_NUM_MSDU_DESC (0)
#endif
/*
* Maximum number of frag table entries
*/
#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 2
/*
* number of vdevs that can support tdls
*/
#define CFG_TGT_NUM_TDLS_VDEVS 1
/*
* number of peers that each Tdls vdev can track
*/
#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES 32
/*
* number of TDLS concurrent sleep STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS 1
/*
* number of TDLS concurrent buffer STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS 1
#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 16
/*
* Maximum number of VDEV that beacon tx offload will support
*/
#ifdef HIF_SDIO
#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 2
#else
#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 1
#endif
/*
* ht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_HT_MASK 0x8080
/*
* vht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_VHT_MASK 0x80200
/*
* threshold to enable GTX
*/
#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD 3
/*
* margin to move back when per > margin + threshold
*/
#define CFG_TGT_DEFAULT_GTX_PER_MARGIN 2
/*
* step for every move
*/
#define CFG_TGT_DEFAULT_GTX_TPC_STEP 1
/*
* lowest TPC
*/
#define CFG_TGT_DEFAULT_GTX_TPC_MIN 0
/*
* enable all BW 20/40/80/160
*/
#define CFG_TGT_DEFAULT_GTX_BW_MASK 0xf
/*
* number of vdevs that can support OCB
*/
#define CFG_TGT_NUM_OCB_VDEVS 1
/*
* maximum number of channels that can do OCB
*/
#define CFG_TGT_NUM_OCB_CHANNELS 2
/*
* maximum number of channels in an OCB schedule
*/
#define CFG_TGT_NUM_OCB_SCHEDULES 2
#endif /*__WLAN_TGT_DEF_CONFIG_H__ */

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/*
* Copyright (c) 2004-2010, 2013-2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* This file contains the definitions of the WMI protocol specified in the
* Wireless Module Interface (WMI). It includes definitions of all the
* commands and events. Commands are messages from the host to the WM.
* Events and Replies are messages from the WM to the host.
*
* Ownership of correctness in regards to commands
* belongs to the host driver and the WMI is not required to validate
* parameters for value, proper range, or any other checking.
*
*/
#ifndef _WMI_H_
#define _WMI_H_
#include "wlan_defs.h"
#include "wmix.h"
#include "wmi_unified.h"
#include "wmi_tlv_helper.h"
#include "wmi_tlv_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HTC_PROTOCOL_VERSION 0x0002
#define WMI_PROTOCOL_VERSION 0x0002
#define WMI_MODE_MAX 8
#define WMI_MAX_RATE_MASK 6
PREPACK struct host_app_area_s {
A_UINT32 wmi_protocol_ver;
} POSTPACK;
#undef MS
#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
#undef WO
#define WO(_f) ((_f ## _OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
#define WMI_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
#define WMI_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
/* TYPO: leave incorrect name as an alias for the correct name */
#define WMI_EP_APASS WMI_EP_APSS
/* WLAN driver running on apps processor sub-system */
#define WMI_EP_APSS 0x0
#define WMI_EP_LPASS 0x1
#define WMI_EP_SENSOR 0x2
/* WLAN driver running on NANO Hub */
#define WMI_EP_NANOHUB 0x3
#define WMI_EP_MODEM 0x4
#define WMI_EP_LOCATION 0x5
/*
* Control Path
*/
typedef PREPACK struct {
A_UINT32 commandId : 24, reserved : 2, /* used for WMI endpoint ID */
plt_priv : 6; /* platform private */
} POSTPACK WMI_CMD_HDR; /* used for commands and events */
#define WMI_CMD_HDR_COMMANDID_LSB 0
#define WMI_CMD_HDR_COMMANDID_MASK 0x00ffffff
#define WMI_CMD_HDR_COMMANDID_OFFSET 0x00000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK 0x03000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET 24
#define WMI_CMD_HDR_PLT_PRIV_LSB 24
#define WMI_CMD_HDR_PLT_PRIV_MASK 0xff000000
#define WMI_CMD_HDR_PLT_PRIV_OFFSET 0x00000000
/*
* List of Commnands
*/
typedef enum {
WMI_EXTENSION_CMDID, /* used in wmi_svc.c / * Non-wireless extensions * / */
WMI_IGNORE_CMDID, /* used in wlan_wmi.c */
} WMI_COMMAND_ID;
typedef enum {
NONE_CRYPT = 0x01,
WEP_CRYPT = 0x02,
TKIP_CRYPT = 0x04,
AES_CRYPT = 0x08,
#ifdef WAPI_ENABLE
WAPI_CRYPT = 0x10,
#endif /*WAPI_ENABLE */
} CRYPTO_TYPE;
#define WMI_MAX_SSID_LEN 32
/*
* WMI_SET_PMK_CMDID
*/
#define WMI_PMK_LEN 32
/*
* WMI_ADD_CIPHER_KEY_CMDID
*/
typedef enum {
PAIRWISE_USAGE = 0x00,
GROUP_USAGE = 0x01,
TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
} KEY_USAGE;
/*
* List of Events (target to host)
*/
typedef enum {
WMI_EXTENSION_EVENTID, /* wmi_profhook.c and umac_wmi_events.c */
} WMI_EVENT_ID;
typedef enum {
WMI_11A_CAPABILITY = 1,
WMI_11G_CAPABILITY = 2,
WMI_11AG_CAPABILITY = 3,
WMI_11NA_CAPABILITY = 4,
WMI_11NG_CAPABILITY = 5,
WMI_11NAG_CAPABILITY = 6,
WMI_11AC_CAPABILITY = 7,
WMI_11AX_CAPABILITY = 8,
/* END CAPABILITY */
WMI_11N_CAPABILITY_OFFSET =
(WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
} WMI_PHY_CAPABILITY;
/* Deprectated, need clean up */
#define WMI_MAX_RX_META_SZ (12)
typedef PREPACK struct {
A_INT8 rssi;
A_UINT8 info; /* usage of 'info' field(8-bit):
* b1:b0 - WMI_MSG_TYPE
* b4:b3:b2 - UP(tid)
* b5 - Used in AP mode. More-data in tx dir, PS in rx.
* b7:b6 - Dot3 header(0),
* Dot11 Header(1),
* ACL data(2)
*/
A_UINT16 info2; /* usage of 'info2' field(16-bit):
* b11:b0 - seq_no
* b12 - A-MSDU?
* b15:b13 - META_DATA_VERSION 0 - 7
*/
A_UINT16 info3; /* b3:b2:b1:b0 - device id
* b4 - Used in AP mode. uAPSD trigger in rx, EOSP in tx
* b7:b5 - unused?
* b15:b8 - pad before data start(irrespective of meta version)
*/
} POSTPACK WMI_DATA_HDR;
#ifdef __cplusplus
}
#endif
#endif /* _WMI_H_ */

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/*
* Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/**
* This file defines WMI services bitmap and the set of WMI services .
* defines macrso to set/clear/get different service bits from the bitmap.
* the service bitmap is sent up to the host via WMI_READY command.
*
*/
#ifndef _WMI_SERVICES_H_
#define _WMI_SERVICES_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WMI_SERVICE_BEACON_OFFLOAD = 0, /* beacon offload */
WMI_SERVICE_SCAN_OFFLOAD = 1, /* scan offload */
WMI_SERVICE_ROAM_SCAN_OFFLOAD = 2, /* roam scan offload */
WMI_SERVICE_BCN_MISS_OFFLOAD = 3, /* beacon miss offload */
/* fake sleep + basic power save */
WMI_SERVICE_STA_PWRSAVE = 4,
WMI_SERVICE_STA_ADVANCED_PWRSAVE = 5, /* uapsd, pspoll, force sleep */
WMI_SERVICE_AP_UAPSD = 6, /* uapsd on AP */
WMI_SERVICE_AP_DFS = 7, /* DFS on AP */
WMI_SERVICE_11AC = 8, /* supports 11ac */
/* Supports triggering ADDBA/DELBA from host*/
WMI_SERVICE_BLOCKACK = 9,
WMI_SERVICE_PHYERR = 10, /* PHY error */
WMI_SERVICE_BCN_FILTER = 11, /* Beacon filter support */
/* RTT (round trip time) support */
WMI_SERVICE_RTT = 12,
WMI_SERVICE_WOW = 13, /* WOW Support */
WMI_SERVICE_RATECTRL_CACHE = 14, /* Rate-control caching */
WMI_SERVICE_IRAM_TIDS = 15, /* TIDs in IRAM */
/* ARP NS Offload support for STA vdev */
WMI_SERVICE_ARPNS_OFFLOAD = 16,
/* Network list offload service */
WMI_SERVICE_NLO = 17,
WMI_SERVICE_GTK_OFFLOAD = 18, /* GTK offload */
WMI_SERVICE_SCAN_SCH = 19, /* Scan Scheduler Service */
WMI_SERVICE_CSA_OFFLOAD = 20, /* CSA offload service */
WMI_SERVICE_CHATTER = 21, /* Chatter service */
/* FW report freq range to avoid */
WMI_SERVICE_COEX_FREQAVOID = 22,
WMI_SERVICE_PACKET_POWER_SAVE = 23, /* packet power save service */
/* Service to test the firmware recovery mechanism */
WMI_SERVICE_FORCE_FW_HANG = 24,
WMI_SERVICE_GPIO = 25, /* GPIO service */
/* Modulated DTIM support */
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
/**
* Basic version of station UAPSD AC Trigger Generation Method with
* variable tigger periods (service, delay, and suspend intervals)
*/
WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
/**
* Station UAPSD AC Trigger Generation Method with variable
* trigger periods (service, delay, and suspend intervals)
*/
WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
/* Serivce to support the STA KEEP ALIVE mechanism */
WMI_SERVICE_STA_KEEP_ALIVE = 29,
/* Packet type for TX encapsulation */
WMI_SERVICE_TX_ENCAP = 30,
/* detect out-of-sync sleeping stations */
WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
WMI_SERVICE_EARLY_RX = 32, /* adaptive early-rx feature */
WMI_SERVICE_STA_SMPS = 33, /* STA MIMO-PS */
WMI_SERVICE_FWTEST = 34, /* Firmware test service */
WMI_SERVICE_STA_WMMAC = 35, /* STA WMMAC */
WMI_SERVICE_TDLS = 36, /* TDLS support */
WMI_SERVICE_BURST = 37, /* SIFS spaced burst support */
/* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */
WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
/* Service to support adaptive off-channel scheduler */
WMI_SERVICE_ADAPTIVE_OCS = 39,
/* target will provide Sequence number for the peer/tid combo */
WMI_SERVICE_BA_SSN_SUPPORT = 40,
WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
WMI_SERVICE_WLAN_HB = 42, /* wlan HB service */
/* support LTE/WLAN antenna sharing */
WMI_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
WMI_SERVICE_BATCH_SCAN = 44, /*Service to support batch scan*/
WMI_SERVICE_QPOWER = 45, /* QPower service */
WMI_SERVICE_PLMREQ = 46,
WMI_SERVICE_THERMAL_MGMT = 47, /* thermal throttling support */
WMI_SERVICE_RMC = 48, /* RMC support */
/* multi-hop forwarding offload */
WMI_SERVICE_MHF_OFFLOAD = 49,
/* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */
WMI_SERVICE_COEX_SAR = 50,
/* Will support the bcn/prb rsp rate override */
WMI_SERVICE_BCN_TXRATE_OVERRIDE = 51,
WMI_SERVICE_NAN = 52, /* Neighbor Awareness Network */
/* L1SS statistics counter report */
WMI_SERVICE_L1SS_STAT = 53,
/* Linkspeed Estimation per peer */
WMI_SERVICE_ESTIMATE_LINKSPEED = 54,
/* Service to support OBSS scan */
WMI_SERVICE_OBSS_SCAN = 55,
WMI_SERVICE_TDLS_OFFCHAN = 56, /* TDLS off channel support */
/* TDLS UAPSD Buffer STA support */
WMI_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
/* TDLS UAPSD Sleep STA support */
WMI_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
WMI_SERVICE_IBSS_PWRSAVE = 59, /* IBSS power save support */
WMI_SERVICE_LPASS = 60, /*Service to support LPASS*/
WMI_SERVICE_EXTSCAN = 61, /* Extended Scans */
WMI_SERVICE_D0WOW = 62, /* D0-WOW Support */
/* Hotspot offload feature Support */
WMI_SERVICE_HSOFFLOAD = 63,
WMI_SERVICE_ROAM_HO_OFFLOAD = 64, /* roam handover offload */
/* target-based Rx full reorder */
WMI_SERVICE_RX_FULL_REORDER = 65,
WMI_SERVICE_DHCP_OFFLOAD = 66, /* DHCP offload support */
/* STA RX DATA offload to IPA support */
WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
/* mDNS responder offload support */
WMI_SERVICE_MDNS_OFFLOAD = 68,
WMI_SERVICE_SAP_AUTH_OFFLOAD = 69, /* softap auth offload */
/* Dual Band Simultaneous support */
WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
WMI_SERVICE_OCB = 71, /* OCB mode support */
/* arp offload support for ap mode vdev */
WMI_SERVICE_AP_ARPNS_OFFLOAD = 72,
/* Per band chainmask support */
WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
WMI_SERVICE_PACKET_FILTER_OFFLOAD = 74, /* Per vdev packet filters */
WMI_SERVICE_MGMT_TX_HTT = 75, /* Mgmt Tx via HTT interface */
WMI_SERVICE_MGMT_TX_WMI = 76, /* Mgmt Tx via WMI interface */
/* WMI_SERVICE_READY_EXT msg follows */
WMI_SERVICE_EXT_MSG = 77,
/* Motion Aided WiFi Connectivity (MAWC)*/
WMI_SERVICE_MAWC = 78,
/* target will send ASSOC_CONF after ASSOC_CMD is processed */
WMI_SERVICE_PEER_ASSOC_CONF = 79,
WMI_SERVICE_EGAP = 80, /* enhanced green ap support */
/* FW supports 11W PMF Offload for STA */
WMI_SERVICE_STA_PMF_OFFLOAD = 81,
/* FW supports unified D0 and D3 wow */
WMI_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
/* Enhanced ProxySTA mode support */
WMI_SERVICE_ENHANCED_PROXY_STA = 83,
WMI_SERVICE_ATF = 84, /* Air Time Fairness support */
WMI_SERVICE_COEX_GPIO = 85, /* BTCOEX GPIO support */
/**
* Aux Radio enhancement support for ignoring spectral scan intf
* from main radios
*/
WMI_SERVICE_AUX_SPECTRAL_INTF = 86,
/**
* Aux Radio enhancement support for ignoring chan load intf
* from main radios
*/
WMI_SERVICE_AUX_CHAN_LOAD_INTF = 87,
/**
* BSS channel info (freq, noise floor, 64-bit counters)
* event support
*/
WMI_SERVICE_BSS_CHANNEL_INFO_64 = 88,
/* Enterprise MESH Service Support */
WMI_SERVICE_ENTERPRISE_MESH = 89,
WMI_SERVICE_RESTRT_CHNL_SUPPORT = 90, /* Restricted Channel Support */
WMI_SERVICE_BPF_OFFLOAD = 91, /* FW supports bpf offload */
/* FW sends response event for Peer, Vdev delete commands */
WMI_SERVICE_SYNC_DELETE_CMDS = 92,
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
/* allow per-peer tx MCS min/max limits by host */
WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
WMI_SERVICE_NAN_DATA = 96, /* FW supports NAN data */
WMI_SERVICE_NAN_RTT = 97, /* FW supports NAN RTT */
WMI_SERVICE_11AX = 98, /* FW supports 802.11ax */
/* WMI_SERVICE_DEPRECATED_REPLACE
* FW supports these new WMI commands, to be used rather than
* deprecated matching commands:
* - WMI_PDEV_SET_PCL_CMDID (vs. WMI_SOC_SET_PCL_CMDID)
* - WMI_PDEV_SET_HW_MODE_CMDID
* (vs. WMI_SOC_SET_HW_MODE_CMDID)
* - WMI_PDEV_SET_MAC_CONFIG_CMDID
* (vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID)
* - WMI_PDEV_SET_ANTENNA_MODE_CMDID
* (vs. WMI_SOC_SET_ANTENNA_MODE_CMDID)
* - WMI_VDEV_SET_DSCP_TID_MAP_CMDID
* (vs. WMI_VDEV_SET_WMM_PARAMS_CMDID)
*/
WMI_SERVICE_DEPRECATED_REPLACE = 99,
/**
* FW supports a new mode that allows to run connection tracker
* in host
*/
WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
/**
* FW supports enhanced multicast filtering (of mcast IP inside
* ucast WLAN)
*/
WMI_SERVICE_ENHANCED_MCAST_FILTER = 101,
/* periodic channel stats service */
WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
WMI_SERVICE_MESH_11S = 103,
/**
* FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate)
* channel bandwidth
*/
WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
/* Support per-vdev specs of which rx frames to filter out */
WMI_SERVICE_VDEV_RX_FILTER = 105,
WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
/**
* FW supports marking the first data packet which wakes
* the host from suspend
*/
WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
/* FW supports command that can add/delete multiple mcast filters */
WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
/* WMI_SERVICE_HOST_MANAGED_RX_REORDER -
* FW supports host-managed RX reorder.
* Host managed RX reorder involves RX BA state machine handling
* on peer/TID basis, REO configuration for HW based reordering/PN
* check and processing reorder exceptions generated by HW.
*/
WMI_SERVICE_HOST_MANAGED_RX_REORDER = 109,
/* Specify whether the target supports the following WMI messages
* for reading / writing its flash memory:
* WMI_READ_DATA_FROM_FLASH_CMDID,
* WMI_READ_DATA_FROM_FLASH_EVENTID,
* WMI_TRANSFER_DATA_TO_FLASH_CMDID,
* WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
*/
WMI_SERVICE_FLASH_RDWR_SUPPORT = 110,
WMI_SERVICE_WLAN_STATS_REPORT = 111, /* support WLAN stats report */
/* WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT -
* FW supports bigger MSDU ID partition which is defined as
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. When both host and FW support
* new partition, FW uses HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. If host
* doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
* Handshaking is done through WMI_INIT and WMI service ready
*
* support bigger MSDU ID partition
*/
WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
WMI_SERVICE_DFS_PHYERR_OFFLOAD = 113,
/*** ADD NEW SERVICES HERE UNTIL ALL VALUES UP TO 128 ARE USED ***/
WMI_MAX_SERVICE = 128, /* max service */
/**
* NOTE:
* The above service flags are delivered in the wmi_service_bitmap
* field of the WMI_SERVICE_READY_EVENT message.
* The below service flags are delivered in a
* WMI_SERVICE_AVAILABLE_EVENT message rather than in the
* WMI_SERVICE_READY_EVENT message's wmi_service_bitmap field.
* The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the
* WMI_SERVICE_READY_EVENT message.
*/
/*PUT 1ST EXT SERVICE HERE:*//*WMI_SERVICE_xxxxxxxx=128,*/
/*PUT 2ND EXT SERVICE HERE:*//*WMI_SERVICE_yyyyyyyy=129,*/
WMI_MAX_EXT_SERVICE
} WMI_SERVICE;
#define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(A_UINT32)- 1)/sizeof(A_UINT32))
#define WMI_NUM_EXT_SERVICES (WMI_MAX_EXT_SERVICE - WMI_MAX_SERVICE)
#define WMI_SERVICE_EXT_BM_SIZE32 ((WMI_NUM_EXT_SERVICES + 31) / 32)
/**
* depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help
* compiling with old host driver
*/
#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD
/*
* turn on the WMI service bit corresponding to the WMI service.
*/
#define WMI_SERVICE_ENABLE(pwmi_svc_bmap,svc_id) \
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \
(1 << ((svc_id)%(sizeof(A_UINT32)))) )
#define WMI_SERVICE_DISABLE(pwmi_svc_bmap,svc_id) \
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &= \
( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) )
#define WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap,svc_id) \
( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] & \
(1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)
#define WMI_SERVICE_EXT_ENABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] |= (1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT_DISABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT_IS_ENABLED(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
/* If the service ID is beyond the known limit, treat it as disabled */ \
((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \
/* If service ID is in the non-extension range, use the old check */ \
(svc_id) < WMI_MAX_SERVICE ? \
WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \
/* If service ID is in the extended range, check ext_bmap */ \
(pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \
((svc_id) & 0x1f))
#ifdef __cplusplus
}
#endif
#endif /*_WMI_SERVICES_H_*/

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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WMI_TLV_HELPER_H_
#define _WMI_TLV_HELPER_H_
/*
* Every command or event parameter structure will need a TLV definition.
* The macro WMITLV_TABLE is used to help build this TLV definition. Inside this macro define, the
* individual TLV's are specified. The parameters for WMITLV_ELEM are:
* (1) the list of parameters that are passed unchanged from the WMITLV_TABLE. Currently, they are id,op,buf,len
* (2) The TLV Tag. You should create a new tag for each cmd/event in WMITLV_TAG_ID. The name of the
* tag is <WMI_TLVTAG_STRUC_><CMD or Event ID name>. There are special tags,
* e.g. WMI_TLVTAG_ARRAY_UINT32 and WMI_TLVTAG_ARRAY_STRUC. WMI_TLVTAG_ARRAY_UINT32 is for a
* variable size array of UINT32 elements. WMI_TLVTAG_ARRAY_STRUC is for a varialbe size array
* of structures.
* (3) type of the TLV. For WMI_TLVTAG_ARRAY_* tag, then it is the type of each element.
* (4) Name of this TLV. It must be unique in this TLV TABLE.
* (5) Either WMITLV_SIZE_FIX or WMITLV_SIZE_VAR to indicate if this TLV is variable size.
*
* Note: It is important that the last TLV_ELEM does not have the "\" character.
*/
/* Size of the TLV Header which is the Tag and Length fields */
#define WMI_TLV_HDR_SIZE (1 * sizeof(A_UINT32))
/** TLV Helper macro to get the TLV Header given the pointer
* to the TLV buffer. */
#define WMITLV_GET_HDR(tlv_buf) (((A_UINT32 *)(tlv_buf))[0])
/** TLV Helper macro to set the TLV Header given the pointer
* to the TLV buffer. */
#define WMITLV_SET_HDR(tlv_buf, tag, len) (((A_UINT32 *)(tlv_buf))[0]) = ((tag << 16) | (len & 0x0000FFFF))
/** TLV Helper macro to get the TLV Tag given the TLV header. */
#define WMITLV_GET_TLVTAG(tlv_header) ((A_UINT32)((tlv_header)>>16))
/** TLV Helper macro to get the TLV Buffer Length (minus TLV
* header size) given the TLV header. */
#define WMITLV_GET_TLVLEN(tlv_header) ((A_UINT32)((tlv_header) & 0x0000FFFF))
/** TLV Helper macro to get the TLV length from TLV structure size by removing TLV header size */
#define WMITLV_GET_STRUCT_TLVLEN(tlv_struct) ((A_UINT32)(sizeof(tlv_struct)-WMI_TLV_HDR_SIZE))
/* Indicates whether the TLV is fixed size or variable length */
#define WMITLV_SIZE_FIX 0
#define WMITLV_SIZE_VAR 1
typedef struct {
A_UINT32 tag_order;
A_UINT32 tag_id;
A_UINT32 tag_struct_size;
A_UINT32 tag_varied_size;
A_UINT32 tag_array_size;
A_UINT32 cmd_num_tlv;
} wmitlv_attributes_struc;
/* Template structure definition for a variable size array of UINT32 */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */
A_UINT32 uint32_array[1]; /* variable length Array of UINT32 */
} wmitlv_array_uint32;
/* Template structure definition for a variable size array of unknown structure */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */
A_UINT32 struc_array[1]; /* variable length Array of structures */
} wmitlv_array_struc;
/*
* Used to fill in the "arr_size" parameter when it is not specified and hence, invalid. Can be used to
* indicate if the original TLV definition specify this fixed array size.
*/
#define WMITLV_ARR_SIZE_INVALID 0x1FE
#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id) \
WMI_TLV_HLPR_NUM_TLVS_FOR_ ## wmi_cmd_event_id
void
wmitlv_set_static_param_tlv_buf(void *param_tlv_buf,
A_UINT32 max_tlvs_accomodated);
void
wmitlv_free_allocated_command_tlvs(A_UINT32 cmd_id, void **wmi_cmd_struct_ptr);
void
wmitlv_free_allocated_event_tlvs(A_UINT32 event_id, void **wmi_cmd_struct_ptr);
int
wmitlv_check_command_tlv_params(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id);
int
wmitlv_check_event_tlv_params(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id);
int
wmitlv_check_and_pad_command_tlvs(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id,
void **wmi_cmd_struct_ptr);
int
wmitlv_check_and_pad_event_tlvs(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id,
void **wmi_cmd_struct_ptr);
/** This structure is the element for the Version WhiteList
* table. */
typedef struct {
A_UINT32 major;
A_UINT32 minor;
A_UINT32 namespace_0;
A_UINT32 namespace_1;
A_UINT32 namespace_2;
A_UINT32 namespace_3;
} wmi_whitelist_version_info;
struct _wmi_abi_version; /* Forward declaration to make the ARM compiler happy */
int
wmi_cmp_and_set_abi_version(int num_whitelist,
wmi_whitelist_version_info *
version_whitelist_table,
struct _wmi_abi_version *my_vers,
struct _wmi_abi_version *opp_vers,
struct _wmi_abi_version *out_vers);
int
wmi_versions_are_compatible(struct _wmi_abi_version *vers1,
struct _wmi_abi_version *vers2);
#endif /*_WMI_TLV_HELPER_H_*/

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target/inc/wmi_unified.h
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target/inc/wmi_version.h
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/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* IMPORTANT NOTE: For all change to WMI Interface, the ABI version number _must_ be updated.
*/
/** Major version number is incremented when there are significant changes to WMI Interface that break compatibility. */
#define __WMI_VER_MAJOR_ 1
/** Minor version number is incremented when there are changes
* (however minor) to WMI Interface that break
* compatibility. */
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility */
#define __WMI_REVISION_ 316
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
* together.
* For example, "QCA_ML" converts to 0x4C, 0x4D5F414351.
* where 'Q'=0x51, 'C'=0x43, 'A'=0x41, '_'=0x5F. 'M'=4D, 'L'=4C
*/
#define __NAMESPACE_0_ 0x5F414351
#define __NAMESPACE_1_ 0x00004C4D
#define __NAMESPACE_2_ 0x00000000
#define __NAMESPACE_3_ 0x00000000
/* Format of the version number. */
#define WMI_VER_MAJOR_BIT_OFFSET 24
#define WMI_VER_MINOR_BIT_OFFSET 0
#define WMI_VER_MAJOR_BIT_MASK 0xFF000000
#define WMI_VER_MINOR_BIT_MASK 0x00FFFFFF
/* Macros to extract the sw_version components.
*/
#define WMI_VER_GET_MAJOR(x) (((x) & WMI_VER_MAJOR_BIT_MASK)>>WMI_VER_MAJOR_BIT_OFFSET)
#define WMI_VER_GET_MINOR(x) (((x) & WMI_VER_MINOR_BIT_MASK)>>WMI_VER_MINOR_BIT_OFFSET)
#define WMI_VER_GET_VERSION_0(major, minor) ( (( major << WMI_VER_MAJOR_BIT_OFFSET ) & WMI_VER_MAJOR_BIT_MASK) + (( minor << WMI_VER_MINOR_BIT_OFFSET ) & WMI_VER_MINOR_BIT_MASK) )
/*
* The version has the following format:
* Bits 24-31: Major version
* Bits 0-23: Minor version
* Bits 0-31: Build number
* E.g. Build 1.1.7 would be represented as 0x01000001 for Major/Minor & 0x00000007 for buildnum.
*
* DO NOT split the following macro into multiple lines as this may confuse the build scripts.
*/
/* ABI Version. Reflects the version of binary interface exposed by Target firmware. */
#define WMI_ABI_VERSION_0 WMI_VER_GET_VERSION_0(__WMI_VER_MAJOR_, __WMI_VER_MINOR_)
#define WMI_ABI_VERSION_1 __WMI_REVISION_
#define WMI_ABI_VERSION_NS_0 __NAMESPACE_0_
#define WMI_ABI_VERSION_NS_1 __NAMESPACE_1_
#define WMI_ABI_VERSION_NS_2 __NAMESPACE_2_
#define WMI_ABI_VERSION_NS_3 __NAMESPACE_3_

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target/inc/wmix.h
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/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* This file contains extensions of the WMI protocol specified in the
* Wireless Module Interface (WMI). It includes definitions of all
* extended commands and events. Extensions include useful commands
* that are not directly related to wireless activities. They may
* be hardware-specific, and they might not be supported on all
* implementations.
*
* Extended WMIX commands are encapsulated in a WMI message with
* cmd=WMI_EXTENSION_CMD.
*/
#ifndef _WMIX_H_
#define _WMIX_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Extended WMI commands are those that are needed during wireless
* operation, but which are not really wireless commands. This allows,
* for instance, platform-specific commands. Extended WMI commands are
* embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
* Extended WMI events are similarly embedded in a WMI event message with
* WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
*/
typedef struct {
A_UINT32 commandId;
} POSTPACK WMIX_CMD_HDR;
typedef enum {
WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
WMIX_DSETDATA_REPLY_CMDID,
WMIX_HB_CHALLENGE_RESP_CMDID,
WMIX_DBGLOG_CFG_MODULE_CMDID,
WMIX_PROF_CFG_CMDID, /* 0x200a */
WMIX_PROF_ADDR_SET_CMDID,
WMIX_PROF_START_CMDID,
WMIX_PROF_STOP_CMDID,
WMIX_PROF_COUNT_GET_CMDID,
} WMIX_COMMAND_ID;
typedef enum {
WMIX_DSETOPENREQ_EVENTID = 0x3001,
WMIX_DSETCLOSE_EVENTID,
WMIX_DSETDATAREQ_EVENTID,
WMIX_HB_CHALLENGE_RESP_EVENTID,
WMIX_DBGLOG_EVENTID,
WMIX_PROF_COUNT_EVENTID,
WMIX_PKTLOG_EVENTID,
} WMIX_EVENT_ID;
/*
* =============DataSet support=================
*/
/*
* WMIX_DSETOPENREQ_EVENTID
* DataSet Open Request Event
*/
typedef struct {
A_UINT32 dset_id;
A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} POSTPACK WMIX_DSETOPENREQ_EVENT;
/*
* WMIX_DSETCLOSE_EVENTID
* DataSet Close Event
*/
typedef struct {
A_UINT32 access_cookie;
} POSTPACK WMIX_DSETCLOSE_EVENT;
/*
* WMIX_DSETDATAREQ_EVENTID
* DataSet Data Request Event
*/
typedef struct {
A_UINT32 access_cookie;
A_UINT32 offset;
A_UINT32 length;
A_UINT32 targ_buf; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} WMIX_DSETDATAREQ_EVENT;
typedef struct {
A_UINT32 status;
A_UINT32 targ_dset_handle;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 access_cookie;
A_UINT32 size;
A_UINT32 version;
} WMIX_DSETOPEN_REPLY_CMD;
typedef struct {
A_UINT32 status;
A_UINT32 targ_buf;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 length;
A_UINT8 buf[1];
} WMIX_DSETDATA_REPLY_CMD;
/*
* =============Error Detection support=================
*/
/*
* WMIX_HB_CHALLENGE_RESP_CMDID
* Heartbeat Challenge Response command
*/
typedef struct {
A_UINT32 cookie;
A_UINT32 source;
} WMIX_HB_CHALLENGE_RESP_CMD;
/*
* WMIX_HB_CHALLENGE_RESP_EVENTID
* Heartbeat Challenge Response Event
*/
#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
/*
* =============Target Profiling support=================
*/
typedef struct {
A_UINT32 period; /* Time (in 30.5us ticks) between samples */
A_UINT32 nbins;
} WMIX_PROF_CFG_CMD;
typedef struct {
A_UINT32 addr;
} WMIX_PROF_ADDR_SET_CMD;
/*
* Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
* using a WMIX_PROF_COUNT_EVENT with
* addr set to the next address
* count set to the corresponding count
*/
typedef struct {
A_UINT32 addr;
A_UINT32 count;
} WMIX_PROF_COUNT_EVENT;
#ifdef __cplusplus
}
#endif
#endif /* _WMIX_H_ */