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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
soc: imx: gpcv2: add support for i.MX8MQ SoC
The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
This commit is contained in:
Lucas Stach
Shawn Guo
parent
e125dcba83
commit
685efffe37
5 changed files with 237 additions and 7 deletions
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@ -1,8 +1,8 @@
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menu "i.MX SoC drivers"
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config IMX7_PM_DOMAINS
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bool "i.MX7 PM domains"
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depends on SOC_IMX7D || (COMPILE_TEST && OF)
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config IMX_GPCV2_PM_DOMAINS
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bool "i.MX GPCv2 PM domains"
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depends on SOC_IMX7D || SOC_IMX8MQ || (COMPILE_TEST && OF)
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depends on PM
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select PM_GENERIC_DOMAINS
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default y if SOC_IMX7D
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@ -1,2 +1,2 @@
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obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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obj-$(CONFIG_IMX7_PM_DOMAINS) += gpcv2.o
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obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
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@ -14,24 +14,55 @@
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/power/imx7-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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#define GPC_LPCR_A_CORE_BSC 0x000
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#define GPC_PGC_CPU_MAPPING 0x0ec
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#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
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#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
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#define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4)
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#define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3)
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#define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2)
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#define IMX8M_PCIE2_A53_DOMAIN BIT(15)
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#define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14)
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#define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13)
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#define IMX8M_DISP_A53_DOMAIN BIT(12)
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#define IMX8M_HDMI_A53_DOMAIN BIT(11)
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#define IMX8M_VPU_A53_DOMAIN BIT(10)
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#define IMX8M_GPU_A53_DOMAIN BIT(9)
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#define IMX8M_DDR2_A53_DOMAIN BIT(8)
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#define IMX8M_DDR1_A53_DOMAIN BIT(7)
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#define IMX8M_OTG2_A53_DOMAIN BIT(5)
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#define IMX8M_OTG1_A53_DOMAIN BIT(4)
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#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
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#define IMX8M_MIPI_A53_DOMAIN BIT(2)
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
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#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
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#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
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#define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
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#define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
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#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
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#define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12)
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#define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11)
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#define IMX8M_DISP_SW_Pxx_REQ BIT(10)
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#define IMX8M_HDMI_SW_Pxx_REQ BIT(9)
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#define IMX8M_VPU_SW_Pxx_REQ BIT(8)
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#define IMX8M_GPU_SW_Pxx_REQ BIT(7)
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#define IMX8M_DDR2_SW_Pxx_REQ BIT(6)
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#define IMX8M_DDR1_SW_Pxx_REQ BIT(5)
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#define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
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#define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
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#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
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#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
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#define GPC_M4_PU_PDN_FLG 0x1bc
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/*
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@ -43,6 +74,19 @@
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#define IMX7_PGC_MIPI 16
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#define IMX7_PGC_PCIE 17
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#define IMX7_PGC_USB_HSIC 20
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#define IMX8M_PGC_MIPI 16
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#define IMX8M_PGC_PCIE1 17
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#define IMX8M_PGC_OTG1 18
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#define IMX8M_PGC_OTG2 19
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#define IMX8M_PGC_DDR1 21
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#define IMX8M_PGC_GPU 23
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#define IMX8M_PGC_VPU 24
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#define IMX8M_PGC_DISP 26
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#define IMX8M_PGC_MIPI_CSI1 27
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#define IMX8M_PGC_MIPI_CSI2 28
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#define IMX8M_PGC_PCIE2 29
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#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
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#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
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@ -221,6 +265,167 @@ static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
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.reg_access_table = &imx7_access_table,
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};
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static const struct imx_pgc_domain imx8m_pgc_domains[] = {
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[IMX8M_POWER_DOMAIN_MIPI] = {
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.genpd = {
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.name = "mipi",
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},
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.bits = {
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.pxx = IMX8M_MIPI_SW_Pxx_REQ,
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.map = IMX8M_MIPI_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_MIPI,
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},
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[IMX8M_POWER_DOMAIN_PCIE1] = {
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.genpd = {
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.name = "pcie1",
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},
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.bits = {
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.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
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.map = IMX8M_PCIE1_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_PCIE1,
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},
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[IMX8M_POWER_DOMAIN_USB_OTG1] = {
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.genpd = {
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.name = "usb-otg1",
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},
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.bits = {
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.pxx = IMX8M_OTG1_SW_Pxx_REQ,
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.map = IMX8M_OTG1_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_OTG1,
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},
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[IMX8M_POWER_DOMAIN_USB_OTG2] = {
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.genpd = {
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.name = "usb-otg2",
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},
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.bits = {
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.pxx = IMX8M_OTG2_SW_Pxx_REQ,
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.map = IMX8M_OTG2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_OTG2,
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},
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[IMX8M_POWER_DOMAIN_DDR1] = {
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.genpd = {
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.name = "ddr1",
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},
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.bits = {
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.pxx = IMX8M_DDR1_SW_Pxx_REQ,
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.map = IMX8M_DDR2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_DDR1,
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},
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[IMX8M_POWER_DOMAIN_GPU] = {
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.genpd = {
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.name = "gpu",
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},
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.bits = {
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.pxx = IMX8M_GPU_SW_Pxx_REQ,
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.map = IMX8M_GPU_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_GPU,
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},
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[IMX8M_POWER_DOMAIN_VPU] = {
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.genpd = {
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.name = "vpu",
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},
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.bits = {
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.pxx = IMX8M_VPU_SW_Pxx_REQ,
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.map = IMX8M_VPU_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_VPU,
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},
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[IMX8M_POWER_DOMAIN_DISP] = {
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.genpd = {
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.name = "disp",
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},
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.bits = {
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.pxx = IMX8M_DISP_SW_Pxx_REQ,
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.map = IMX8M_DISP_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_DISP,
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},
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[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
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.genpd = {
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.name = "mipi-csi1",
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},
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.bits = {
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.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
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.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_MIPI_CSI1,
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},
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[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
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.genpd = {
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.name = "mipi-csi2",
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},
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.bits = {
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.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
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.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_MIPI_CSI2,
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},
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[IMX8M_POWER_DOMAIN_PCIE2] = {
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.genpd = {
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.name = "pcie2",
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},
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.bits = {
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.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
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.map = IMX8M_PCIE2_A53_DOMAIN,
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},
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.pgc = IMX8M_PGC_PCIE2,
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},
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};
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static const struct regmap_range imx8m_yes_ranges[] = {
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regmap_reg_range(GPC_LPCR_A_CORE_BSC,
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GPC_M4_PU_PDN_FLG),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
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GPC_PGC_SR(IMX8M_PGC_MIPI)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
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GPC_PGC_SR(IMX8M_PGC_PCIE1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
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GPC_PGC_SR(IMX8M_PGC_OTG1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
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GPC_PGC_SR(IMX8M_PGC_OTG2)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
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GPC_PGC_SR(IMX8M_PGC_DDR1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
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GPC_PGC_SR(IMX8M_PGC_GPU)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
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GPC_PGC_SR(IMX8M_PGC_VPU)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
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GPC_PGC_SR(IMX8M_PGC_DISP)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
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GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
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GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
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regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
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GPC_PGC_SR(IMX8M_PGC_PCIE2)),
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};
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static const struct regmap_access_table imx8m_access_table = {
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.yes_ranges = imx8m_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges),
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};
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static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
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.domains = imx8m_pgc_domains,
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.domains_num = ARRAY_SIZE(imx8m_pgc_domains),
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.reg_access_table = &imx8m_access_table,
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};
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static int imx_pgc_domain_probe(struct platform_device *pdev)
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{
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struct imx_pgc_domain *domain = pdev->dev.platform_data;
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@ -235,7 +440,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
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dev_err(domain->dev, "Failed to get domain's regulator\n");
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return PTR_ERR(domain->regulator);
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}
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} else {
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} else if (domain->voltage) {
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regulator_set_voltage(domain->regulator,
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domain->voltage, domain->voltage);
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}
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@ -376,6 +581,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
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static const struct of_device_id imx_gpcv2_dt_ids[] = {
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{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
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{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
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{ }
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};
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