From ca3f7925dd9a257b2d80e7ebf3c27d451fb6887f Mon Sep 17 00:00:00 2001
From: Sarthak Garg <sartgarg@qti.qualcomm.com>
Date: Tue, 11 Aug 2020 21:28:21 +0530
Subject: [PATCH] ARM: dts: msm: Add ice core clock node for shima

Add ice core clock node in the devicetree file for shima.

Change-Id: I77221a48b93e99e4faa451b2f58ef256f585af52
---
 qcom/shima.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index e6c611317c2d..1df27e985007 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -1508,8 +1508,12 @@
 				<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hc_irq", "pwr_irq";
 
-		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
-		clock-names = "core", "iface";
+		clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+			<&gcc GCC_SDCC1_AHB_CLK>,
+			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
+		clock-names = "core", "iface", "ice_core";
+
+		qcom,ice-clk-rates = <300000000 100000000>;
 
 		interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
 			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDC_1>;