diff --git a/drivers/clk/qcom/clk-regmap-mux-div.c b/drivers/clk/qcom/clk-regmap-mux-div.c
index 4ec0a09ffc66..26d48a65bd37 100644
--- a/drivers/clk/qcom/clk-regmap-mux-div.c
+++ b/drivers/clk/qcom/clk-regmap-mux-div.c
@@ -150,7 +150,7 @@ static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
 
 			if (is_better_rate(rate, best_rate, actual_rate)) {
 				best_rate = actual_rate;
-				best_src = md->parent_map[i];
+				best_src = md->parent_map[i].cfg;
 				best_div = div - 1;
 			}
 
@@ -177,7 +177,7 @@ static u8 mux_div_get_parent(struct clk_hw *hw)
 	mux_div_get_src_div(md, &src, &div);
 
 	for (i = 0; i < clk_hw_get_num_parents(hw); i++)
-		if (src == md->parent_map[i])
+		if (src == md->parent_map[i].cfg)
 			return i;
 
 	pr_err("%s: Can't find parent with src %d\n", name, src);
@@ -188,7 +188,7 @@ static int mux_div_set_parent(struct clk_hw *hw, u8 index)
 {
 	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
 
-	return mux_div_set_src_div(md, md->parent_map[index], md->div);
+	return mux_div_set_src_div(md, md->parent_map[index].cfg, md->div);
 }
 
 static int mux_div_set_rate(struct clk_hw *hw,
@@ -205,7 +205,7 @@ static int mux_div_set_rate_and_parent(struct clk_hw *hw,  unsigned long rate,
 	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
 
 	return __mux_div_set_rate_and_parent(hw, rate, prate,
-					     md->parent_map[index]);
+					     md->parent_map[index].cfg);
 }
 
 static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
@@ -217,7 +217,7 @@ static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
 
 	mux_div_get_src_div(md, &src, &div);
 	for (i = 0; i < num_parents; i++)
-		if (src == md->parent_map[i]) {
+		if (src == md->parent_map[i].cfg) {
 			struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
 			unsigned long parent_rate = clk_hw_get_rate(p);
 
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.h b/drivers/clk/qcom/clk-regmap-mux-div.h
index 70215e8ff63f..08acb529f36f 100644
--- a/drivers/clk/qcom/clk-regmap-mux-div.h
+++ b/drivers/clk/qcom/clk-regmap-mux-div.h
@@ -19,7 +19,7 @@
  * @src_shift:	lowest bit of source select field
  * @div:	the divider raw configuration value
  * @src:	the mux index which will be used if the clock is enabled
- * @parent_map: map from parent_names index to src_sel field
+ * @parent_map: pointer to parent_map struct
  * @clkr:	handle between common and hardware-specific interfaces
  * @pclk:	the input PLL clock
  * @clk_nb:	clock notifier for rate changes of the input PLL
@@ -32,7 +32,7 @@ struct clk_regmap_mux_div {
 	u32				src_shift;
 	u32				div;
 	u32				src;
-	const u32			*parent_map;
+	const struct parent_map		*parent_map;
 	struct clk_regmap		clkr;
 	struct clk			*pclk;
 	struct notifier_block		clk_nb;