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[MIPS] Delete Ocelot 3 support.

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Signed-off-by: Ralf Baechle <[email protected]>
This commit is contained in:
Ralf Baechle 2007-07-09 16:29:16 +01:00
commit 688b3d7208
62 changed files with 3 additions and 2732 deletions
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48
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
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@ -1,48 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 MontaVista Software Inc.
* Author: Manish Lachwani, mlachwani@mvista.com
* Copyright (C) 2004 Ralf Baechle
*/
#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
/*
* Momentum Ocelot-3 is based on Rm7900 processor which
* is based on the E9000 core.
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */

4
include/asm-mips/war.h
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@ -183,8 +183,8 @@
*/
#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \
defined(CONFIG_MOMENCO_OCELOT_3) || defined(CONFIG_PMC_YOSEMITE) || \
defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
defined(CONFIG_WR_PPMC)
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif