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clk: samsung: exynos5410: Add gate clock for ADC

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Add the gate clock for ADC block on Exynos5410.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Sylwester Nawrocki <[email protected]>
This commit is contained in:
Krzysztof Kozlowski 2019-02-12 18:50:51 +01:00 • committed by Sylwester Nawrocki
commit 691dc38276
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/samsung/clk-exynos5410.c
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@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",