A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-09 05:39:54 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge "clk: qcom: alpha-pll: Add odd/even support for Trion PLL"

Browse source
This commit is contained in:
qctecmdr 2020-06-22 04:57:00 -07:00 • committed by Gerrit - the friendly Code Review server
commit 699da85287
1 changed files with 14 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

18
drivers/clk/qcom/clk-alpha-pll.c
View file

@ -41,7 +41,7 @@
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
# define PLL_POST_DIV_SHIFT 8
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
# define PLL_ALPHA_EN BIT(24)
# define PLL_ALPHA_MODE BIT(25)
# define PLL_VCO_SHIFT 20
@ -1184,7 +1184,7 @@ static void clk_trion_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},
{"PLL_STATUS", PLL_OFF_STATUS},
{"PLL_OPMODE", PLL_OFF_MODE},
{"PLL_OPMODE", PLL_OFF_OPMODE},
{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
};
@ -2330,6 +2330,11 @@ clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
struct regmap *regmap = pll->clkr.regmap;
u32 i, div = 1, val;
if (!pll->post_div_table) {
pr_err("Missing the post_div_table for the PLL\n");
return -EINVAL;
}
regmap_read(regmap, PLL_USER_CTL(pll), &val);
val >>= pll->post_div_shift;
@ -2363,6 +2368,11 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
struct regmap *regmap = pll->clkr.regmap;
int i, val = 0, div;
if (!pll->post_div_table) {
pr_err("Missing the post_div_table for the PLL\n");
return -EINVAL;
}
div = DIV_ROUND_UP_ULL(parent_rate, rate);
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].div == div) {
@ -2372,8 +2382,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
}
return regmap_update_bits(regmap, PLL_USER_CTL(pll),
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
val << PLL_POST_DIV_SHIFT);
PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
val << pll->post_div_shift);
}
const struct clk_ops clk_trion_pll_postdiv_ops = {