A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: Add apss dl cti0 for shima

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Add app dl cti0 to device tree for DCC LLCC timeout on shima.

Change-Id: I8f8bd5626a848c015631849b1790e18582109c22
This commit is contained in:
Tao Zhang 2021-05-27 18:08:59 +08:00
commit 69ac018809
1 changed files with 12 additions and 0 deletions
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12
qcom/shima-coresight.dtsi
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@ -3598,6 +3598,18 @@
clock-names = "apb_pclk";
};
cti0_apss_dl: cti@7862000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb966>;
reg = <0x7862000 0x1000>;
reg-names = "cti-base";
coresight-name = "coresight-cti-apss_dl_cti0";
clocks = <&aopcc QDSS_CLK>;
clock-names = "apb_pclk";
};
snoc: snoc {
compatible = "qcom,coresight-dummy";
coresight-name = "coresight-snoc";