From 69c24f5a32edc8c12bcbc02e79bdb199c6ba29ab Mon Sep 17 00:00:00 2001 From: Raviteja Tamatam Date: Thu, 21 Nov 2019 18:22:11 +0530 Subject: [PATCH] disp: msm: sde: update BW_INDICATION programing sequence BW_INDICATION indication must be programed before BWI_THRESHOLD. Otherwise, it will revert to legacy behaviour and rsc wakeup is delayed by one vsync causing janks. In current code BW_INDICATION is done after LM/SSPP programming and plane fence wait. Moved the perf_crtc_update before this and just after ctl prepare configuration to avoid chances of BW_INDICATION crossing BWI_THRESHOLD time. Change-Id: Ie976720910c34aaf140f1ce7daef38ba20bc10f5 Signed-off-by: Raviteja Tamatam --- msm/sde/sde_crtc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/msm/sde/sde_crtc.c b/msm/sde/sde_crtc.c index 1e6002ce8e07..8fc5a2b5c5dd 100644 --- a/msm/sde/sde_crtc.c +++ b/msm/sde/sde_crtc.c @@ -3143,6 +3143,9 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc, sde_encoder_trigger_kickoff_pending(encoder); } + /* update performance setting */ + sde_core_perf_crtc_update(crtc, 1, false); + /* * If no mixers have been allocated in sde_crtc_atomic_check(), * it means we are trying to flush a CRTC whose state is disabled: @@ -3290,9 +3293,6 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc, cstate->rsc_update = true; } - /* update performance setting before crtc kickoff */ - sde_core_perf_crtc_update(crtc, 1, false); - /* * Final plane updates: Give each plane a chance to complete all * required writes/flushing before crtc's "flush