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[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation

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Patch from Catalin Marinas

Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).

Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.

Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Catalin Marinas 2006-03-07 14:42:27 +00:00 • committed by Russell King
commit 6a0e243069
3 changed files with 8 additions and 1 deletions
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6
include/asm-arm/tlbflush.h
View file

@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
/* The ARM ARM states that the completion of a TLB maintenance
* operation is only guaranteed by a DSB instruction
*/
if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
}
/*