diff --git a/hal/wifi3.0/hal_srng.c b/hal/wifi3.0/hal_srng.c index 1560f70ea820..7e2bcf4287c6 100644 --- a/hal/wifi3.0/hal_srng.c +++ b/hal/wifi3.0/hal_srng.c @@ -27,15 +27,12 @@ void hal_qca6290_attach(struct hal_soc *hal); #ifdef QCA_WIFI_QCA8074 void hal_qca8074_attach(struct hal_soc *hal); #endif -#ifdef QCA_WIFI_QCA8074V2 +#if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) void hal_qca8074v2_attach(struct hal_soc *hal); #endif #ifdef QCA_WIFI_QCA6390 void hal_qca6390_attach(struct hal_soc *hal); #endif -#ifdef QCA_WIFI_QCA6018 -void hal_qca6018_attach(struct hal_soc *hal); -#endif #ifdef ENABLE_VERBOSE_DEBUG bool is_hal_verbose_debug_enabled; @@ -261,7 +258,7 @@ static void hal_target_based_configure(struct hal_soc *hal) #if defined(QCA_WIFI_QCA6018) && defined(CONFIG_WIN) case TARGET_TYPE_QCA6018: - hal_qca6018_attach(hal); + hal_qca8074v2_attach(hal); break; #endif default: diff --git a/hal/wifi3.0/qca6018/hal_6018.c b/hal/wifi3.0/qca6018/hal_6018.c deleted file mode 100644 index 697f2d1961f8..000000000000 --- a/hal/wifi3.0/qca6018/hal_6018.c +++ /dev/null @@ -1,601 +0,0 @@ -/* - * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all - * copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL - * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE - * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL - * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR - * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "hal_hw_headers.h" -#include "hal_internal.h" -#include "hal_api.h" -#include "target_type.h" -#include "wcss_version.h" -#include "qdf_module.h" - -#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ - RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET -#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ - RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK -#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ - RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB -#define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ - PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET -#define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ - PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET -#define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ - PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET -#define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ - PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET -#define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ - PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET -#define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ - PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET -#define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ - PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET -#define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ - PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET -#define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ - PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET -#define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ - PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET -#define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ - PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET -#define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ - RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET -#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ - RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET -#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ - RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET -#define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ - RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET -#define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ - REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET -#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ - STATUS_HEADER_REO_STATUS_NUMBER -#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ - STATUS_HEADER_TIMESTAMP -#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ - RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET -#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ - RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET -#define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ - TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET -#define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ - TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET -#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ - TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET -#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ - BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB -#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ - BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK -#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ - BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB -#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ - BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK -#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ - BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB -#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ - BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK -#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ - BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB -#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ - BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK -#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ - TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB -#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ - TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK -#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ - WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK -#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ - WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET -#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ - WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB -#include "hal_6018_tx.h" -#include "hal_6018_rx.h" -#include -#include - -struct hal_hw_txrx_ops qca6018_hal_hw_txrx_ops = { - /* init and setup */ - hal_srng_dst_hw_init_generic, - hal_srng_src_hw_init_generic, - hal_get_hw_hptp_generic, - hal_reo_setup_generic, - hal_setup_link_idle_list_generic, - - /* tx */ - hal_tx_desc_set_dscp_tid_table_id_6018, - hal_tx_set_dscp_tid_map_6018, - hal_tx_update_dscp_tid_6018, - hal_tx_desc_set_lmac_id_6018, - hal_tx_desc_set_buf_addr_generic, - hal_tx_desc_set_search_type_generic, - hal_tx_desc_set_search_index_generic, - hal_tx_comp_get_status_generic, - hal_tx_comp_get_release_reason_generic, - - /* rx */ - hal_rx_msdu_start_nss_get_6018, - hal_rx_mon_hw_desc_get_mpdu_status_6018, - hal_rx_get_tlv_6018, - hal_rx_proc_phyrx_other_receive_info_tlv_6018, - hal_rx_dump_msdu_start_tlv_6018, - hal_rx_dump_msdu_end_tlv_6018, - hal_get_link_desc_size_6018, - hal_rx_mpdu_start_tid_get_6018, - hal_rx_msdu_start_reception_type_get_6018, - hal_rx_msdu_end_da_idx_get_6018, - hal_rx_msdu_desc_info_get_ptr_generic, - hal_rx_link_desc_msdu0_ptr_generic, - hal_reo_status_get_header_generic, - hal_rx_status_get_tlv_info_generic, - hal_rx_wbm_err_info_get_generic, - hal_rx_dump_mpdu_start_tlv_generic, - - hal_tx_set_pcp_tid_map_generic, - hal_tx_update_pcp_tid_generic, - hal_tx_update_tidmap_prty_generic, -}; - -struct hal_hw_srng_config hw_srng_table_6018[] = { - /* TODO: max_rings can populated by querying HW capabilities */ - { /* REO_DST */ - .start_ring_id = HAL_SRNG_REO2SW1, - .max_rings = 4, - .entry_size = sizeof(struct reo_destination_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_DST_RING, - .reg_start = { - HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET), - HWIO_REO_R2_REO2SW1_RING_HP_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET) - }, - .reg_size = { - HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - - HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), - HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - - HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), - }, - .max_size = - HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* REO_EXCEPTION */ - /* Designating REO2TCL ring as exception ring. This ring is - * similar to other REO2SW rings though it is named as REO2TCL. - * Any of theREO2SW rings can be used as exception ring. - */ - .start_ring_id = HAL_SRNG_REO2TCL, - .max_rings = 1, - .entry_size = sizeof(struct reo_destination_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_DST_RING, - .reg_start = { - HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET), - HWIO_REO_R2_REO2TCL_RING_HP_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET) - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = - HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* REO_REINJECT */ - .start_ring_id = HAL_SRNG_SW2REO, - .max_rings = 1, - .entry_size = sizeof(struct reo_entrance_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET), - HWIO_REO_R2_SW2REO_RING_HP_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET) - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* REO_CMD */ - .start_ring_id = HAL_SRNG_REO_CMD, - .max_rings = 1, - .entry_size = (sizeof(struct tlv_32_hdr) + - sizeof(struct reo_get_queue_stats)) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET), - HWIO_REO_R2_REO_CMD_RING_HP_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET), - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* REO_STATUS */ - .start_ring_id = HAL_SRNG_REO_STATUS, - .max_rings = 1, - .entry_size = (sizeof(struct tlv_32_hdr) + - sizeof(struct reo_get_queue_stats_status)) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_DST_RING, - .reg_start = { - HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET), - HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( - SEQ_WCSS_UMAC_REO_REG_OFFSET), - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = - HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* TCL_DATA */ - .start_ring_id = HAL_SRNG_SW2TCL1, - .max_rings = 3, - .entry_size = (sizeof(struct tlv_32_hdr) + - sizeof(struct tcl_data_cmd)) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), - HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), - }, - .reg_size = { - HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - - HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), - HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - - HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), - }, - .max_size = - HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* TCL_CMD */ - .start_ring_id = HAL_SRNG_SW2TCL_CMD, - .max_rings = 1, - .entry_size = (sizeof(struct tlv_32_hdr) + - sizeof(struct tcl_gse_cmd)) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), - HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = - HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* TCL_STATUS */ - .start_ring_id = HAL_SRNG_TCL_STATUS, - .max_rings = 1, - .entry_size = (sizeof(struct tlv_32_hdr) + - sizeof(struct tcl_status_ring)) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_DST_RING, - .reg_start = { - HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), - HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = - HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* CE_SRC */ - .start_ring_id = HAL_SRNG_CE_0_SRC, - .max_rings = 12, - .entry_size = sizeof(struct ce_src_desc) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), - HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), - }, - .reg_size = { - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, - }, - .max_size = - HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* CE_DST */ - .start_ring_id = HAL_SRNG_CE_0_DST, - .max_rings = 12, - .entry_size = 8 >> 2, - /*TODO: entry_size above should actually be - * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition - * of struct ce_dst_desc in HW header files - */ - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), - HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), - }, - .reg_size = { - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, - }, - .max_size = - HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* CE_DST_STATUS */ - .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, - .max_rings = 12, - .entry_size = sizeof(struct ce_stat_desc) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_DST_RING, - .reg_start = { - HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), - HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), - }, - /* TODO: check destination status ring registers */ - .reg_size = { - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, - }, - .max_size = - HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* WBM_IDLE_LINK */ - .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, - .max_rings = 1, - .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = - HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* SW2WBM_RELEASE */ - .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, - .max_rings = 1, - .entry_size = sizeof(struct wbm_release_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = - HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* WBM2SW_RELEASE */ - .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, - .max_rings = 4, - .entry_size = sizeof(struct wbm_release_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_DST_RING, - .reg_start = { - HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - }, - .reg_size = { - HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - - HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - - HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), - }, - .max_size = - HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* RXDMA_BUF */ - .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, -#ifdef IPA_OFFLOAD - .max_rings = 3, -#else - .max_rings = 2, -#endif - .entry_size = sizeof(struct wbm_buffer_ring) >> 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_SRC_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, - { /* RXDMA_DST */ - .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, - .max_rings = 1, - .entry_size = sizeof(struct reo_entrance_ring) >> 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_DST_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, - { /* RXDMA_MONITOR_BUF */ - .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, - .max_rings = 1, - .entry_size = sizeof(struct wbm_buffer_ring) >> 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_SRC_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, - { /* RXDMA_MONITOR_STATUS */ - .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, - .max_rings = 1, - .entry_size = sizeof(struct wbm_buffer_ring) >> 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_SRC_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, - { /* RXDMA_MONITOR_DST */ - .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, - .max_rings = 1, - .entry_size = sizeof(struct reo_entrance_ring) >> 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_DST_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, - { /* RXDMA_MONITOR_DESC */ - .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, - .max_rings = 1, - .entry_size = sizeof(struct wbm_buffer_ring) >> 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_SRC_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, - { /* DIR_BUF_RX_DMA_SRC */ - .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, - .max_rings = 1, - .entry_size = 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_SRC_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, -#ifdef WLAN_FEATURE_CIF_CFR - { /* WIFI_POS_SRC */ - .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, - .max_rings = 1, - .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, - .lmac_ring = TRUE, - .ring_dir = HAL_SRNG_SRC_RING, - /* reg_start is not set because LMAC rings are not accessed - * from host - */ - .reg_start = {}, - .reg_size = {}, - .max_size = HAL_RXDMA_MAX_RING_SIZE, - }, -#endif -}; - -int32_t hal_hw_reg_offset_qca6018[] = { - /* dst */ - REG_OFFSET(DST, HP), - REG_OFFSET(DST, TP), - REG_OFFSET(DST, ID), - REG_OFFSET(DST, MISC), - REG_OFFSET(DST, HP_ADDR_LSB), - REG_OFFSET(DST, HP_ADDR_MSB), - REG_OFFSET(DST, MSI1_BASE_LSB), - REG_OFFSET(DST, MSI1_BASE_MSB), - REG_OFFSET(DST, MSI1_DATA), - REG_OFFSET(DST, BASE_LSB), - REG_OFFSET(DST, BASE_MSB), - REG_OFFSET(DST, PRODUCER_INT_SETUP), - /* src */ - REG_OFFSET(SRC, HP), - REG_OFFSET(SRC, TP), - REG_OFFSET(SRC, ID), - REG_OFFSET(SRC, MISC), - REG_OFFSET(SRC, TP_ADDR_LSB), - REG_OFFSET(SRC, TP_ADDR_MSB), - REG_OFFSET(SRC, MSI1_BASE_LSB), - REG_OFFSET(SRC, MSI1_BASE_MSB), - REG_OFFSET(SRC, MSI1_DATA), - REG_OFFSET(SRC, BASE_LSB), - REG_OFFSET(SRC, BASE_MSB), - REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), - REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), -}; - -/** - * hal_qca6018_attach() - Attach 6018 target specific hal_soc ops, - * offset and srng table - */ -void hal_qca6018_attach(struct hal_soc *hal_soc) -{ - hal_soc->hw_srng_table = hw_srng_table_6018; - hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6018; - hal_soc->ops = &qca6018_hal_hw_txrx_ops; -} diff --git a/hal/wifi3.0/qca6018/hal_6018_rx.h b/hal/wifi3.0/qca6018/hal_6018_rx.h deleted file mode 100644 index 30d827ebfffb..000000000000 --- a/hal/wifi3.0/qca6018/hal_6018_rx.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all - * copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL - * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE - * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL - * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR - * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "hal_hw_headers.h" -#include "hal_internal.h" -#include "cdp_txrx_mon_struct.h" -#include "qdf_trace.h" -#include "hal_rx.h" -#include "hal_tx.h" -#include "dp_types.h" -#include "hal_api_mon.h" - -#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ - RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ - RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ - RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) -/* - * hal_rx_msdu_start_nss_get_6018(): API to get the NSS - * Interval from rx_msdu_start - * - * @buf: pointer to the start of RX PKT TLV header - * Return: uint32_t(nss) - */ -static uint32_t hal_rx_msdu_start_nss_get_6018(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_msdu_start *msdu_start = - &pkt_tlvs->msdu_start_tlv.rx_msdu_start; - uint8_t mimo_ss_bitmap; - - mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); - - return qdf_get_hweight8(mimo_ss_bitmap); -} - -/** - * hal_rx_mon_hw_desc_get_mpdu_status_6018(): Retrieve MPDU status - * - * @ hw_desc_addr: Start address of Rx HW TLVs - * @ rs: Status for monitor mode - * - * Return: void - */ -static void hal_rx_mon_hw_desc_get_mpdu_status_6018(void *hw_desc_addr, - struct mon_rx_status *rs) -{ - struct rx_msdu_start *rx_msdu_start; - struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; - uint32_t reg_value; - const uint32_t sgi_hw_to_cdp[] = { - CDP_SGI_0_8_US, - CDP_SGI_0_4_US, - CDP_SGI_1_6_US, - CDP_SGI_3_2_US, - }; - - rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; - - HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); - - rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, - RX_MSDU_START_5, USER_RSSI); - rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); - - reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); - rs->sgi = sgi_hw_to_cdp[reg_value]; - reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, PKT_TYPE); - switch (reg_value) { - case HAL_RX_PKT_TYPE_11N: - rs->ht_flags = 1; - break; - case HAL_RX_PKT_TYPE_11AC: - rs->vht_flags = 1; - reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, - RECEIVE_BANDWIDTH); - rs->vht_flag_values2 = reg_value; - break; - case HAL_RX_PKT_TYPE_11AX: - rs->he_flags = 1; - break; - default: - break; - } - reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); - rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; - /* TODO: rs->beamformed should be set for SU beamforming also */ -} - -#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) -static uint32_t hal_get_link_desc_size_6018(void) -{ - return LINK_DESC_SIZE; -} - -/* - * hal_rx_get_tlv_6018(): API to get the tlv - * - * @rx_tlv: TLV data extracted from the rx packet - * Return: uint8_t - */ -static uint8_t hal_rx_get_tlv_6018(void *rx_tlv) -{ - return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); -} - -/** - * hal_rx_proc_phyrx_other_receive_info_tlv_6018() - * -process other receive info TLV - * @rx_tlv_hdr: pointer to TLV header - * @ppdu_info: pointer to ppdu_info - * - * Return: None - */ -static -void hal_rx_proc_phyrx_other_receive_info_tlv_6018(void *rx_tlv_hdr, - void *ppdu_info) -{ -} - - -/** - * hal_rx_dump_msdu_start_tlv_6018() : dump RX msdu_start TLV in structured - * human readable format. - * @ msdu_start: pointer the msdu_start TLV in pkt. - * @ dbg_level: log level. - * - * Return: void - */ -static void hal_rx_dump_msdu_start_tlv_6018(void *msdustart, - uint8_t dbg_level) -{ - struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; - - QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, - "rx_msdu_start tlv - " - "rxpcu_mpdu_filter_in_category: %d " - "sw_frame_group_id: %d " - "phy_ppdu_id: %d " - "msdu_length: %d " - "ipsec_esp: %d " - "l3_offset: %d " - "ipsec_ah: %d " - "l4_offset: %d " - "msdu_number: %d " - "decap_format: %d " - "ipv4_proto: %d " - "ipv6_proto: %d " - "tcp_proto: %d " - "udp_proto: %d " - "ip_frag: %d " - "tcp_only_ack: %d " - "da_is_bcast_mcast: %d " - "ip4_protocol_ip6_next_header: %d " - "toeplitz_hash_2_or_4: %d " - "flow_id_toeplitz: %d " - "user_rssi: %d " - "pkt_type: %d " - "stbc: %d " - "sgi: %d " - "rate_mcs: %d " - "receive_bandwidth: %d " - "reception_type: %d " - "ppdu_start_timestamp: %d " - "sw_phy_meta_data: %d ", - msdu_start->rxpcu_mpdu_filter_in_category, - msdu_start->sw_frame_group_id, - msdu_start->phy_ppdu_id, - msdu_start->msdu_length, - msdu_start->ipsec_esp, - msdu_start->l3_offset, - msdu_start->ipsec_ah, - msdu_start->l4_offset, - msdu_start->msdu_number, - msdu_start->decap_format, - msdu_start->ipv4_proto, - msdu_start->ipv6_proto, - msdu_start->tcp_proto, - msdu_start->udp_proto, - msdu_start->ip_frag, - msdu_start->tcp_only_ack, - msdu_start->da_is_bcast_mcast, - msdu_start->ip4_protocol_ip6_next_header, - msdu_start->toeplitz_hash_2_or_4, - msdu_start->flow_id_toeplitz, - msdu_start->user_rssi, - msdu_start->pkt_type, - msdu_start->stbc, - msdu_start->sgi, - msdu_start->rate_mcs, - msdu_start->receive_bandwidth, - msdu_start->reception_type, - msdu_start->ppdu_start_timestamp, - msdu_start->sw_phy_meta_data); -} - -/** - * hal_rx_dump_msdu_end_tlv_6018: dump RX msdu_end TLV in structured - * human readable format. - * @ msdu_end: pointer the msdu_end TLV in pkt. - * @ dbg_level: log level. - * - * Return: void - */ -static void hal_rx_dump_msdu_end_tlv_6018(void *msduend, - uint8_t dbg_level) -{ - struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; - - QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, - "rx_msdu_end tlv - " - "rxpcu_mpdu_filter_in_category: %d " - "sw_frame_group_id: %d " - "phy_ppdu_id: %d " - "ip_hdr_chksum: %d " - "tcp_udp_chksum: %d " - "key_id_octet: %d " - "cce_super_rule: %d " - "cce_classify_not_done_truncat: %d " - "cce_classify_not_done_cce_dis: %d " - "ext_wapi_pn_63_48: %d " - "ext_wapi_pn_95_64: %d " - "ext_wapi_pn_127_96: %d " - "reported_mpdu_length: %d " - "first_msdu: %d " - "last_msdu: %d " - "sa_idx_timeout: %d " - "da_idx_timeout: %d " - "msdu_limit_error: %d " - "flow_idx_timeout: %d " - "flow_idx_invalid: %d " - "wifi_parser_error: %d " - "amsdu_parser_error: %d " - "sa_is_valid: %d " - "da_is_valid: %d " - "da_is_mcbc: %d " - "l3_header_padding: %d " - "ipv6_options_crc: %d " - "tcp_seq_number: %d " - "tcp_ack_number: %d " - "tcp_flag: %d " - "lro_eligible: %d " - "window_size: %d " - "da_offset: %d " - "sa_offset: %d " - "da_offset_valid: %d " - "sa_offset_valid: %d " - "rule_indication_31_0: %d " - "rule_indication_63_32: %d " - "sa_idx: %d " - "msdu_drop: %d " - "reo_destination_indication: %d " - "flow_idx: %d " - "fse_metadata: %d " - "cce_metadata: %d " - "sa_sw_peer_id: %d ", - msdu_end->rxpcu_mpdu_filter_in_category, - msdu_end->sw_frame_group_id, - msdu_end->phy_ppdu_id, - msdu_end->ip_hdr_chksum, - msdu_end->tcp_udp_chksum, - msdu_end->key_id_octet, - msdu_end->cce_super_rule, - msdu_end->cce_classify_not_done_truncate, - msdu_end->cce_classify_not_done_cce_dis, - msdu_end->ext_wapi_pn_63_48, - msdu_end->ext_wapi_pn_95_64, - msdu_end->ext_wapi_pn_127_96, - msdu_end->reported_mpdu_length, - msdu_end->first_msdu, - msdu_end->last_msdu, - msdu_end->sa_idx_timeout, - msdu_end->da_idx_timeout, - msdu_end->msdu_limit_error, - msdu_end->flow_idx_timeout, - msdu_end->flow_idx_invalid, - msdu_end->wifi_parser_error, - msdu_end->amsdu_parser_error, - msdu_end->sa_is_valid, - msdu_end->da_is_valid, - msdu_end->da_is_mcbc, - msdu_end->l3_header_padding, - msdu_end->ipv6_options_crc, - msdu_end->tcp_seq_number, - msdu_end->tcp_ack_number, - msdu_end->tcp_flag, - msdu_end->lro_eligible, - msdu_end->window_size, - msdu_end->da_offset, - msdu_end->sa_offset, - msdu_end->da_offset_valid, - msdu_end->sa_offset_valid, - msdu_end->rule_indication_31_0, - msdu_end->rule_indication_63_32, - msdu_end->sa_idx, - msdu_end->msdu_drop, - msdu_end->reo_destination_indication, - msdu_end->flow_idx, - msdu_end->fse_metadata, - msdu_end->cce_metadata, - msdu_end->sa_sw_peer_id); -} - -/* - * Get tid from RX_MPDU_START - */ -#define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ - RX_MPDU_INFO_3_TID_OFFSET)), \ - RX_MPDU_INFO_3_TID_MASK, \ - RX_MPDU_INFO_3_TID_LSB)) - -static uint32_t hal_rx_mpdu_start_tid_get_6018(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_mpdu_start *mpdu_start = - &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; - uint32_t tid; - - tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); - - return tid; -} - -#define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ - RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ - RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ - RX_MSDU_START_5_RECEPTION_TYPE_LSB)) - -/* - * hal_rx_msdu_start_reception_type_get(): API to get the reception type - * Interval from rx_msdu_start - * - * @buf: pointer to the start of RX PKT TLV header - * Return: uint32_t(reception_type) - */ -static uint32_t hal_rx_msdu_start_reception_type_get_6018(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_msdu_start *msdu_start = - &pkt_tlvs->msdu_start_tlv.rx_msdu_start; - uint32_t reception_type; - - reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); - - return reception_type; -} - -/* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */ -#define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ - RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ - RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) - /** - * hal_rx_msdu_end_da_idx_get_6018: API to get da_idx - * from rx_msdu_end TLV - * - * @ buf: pointer to the start of RX PKT TLV headers - * Return: da index - */ -static uint16_t hal_rx_msdu_end_da_idx_get_6018(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; - uint16_t da_idx; - - da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); - - return da_idx; -} - diff --git a/hal/wifi3.0/qca6018/hal_6018_tx.h b/hal/wifi3.0/qca6018/hal_6018_tx.h deleted file mode 100644 index fc915795c4e2..000000000000 --- a/hal/wifi3.0/qca6018/hal_6018_tx.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all - * copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL - * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE - * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL - * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR - * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "hal_hw_headers.h" -#include "hal_internal.h" -#include "cdp_txrx_mon_struct.h" -#include "qdf_trace.h" -#include "hal_rx.h" -#include "hal_tx.h" -#include "dp_types.h" -#include "hal_api_mon.h" - -/** - * hal_tx_desc_set_dscp_tid_table_id_6018() - Sets DSCP to TID conversion - * table ID - * @desc: Handle to Tx Descriptor - * @id: DSCP to tid conversion table to be used for this frame - * - * Return: void - */ - -static void hal_tx_desc_set_dscp_tid_table_id_6018(void *desc, uint8_t id) -{ - HAL_SET_FLD(desc, TCL_DATA_CMD_5, - DSCP_TID_TABLE_NUM) |= - HAL_TX_SM(TCL_DATA_CMD_5, - DSCP_TID_TABLE_NUM, id); -} - -#define DSCP_TID_TABLE_SIZE 24 -#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) -/** - * hal_tx_set_dscp_tid_map_6018() - Configure default DSCP to TID map table - * @soc: HAL SoC context - * @map: DSCP-TID mapping table - * @id: mapping table ID - 0,1 - * - * DSCP are mapped to 8 TID values using TID values programmed - * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0) - * and DSCP_TID2_MAP_<0 to 6> (id = 1) - * Each mapping register has TID mapping for 10 DSCP values - * - * Return: none - */ - -static void hal_tx_set_dscp_tid_map_6018(void *hal_soc, uint8_t *map, - uint8_t id) -{ - int i; - uint32_t addr, cmn_reg_addr; - uint32_t value = 0, regval; - uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; - - struct hal_soc *soc = (struct hal_soc *)hal_soc; - - if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX) - return; - - cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); - - addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, - id * NUM_WORDS_PER_DSCP_TID_TABLE); - - /* Enable read/write access */ - regval = HAL_REG_READ(soc, cmn_reg_addr); - regval |= - (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); - - HAL_REG_WRITE(soc, cmn_reg_addr, regval); - - /* Write 8 (24 bits) DSCP-TID mappings in each interation */ - for (i = 0; i < 64; i += 8) { - value = (map[i] | - (map[i + 1] << 0x3) | - (map[i + 2] << 0x6) | - (map[i + 3] << 0x9) | - (map[i + 4] << 0xc) | - (map[i + 5] << 0xf) | - (map[i + 6] << 0x12) | - (map[i + 7] << 0x15)); - - qdf_mem_copy(&val[cnt], (void *)&value, 3); - cnt += 3; - } - - for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { - regval = *(uint32_t *)(val + i); - HAL_REG_WRITE(soc, addr, - (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); - addr += 4; - } - - /* Diasble read/write access */ - regval = HAL_REG_READ(soc, cmn_reg_addr); - regval &= - ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); - - HAL_REG_WRITE(soc, cmn_reg_addr, regval); -} - -/** - * hal_tx_update_dscp_tid_6018() - Update the dscp tid map table as - updated by user - * @soc: HAL SoC context - * @map: DSCP-TID mapping table - * @id : MAP ID - * @dscp: DSCP_TID map index - * - * Return: void - */ - -static void hal_tx_update_dscp_tid_6018(void *hal_soc, uint8_t tid, - uint8_t id, uint8_t dscp) -{ - int index; - uint32_t addr; - uint32_t value; - uint32_t regval; - struct hal_soc *soc = (struct hal_soc *)hal_soc; - - addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( - SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id); - - index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER; - addr += 4 * (dscp / HAL_TX_NUM_DSCP_PER_REGISTER); - value = tid << (HAL_TX_BITS_PER_TID * index); - - regval = HAL_REG_READ(soc, addr); - regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index)); - regval |= value; - - HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); -} - -/** - * hal_tx_desc_set_lmac_id - Set the lmac_id value - * @desc: Handle to Tx Descriptor - * @lmac_id: mac Id to ast matching - * b00 – mac 0 - * b01 – mac 1 - * b10 – mac 2 - * b11 – all macs (legacy HK way) - * - * Return: void - */ - -static void hal_tx_desc_set_lmac_id_6018(void *desc, uint8_t lmac_id) -{ - HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= - HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); -} -