From 390b3f3f4b25b724a37654ad7b330d2b8c31467b Mon Sep 17 00:00:00 2001
From: Melody Olvera <molvera@quicinc.com>
Date: Mon, 29 Mar 2021 08:58:25 -0700
Subject: [PATCH] ARM: dts: msm: Add bindings for llcc tcm

Add memory region for llcc tightly coupled memory.

Change-Id: Ic553f10e26f24fc51e3c1de1c466a4f78f3c0b9b
---
 bindings/arm/msm/qcom,llcc.txt |  6 ++++++
 qcom/sdxlemur.dtsi             | 14 ++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt
index bf052f36b6de..dc9c20cfec7b 100644
--- a/bindings/arm/msm/qcom,llcc.txt
+++ b/bindings/arm/msm/qcom,llcc.txt
@@ -47,6 +47,12 @@ Properties:
 	Definition: List of clock input name strings sorted in the same
 		    order as the clocks property. Definition must have
 		    "qdss_clk"
+
+- memory-region:
+	Usage: optional
+	Value type: <prop-encoded-array>
+	Definition: List of memory regions which define the range of addresses used
+		    for tightly coupled memory in the llcc.
 Example:
 
 	cache-controller@1100000 {
diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index 931e72883b24..9b5aae70a9e0 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -76,6 +76,19 @@
 			reusable;
 			size = <0x400000>;
 		};
+
+		cnss_wlan_mem: cnss_wlan_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x00000000 0xffffffff>;
+			reusable;
+			alignment = <0x400000>;
+			size = <0x1400000>;
+		};
+
+		llcc_tcm_mem: llcc_tcm_region {
+			no-map;
+			reg = <0x15800000 0x800000>;
+		};
 	};
 
 	cpus {
@@ -704,6 +717,7 @@
 		cap-based-alloc-and-pwr-collapse;
 		clocks = <&aopcc QDSS_CLK>;
 		clock-names = "aopcc_closks";
+		memory-region = <&llcc_tcm_mem>;
 	};
 
 	smem: qcom,smem {