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pch_uart: reference clock on CM-iTC

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Default clock source for UARTs on Topcliff is external UART_CLK.
On CM-iTC USB_48MHz is used instead. After VCO2PLL and DIV
manipulations UARTs will receive 192 MHz.
Clock manipulations on Topcliff are controlled in pch_phub.c

v2: redone against the linux-next tree
v3: redone against linux/kernel/git/next/linux-next.git snapshot

Signed-off-by: Denis Turischev <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Denis Turischev 2011-03-10 15:14:00 +02:00 • committed by Greg Kroah-Hartman
commit 6ae705b23b
2 changed files with 23 additions and 2 deletions
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9
drivers/tty/serial/pch_uart.c
View file

@ -21,6 +21,7 @@
#include <linux/serial_core.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/dmi.h>
#include <linux/dmaengine.h>
#include <linux/pch_dma.h>
@ -1404,14 +1405,18 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
if (!rxbuf)
goto init_port_free_txbuf;
base_baud = 1843200; /* 1.8432MHz */
/* quirk for CM-iTC board */
if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
base_baud = 192000000; /* 192.0MHz */
switch (port_type) {
case PORT_UNKNOWN:
fifosize = 256; /* EG20T/ML7213: UART0 */
base_baud = 1843200; /* 1.8432MHz */
break;
case PORT_8250:
fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
base_baud = 1843200; /* 1.8432MHz */
break;
default:
dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);