mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
[POWERPC] qe: miscellaneous code improvements and fixes to the QE library
This patch makes numerous miscellaneous code improvements to the QE library.
1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type()
(every caller of ucc_init_guemr() also calls ucc_set_type()). Modify all
callers of ucc_set_type() accordingly.
2. Remove the unused enum ucc_pram_initial_offset.
3. Refactor qe_setbrg(), also implement work-around for errata QE_General4.
4. Several printk() calls were missing the terminating \n.
5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where
appropriate.
6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed
with the wrong value.
7. Add the protocol type to struct us_info and updated ucc_slow_init() to
use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED.
8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx()
9. Add several macros in qe.h (mostly for slow UCC support, but also to
standardize some naming convention) and remove several unused macros.
10. Update ucc_geth.c to use the new macros.
11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol
to use when initializing the UCC in ucc_slow_init().
12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since
these are the real names of the registers.
13. Use the setbits, clrbits, and clrsetbits where appropriate.
14. Refactor ucc_set_qe_mux_rxtx().
15. Remove all instances of 'volatile'.
16. Simplify get_cmxucr_reg();
17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[].
18. Updated struct ucc_geth because struct ucc_fast is not padded any more.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
This commit is contained in:
Timur Tabi
Kumar Gala
parent
6039680705
commit
6b0b594bb8
12 changed files with 431 additions and 412 deletions
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@ -97,10 +97,7 @@ struct qe_mux {
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__be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
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__be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
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__be32 cmxsi1syr; /* CMX SI1 SYNC route register */
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__be32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
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__be32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
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__be32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
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__be32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
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__be32 cmxucr[4]; /* CMX UCCx clock route registers */
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__be32 cmxupcr; /* CMX UPC clock route register */
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u8 res0[0x1C];
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} __attribute__ ((packed));
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@ -261,7 +258,6 @@ struct ucc_slow {
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__be16 utpt;
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u8 res4[0x52];
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u8 guemr; /* UCC general extended mode register */
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u8 res5[0x200 - 0x091];
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} __attribute__ ((packed));
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/* QE UCC Fast */
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@ -294,21 +290,13 @@ struct ucc_fast {
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__be32 urtry; /* UCC retry counter register */
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u8 res8[0x4C];
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u8 guemr; /* UCC general extended mode register */
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u8 res9[0x100 - 0x091];
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} __attribute__ ((packed));
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/* QE UCC */
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struct ucc_common {
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u8 res1[0x90];
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u8 guemr;
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u8 res2[0x200 - 0x091];
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} __attribute__ ((packed));
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struct ucc {
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union {
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struct ucc_slow slow;
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struct ucc_fast fast;
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struct ucc_common common;
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u8 res[0x200]; /* UCC blocks are 512 bytes each */
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};
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} __attribute__ ((packed));
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@ -407,7 +395,7 @@ struct dbg {
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/* RISC Special Registers (Trap and Breakpoint) */
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struct rsp {
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u8 fixme[0x100];
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u32 reg[0x40]; /* 64 32-bit registers */
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} __attribute__ ((packed));
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struct qe_immap {
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@ -436,11 +424,13 @@ struct qe_immap {
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u8 res13[0x600];
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struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
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struct sdma sdma; /* SDMA */
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struct dbg dbg; /* Debug Space */
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struct rsp rsp[0x2]; /* RISC Special Registers
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struct dbg dbg; /* 0x104080 - 0x1040FF
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Debug Space */
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struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
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RISC Special Registers
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(Trap and Breakpoint) */
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u8 res14[0x300];
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u8 res15[0x3A00];
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u8 res14[0x300]; /* 0x104300 - 0x1045FF */
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u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
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u8 res16[0x8000]; /* 0x108000 - 0x110000 */
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u8 muram[0xC000]; /* 0x110000 - 0x11C000
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Multi-user RAM */
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@ -451,7 +441,7 @@ struct qe_immap {
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extern struct qe_immap *qe_immr;
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extern phys_addr_t get_qe_base(void);
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static inline unsigned long immrbar_virt_to_phys(volatile void * address)
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static inline unsigned long immrbar_virt_to_phys(void *address)
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{
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if ( ((u32)address >= (u32)qe_immr) &&
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((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
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@ -38,7 +38,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
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/* QE internal API */
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int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
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void qe_setbrg(u32 brg, u32 rate);
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void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier);
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int qe_get_snum(void);
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void qe_put_snum(u8 snum);
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unsigned long qe_muram_alloc(int size, int align);
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@ -49,14 +49,28 @@ void *qe_muram_addr(unsigned long offset);
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/* Buffer descriptors */
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struct qe_bd {
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u16 status;
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u16 length;
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u32 buf;
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__be16 status;
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__be16 length;
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__be32 buf;
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} __attribute__ ((packed));
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#define BD_STATUS_MASK 0xffff0000
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#define BD_LENGTH_MASK 0x0000ffff
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#define BD_SC_EMPTY 0x8000 /* Receive is empty */
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#define BD_SC_READY 0x8000 /* Transmit is ready */
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#define BD_SC_WRAP 0x2000 /* Last buffer descriptor */
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#define BD_SC_INTRPT 0x1000 /* Interrupt on change */
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#define BD_SC_LAST 0x0800 /* Last buffer in frame */
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#define BD_SC_CM 0x0200 /* Continous mode */
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#define BD_SC_ID 0x0100 /* Rec'd too many idles */
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#define BD_SC_P 0x0100 /* xmt preamble */
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#define BD_SC_BR 0x0020 /* Break received */
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#define BD_SC_FR 0x0010 /* Framing error */
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#define BD_SC_PR 0x0008 /* Parity error */
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#define BD_SC_OV 0x0002 /* Overrun */
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#define BD_SC_CD 0x0001 /* ?? */
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/* Alignment */
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#define QE_INTR_TABLE_ALIGN 16 /* ??? */
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#define QE_ALIGNMENT_OF_BD 8
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@ -269,15 +283,12 @@ enum qe_clock {
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/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
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#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
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#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
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#define QE_CR_PROTOCOL_QMC 0x02
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#define QE_CR_PROTOCOL_UART 0x04
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#define QE_CR_PROTOCOL_ATM_POS 0x0A
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#define QE_CR_PROTOCOL_ETHERNET 0x0C
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#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
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/* BMR byte order */
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#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
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#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
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#define QE_BMR_BYTE_ORDER_BO_MAX 0x18
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/* BRG configuration register */
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#define QE_BRGC_ENABLE 0x00010000
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#define QE_BRGC_DIVISOR_SHIFT 1
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@ -324,41 +335,41 @@ enum qe_clock {
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#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
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#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
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/* UCC */
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/* UCC GUEMR register */
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#define UCC_GUEMR_MODE_MASK_RX 0x02
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#define UCC_GUEMR_MODE_MASK_TX 0x01
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#define UCC_GUEMR_MODE_FAST_RX 0x02
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#define UCC_GUEMR_MODE_FAST_TX 0x01
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#define UCC_GUEMR_MODE_SLOW_RX 0x00
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#define UCC_GUEMR_MODE_MASK_TX 0x01
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#define UCC_GUEMR_MODE_FAST_TX 0x01
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#define UCC_GUEMR_MODE_SLOW_TX 0x00
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#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
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#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
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must be set 1 */
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/* structure representing UCC SLOW parameter RAM */
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struct ucc_slow_pram {
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u16 rbase; /* RX BD base address */
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u16 tbase; /* TX BD base address */
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u8 rfcr; /* Rx function code */
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u8 tfcr; /* Tx function code */
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u16 mrblr; /* Rx buffer length */
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u32 rstate; /* Rx internal state */
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u32 rptr; /* Rx internal data pointer */
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u16 rbptr; /* rb BD Pointer */
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u16 rcount; /* Rx internal byte count */
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u32 rtemp; /* Rx temp */
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u32 tstate; /* Tx internal state */
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u32 tptr; /* Tx internal data pointer */
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u16 tbptr; /* Tx BD pointer */
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u16 tcount; /* Tx byte count */
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u32 ttemp; /* Tx temp */
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u32 rcrc; /* temp receive CRC */
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u32 tcrc; /* temp transmit CRC */
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__be16 rbase; /* RX BD base address */
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__be16 tbase; /* TX BD base address */
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u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
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u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
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__be16 mrblr; /* Rx buffer length */
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__be32 rstate; /* Rx internal state */
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__be32 rptr; /* Rx internal data pointer */
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__be16 rbptr; /* rb BD Pointer */
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__be16 rcount; /* Rx internal byte count */
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__be32 rtemp; /* Rx temp */
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__be32 tstate; /* Tx internal state */
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__be32 tptr; /* Tx internal data pointer */
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__be16 tbptr; /* Tx BD pointer */
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__be16 tcount; /* Tx byte count */
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__be32 ttemp; /* Tx temp */
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__be32 rcrc; /* temp receive CRC */
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__be32 tcrc; /* temp transmit CRC */
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} __attribute__ ((packed));
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/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
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#define UCC_SLOW_GUMR_H_CRC16 0x00004000
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#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000
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#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
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#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
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#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
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#define UCC_SLOW_GUMR_H_REVD 0x00002000
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#define UCC_SLOW_GUMR_H_TRX 0x00001000
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#define UCC_SLOW_GUMR_H_TTX 0x00000800
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@ -378,9 +389,33 @@ struct ucc_slow_pram {
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#define UCC_SLOW_GUMR_L_TCI 0x10000000
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#define UCC_SLOW_GUMR_L_RINV 0x02000000
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#define UCC_SLOW_GUMR_L_TINV 0x01000000
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#define UCC_SLOW_GUMR_L_TEND 0x00020000
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#define UCC_SLOW_GUMR_L_TEND 0x00040000
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#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
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#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
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#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
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#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
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#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
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#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
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#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
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#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
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#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
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#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
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#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
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#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
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#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
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#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
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#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
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#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
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#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
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#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
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#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
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#define UCC_SLOW_GUMR_L_ENR 0x00000020
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#define UCC_SLOW_GUMR_L_ENT 0x00000010
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#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
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#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
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#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
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#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
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#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
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/* General UCC FAST Mode Register */
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#define UCC_FAST_GUMR_TCI 0x20000000
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@ -397,53 +432,111 @@ struct ucc_slow_pram {
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#define UCC_FAST_GUMR_ENR 0x00000020
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#define UCC_FAST_GUMR_ENT 0x00000010
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/* Slow UCC Event Register (UCCE) */
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#define UCC_SLOW_UCCE_GLR 0x1000
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#define UCC_SLOW_UCCE_GLT 0x0800
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#define UCC_SLOW_UCCE_DCC 0x0400
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#define UCC_SLOW_UCCE_FLG 0x0200
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#define UCC_SLOW_UCCE_AB 0x0200
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#define UCC_SLOW_UCCE_IDLE 0x0100
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#define UCC_SLOW_UCCE_GRA 0x0080
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#define UCC_SLOW_UCCE_TXE 0x0010
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#define UCC_SLOW_UCCE_RXF 0x0008
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#define UCC_SLOW_UCCE_CCR 0x0008
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#define UCC_SLOW_UCCE_RCH 0x0008
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#define UCC_SLOW_UCCE_BSY 0x0004
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#define UCC_SLOW_UCCE_TXB 0x0002
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#define UCC_SLOW_UCCE_TX 0x0002
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#define UCC_SLOW_UCCE_RX 0x0001
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#define UCC_SLOW_UCCE_GOV 0x0001
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#define UCC_SLOW_UCCE_GUN 0x0002
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#define UCC_SLOW_UCCE_GINT 0x0004
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#define UCC_SLOW_UCCE_IQOV 0x0008
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/* UART Slow UCC Event Register (UCCE) */
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#define UCC_UART_UCCE_AB 0x0200
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#define UCC_UART_UCCE_IDLE 0x0100
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#define UCC_UART_UCCE_GRA 0x0080
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#define UCC_UART_UCCE_BRKE 0x0040
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#define UCC_UART_UCCE_BRKS 0x0020
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#define UCC_UART_UCCE_CCR 0x0008
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#define UCC_UART_UCCE_BSY 0x0004
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#define UCC_UART_UCCE_TX 0x0002
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#define UCC_UART_UCCE_RX 0x0001
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#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
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UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \
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UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
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#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
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UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF)
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#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
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UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
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UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
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#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \
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UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
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UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
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#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \
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UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV)
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/* HDLC Slow UCC Event Register (UCCE) */
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#define UCC_HDLC_UCCE_GLR 0x1000
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#define UCC_HDLC_UCCE_GLT 0x0800
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#define UCC_HDLC_UCCE_IDLE 0x0100
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#define UCC_HDLC_UCCE_BRKE 0x0040
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#define UCC_HDLC_UCCE_BRKS 0x0020
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#define UCC_HDLC_UCCE_TXE 0x0010
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#define UCC_HDLC_UCCE_RXF 0x0008
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#define UCC_HDLC_UCCE_BSY 0x0004
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#define UCC_HDLC_UCCE_TXB 0x0002
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#define UCC_HDLC_UCCE_RXB 0x0001
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#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
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UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \
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UCC_SLOW_UCCE_GLR)
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/* BISYNC Slow UCC Event Register (UCCE) */
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#define UCC_BISYNC_UCCE_GRA 0x0080
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#define UCC_BISYNC_UCCE_TXE 0x0010
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#define UCC_BISYNC_UCCE_RCH 0x0008
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#define UCC_BISYNC_UCCE_BSY 0x0004
|
||||
#define UCC_BISYNC_UCCE_TXB 0x0002
|
||||
#define UCC_BISYNC_UCCE_RXB 0x0001
|
||||
|
||||
#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB
|
||||
#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX)
|
||||
#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX)
|
||||
/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
|
||||
#define UCC_GETH_UCCE_MPD 0x80000000
|
||||
#define UCC_GETH_UCCE_SCAR 0x40000000
|
||||
#define UCC_GETH_UCCE_GRA 0x20000000
|
||||
#define UCC_GETH_UCCE_CBPR 0x10000000
|
||||
#define UCC_GETH_UCCE_BSY 0x08000000
|
||||
#define UCC_GETH_UCCE_RXC 0x04000000
|
||||
#define UCC_GETH_UCCE_TXC 0x02000000
|
||||
#define UCC_GETH_UCCE_TXE 0x01000000
|
||||
#define UCC_GETH_UCCE_TXB7 0x00800000
|
||||
#define UCC_GETH_UCCE_TXB6 0x00400000
|
||||
#define UCC_GETH_UCCE_TXB5 0x00200000
|
||||
#define UCC_GETH_UCCE_TXB4 0x00100000
|
||||
#define UCC_GETH_UCCE_TXB3 0x00080000
|
||||
#define UCC_GETH_UCCE_TXB2 0x00040000
|
||||
#define UCC_GETH_UCCE_TXB1 0x00020000
|
||||
#define UCC_GETH_UCCE_TXB0 0x00010000
|
||||
#define UCC_GETH_UCCE_RXB7 0x00008000
|
||||
#define UCC_GETH_UCCE_RXB6 0x00004000
|
||||
#define UCC_GETH_UCCE_RXB5 0x00002000
|
||||
#define UCC_GETH_UCCE_RXB4 0x00001000
|
||||
#define UCC_GETH_UCCE_RXB3 0x00000800
|
||||
#define UCC_GETH_UCCE_RXB2 0x00000400
|
||||
#define UCC_GETH_UCCE_RXB1 0x00000200
|
||||
#define UCC_GETH_UCCE_RXB0 0x00000100
|
||||
#define UCC_GETH_UCCE_RXF7 0x00000080
|
||||
#define UCC_GETH_UCCE_RXF6 0x00000040
|
||||
#define UCC_GETH_UCCE_RXF5 0x00000020
|
||||
#define UCC_GETH_UCCE_RXF4 0x00000010
|
||||
#define UCC_GETH_UCCE_RXF3 0x00000008
|
||||
#define UCC_GETH_UCCE_RXF2 0x00000004
|
||||
#define UCC_GETH_UCCE_RXF1 0x00000002
|
||||
#define UCC_GETH_UCCE_RXF0 0x00000001
|
||||
|
||||
/* UPSMR, when used as a UART */
|
||||
#define UCC_UART_UPSMR_FLC 0x8000
|
||||
#define UCC_UART_UPSMR_SL 0x4000
|
||||
#define UCC_UART_UPSMR_CL_MASK 0x3000
|
||||
#define UCC_UART_UPSMR_CL_8 0x3000
|
||||
#define UCC_UART_UPSMR_CL_7 0x2000
|
||||
#define UCC_UART_UPSMR_CL_6 0x1000
|
||||
#define UCC_UART_UPSMR_CL_5 0x0000
|
||||
#define UCC_UART_UPSMR_UM_MASK 0x0c00
|
||||
#define UCC_UART_UPSMR_UM_NORMAL 0x0000
|
||||
#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
|
||||
#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
|
||||
#define UCC_UART_UPSMR_FRZ 0x0200
|
||||
#define UCC_UART_UPSMR_RZS 0x0100
|
||||
#define UCC_UART_UPSMR_SYN 0x0080
|
||||
#define UCC_UART_UPSMR_DRT 0x0040
|
||||
#define UCC_UART_UPSMR_PEN 0x0010
|
||||
#define UCC_UART_UPSMR_RPM_MASK 0x000c
|
||||
#define UCC_UART_UPSMR_RPM_ODD 0x0000
|
||||
#define UCC_UART_UPSMR_RPM_LOW 0x0004
|
||||
#define UCC_UART_UPSMR_RPM_EVEN 0x0008
|
||||
#define UCC_UART_UPSMR_RPM_HIGH 0x000C
|
||||
#define UCC_UART_UPSMR_TPM_MASK 0x0003
|
||||
#define UCC_UART_UPSMR_TPM_ODD 0x0000
|
||||
#define UCC_UART_UPSMR_TPM_LOW 0x0001
|
||||
#define UCC_UART_UPSMR_TPM_EVEN 0x0002
|
||||
#define UCC_UART_UPSMR_TPM_HIGH 0x0003
|
||||
|
||||
/* UCC Transmit On Demand Register (UTODR) */
|
||||
#define UCC_SLOW_TOD 0x8000
|
||||
#define UCC_FAST_TOD 0x8000
|
||||
|
||||
/* UCC Bus Mode Register masks */
|
||||
/* Not to be confused with the Bundle Mode Register */
|
||||
#define UCC_BMR_GBL 0x20
|
||||
#define UCC_BMR_BO_BE 0x10
|
||||
#define UCC_BMR_CETM 0x04
|
||||
#define UCC_BMR_DTB 0x02
|
||||
#define UCC_BMR_BDB 0x01
|
||||
|
||||
/* Function code masks */
|
||||
#define FC_GBL 0x20
|
||||
#define FC_DTB_LCL 0x02
|
||||
|
|
|
|||
|
|
@ -25,58 +25,38 @@
|
|||
/* Slow or fast type for UCCs.
|
||||
*/
|
||||
enum ucc_speed_type {
|
||||
UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
|
||||
};
|
||||
|
||||
/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
|
||||
*/
|
||||
enum ucc_pram_initial_offset {
|
||||
UCC_PRAM_OFFSET_UCC1 = 0x8400,
|
||||
UCC_PRAM_OFFSET_UCC2 = 0x8500,
|
||||
UCC_PRAM_OFFSET_UCC3 = 0x8600,
|
||||
UCC_PRAM_OFFSET_UCC4 = 0x9000,
|
||||
UCC_PRAM_OFFSET_UCC5 = 0x8000,
|
||||
UCC_PRAM_OFFSET_UCC6 = 0x8100,
|
||||
UCC_PRAM_OFFSET_UCC7 = 0x8200,
|
||||
UCC_PRAM_OFFSET_UCC8 = 0x8300
|
||||
UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
|
||||
UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
|
||||
};
|
||||
|
||||
/* ucc_set_type
|
||||
* Sets UCC to slow or fast mode.
|
||||
*
|
||||
* ucc_num - (In) number of UCC (0-7).
|
||||
* regs - (In) pointer to registers base for the UCC.
|
||||
* speed - (In) slow or fast mode for UCC.
|
||||
*/
|
||||
int ucc_set_type(int ucc_num, struct ucc_common *regs,
|
||||
enum ucc_speed_type speed);
|
||||
int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
|
||||
|
||||
/* ucc_init_guemr
|
||||
* Init the Guemr register.
|
||||
*
|
||||
* regs - (In) pointer to registers base for the UCC.
|
||||
*/
|
||||
int ucc_init_guemr(struct ucc_common *regs);
|
||||
int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
|
||||
|
||||
int ucc_set_qe_mux_mii_mng(int ucc_num);
|
||||
int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
|
||||
enum comm_dir mode);
|
||||
|
||||
int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode);
|
||||
|
||||
int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask);
|
||||
int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
|
||||
|
||||
/* QE MUX clock routing for UCC
|
||||
*/
|
||||
static inline int ucc_set_qe_mux_grant(int ucc_num, int set)
|
||||
static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
|
||||
{
|
||||
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
|
||||
}
|
||||
|
||||
static inline int ucc_set_qe_mux_tsa(int ucc_num, int set)
|
||||
static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
|
||||
{
|
||||
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
|
||||
}
|
||||
|
||||
static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set)
|
||||
static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
|
||||
{
|
||||
return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -148,9 +148,10 @@ enum ucc_slow_diag_mode {
|
|||
|
||||
struct ucc_slow_info {
|
||||
int ucc_num;
|
||||
int protocol; /* QE_CR_PROTOCOL_xxx */
|
||||
enum qe_clock rx_clock;
|
||||
enum qe_clock tx_clock;
|
||||
u32 regs;
|
||||
phys_addr_t regs;
|
||||
int irq;
|
||||
u16 uccm_mask;
|
||||
int data_mem_part;
|
||||
|
|
@ -186,7 +187,7 @@ struct ucc_slow_info {
|
|||
|
||||
struct ucc_slow_private {
|
||||
struct ucc_slow_info *us_info;
|
||||
struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs */
|
||||
struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
|
||||
struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
|
||||
u32 us_pram_offset;
|
||||
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
|
||||
|
|
@ -277,12 +278,12 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
|
|||
*/
|
||||
void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
|
||||
|
||||
/* ucc_slow_restart_x
|
||||
/* ucc_slow_restart_tx
|
||||
* Restarts transmitting on a specified slow UCC.
|
||||
*
|
||||
* uccs - (In) pointer to the slow UCC structure.
|
||||
*/
|
||||
void ucc_slow_restart_x(struct ucc_slow_private * uccs);
|
||||
void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
|
||||
|
||||
u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue