mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge tag 'drm-for-v4.9' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "Core: - Fence destaging work - DRIVER_LEGACY to split off legacy drm drivers - drm_mm refactoring - Splitting drm_crtc.c into chunks and documenting better - Display info fixes - rbtree support for prime buffer lookup - Simple VGA DAC driver Panel: - Add Nexus 7 panel - More simple panels i915: - Refactoring GEM naming - Refactored vma/active tracking - Lockless request lookups - Better stolen memory support - FBC fixes - SKL watermark fixes - VGPU improvements - dma-buf fencing support - Better DP dongle support amdgpu: - Powerplay for Iceland asics - Improved GPU reset support - UVD/VEC powergating support for CZ/ST - Preinitialised VRAM buffer support - Virtual display support - Initial SI support - GTT rework - PCI shutdown callback support - HPD IRQ storm fixes amdkfd: - bugfixes tilcdc: - Atomic modesetting support mediatek: - AAL + GAMMA engine support - Hook up gamma LUT - Temporal dithering support imx: - Pixel clock from devicetree - drm bridge support for LVDS bridges - active plane reconfiguration - VDIC deinterlacer support - Frame synchronisation unit support - Color space conversion support analogix: - PSR support - Better panel on/off support rockchip: - rk3399 vop/crtc support - PSR support vc4: - Interlaced vblank timing - 3D rendering CPU overhead reduction - HDMI output fixes tda998x: - HDMI audio ASoC support sunxi: - Allwinner A33 support - better TCON support msm: - DT binding cleanups - Explicit fence-fd support sti: - remove sti415/416 support etnaviv: - MMUv2 refactoring - GC3000 support exynos: - Refactoring HDMI DCC/PHY - G2D pm regression fix - Page fault issues with wait for vblank There is no nouveau work in this tree, as Ben didn't get a pull request in, and he was fighting moving to atomic and adding mst support, so maybe best it waits for a cycle" * tag 'drm-for-v4.9' of git://people.freedesktop.org/~airlied/linux: (1412 commits) drm/crtc: constify drm_crtc_index parameter drm/i915: Fix conflict resolution from backmerge of v4.8-rc8 to drm-next drm/i915/guc: Unwind GuC workqueue reservation if request construction fails drm/i915: Reset the breadcrumbs IRQ more carefully drm/i915: Force relocations via cpu if we run out of idle aperture drm/i915: Distinguish last emitted request from last submitted request drm/i915: Allow DP to work w/o EDID drm/i915: Move long hpd handling into the hotplug work drm/i915/execlists: Reinitialise context image after GPU hang drm/i915: Use correct index for backtracking HUNG semaphores drm/i915: Unalias obj->phys_handle and obj->userptr drm/i915: Just clear the mmiodebug before a register access drm/i915/gen9: only add the planes actually affected by ddb changes drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED drm/i915/bxt: Fix HDMI DPLL configuration drm/i915/gen9: fix the watermark res_blocks value drm/i915/gen9: fix plane_blocks_per_line on watermarks calculations drm/i915/gen9: minimum scanlines for Y tile is not always 4 drm/i915/gen9: fix the WaWmMemoryReadLatency implementation drm/i915/kbl: KBL also needs to run the SAGV code ...
This commit is contained in:
Linus Torvalds
commit
6b25e21fa6
682 changed files with 85635 additions and 54725 deletions
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@ -0,0 +1,48 @@
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Dumb RGB to VGA DAC bridge
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---------------------------
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This binding is aimed for dumb RGB to VGA DAC based bridges that do not require
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any configuration.
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Required properties:
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- compatible: Must be "dumb-vga-dac"
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Required nodes:
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This device has two video ports. Their connections are modelled using the OF
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graph bindings specified in Documentation/devicetree/bindings/graph.txt.
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- Video port 0 for RGB input
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- Video port 1 for VGA output
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Example
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-------
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bridge {
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compatible = "dumb-vga-dac";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vga_bridge_in: endpoint {
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remote-endpoint = <&tcon0_out_vga>;
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};
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};
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port@1 {
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reg = <1>;
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vga_bridge_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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};
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};
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@ -21,8 +21,19 @@ Optional properties:
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- video-ports: 24 bits value which defines how the video controller
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output is wired to the TDA998x input - default: <0x230145>
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- audio-ports: array of 8-bit values, 2 values per one DAI[1].
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The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S[2].
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The second value defines the tda998x AP_ENA reg content when the DAI
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in question is used. The implementation allows one or two DAIs. If two
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DAIs are defined, they must be of different type.
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[1] Documentation/sound/alsa/soc/DAI.txt
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[2] include/dt-bindings/display/tda998x.h
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Example:
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#include <dt-bindings/display/tda998x.h>
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tda998x: hdmi-encoder {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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@ -30,4 +41,11 @@ Example:
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interrupts = <27 2>; /* falling edge */
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pinctrl-0 = <&pmx_camera>;
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pinctrl-names = "default";
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video-ports = <0x230145>;
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#sound-dai-cells = <2>;
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/* DAI-format AP_ENA reg value */
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audio-ports = < TDA998x_SPDIF 0x04
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TDA998x_I2S 0x03>;
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};
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@ -14,17 +14,16 @@ Required properties:
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See ../clocks/clock-bindings.txt for details.
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- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
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- qcom,hdmi-tx-ddc-data-gpio: ddc data pin
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- qcom,hdmi-tx-hpd-gpio: hpd pin
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- core-vdda-supply: phandle to supply regulator
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- hdmi-mux-supply: phandle to mux regulator
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- phys: the phandle for the HDMI PHY device
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- phy-names: the name of the corresponding PHY device
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Optional properties:
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- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
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- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
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- hpd-gpios: hpd pin
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- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
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- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
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- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
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- power-domains: reference to the power domain(s), if available.
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- pinctrl-names: the pin control state names; should contain "default"
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- pinctrl-0: the default pinctrl state (active)
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@ -0,0 +1,7 @@
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Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel
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Required properties:
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- compatible: should be "innolux,g101ice-l01"
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@ -0,0 +1,31 @@
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JDI model LT070ME05000 1200x1920 7" DSI Panel
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Required properties:
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- compatible: should be "jdi,lt070me05000"
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- vddp-supply: phandle of the regulator that provides the supply voltage
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Power IC supply (3-5V)
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- iovcc-supply: phandle of the regulator that provides the supply voltage
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IOVCC , power supply for LCM (1.8V)
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- enable-gpios: phandle of gpio for enable line
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LED_EN, LED backlight enable, High active
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- reset-gpios: phandle of gpio for reset line
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This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
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XRES, Reset, Low active
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- dcdc-en-gpios: phandle of the gpio for power ic line
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Power IC supply enable, High active
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Example:
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dsi0: qcom,mdss_dsi@4700000 {
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panel@0 {
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compatible = "jdi,lt070me05000";
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reg = <0>;
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vddp-supply = <&pm8921_l17>;
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iovcc-supply = <&pm8921_lvs7>;
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enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
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dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
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};
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};
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@ -6,8 +6,10 @@ buffer to an external LCD interface.
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Required properties:
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- compatible: value should be one of the following
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"rockchip,rk3288-vop";
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"rockchip,rk3036-vop";
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"rockchip,rk3288-vop";
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"rockchip,rk3399-vop-big";
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"rockchip,rk3399-vop-lit";
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- interrupts: should contain a list of all VOP IP block interrupts in the
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order: VSYNC, LCD_SYSTEM. The interrupt specifier
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@ -26,13 +26,14 @@ TCON
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The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
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Required properties:
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- compatible: value should be "allwinner,sun5i-a13-tcon".
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- compatible: value must be either:
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* allwinner,sun5i-a13-tcon
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* allwinner,sun8i-a33-tcon
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the TCON. Three are needed:
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- 'ahb': the interface clocks
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- 'tcon-ch0': The clock driving the TCON channel 0
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- 'tcon-ch1': The clock driving the TCON channel 1
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- resets: phandles to the reset controllers driving the encoder
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- "lcd": the reset line for the TCON channel 0
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@ -49,6 +50,33 @@ Required properties:
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second the block connected to the TCON channel 1 (usually the TV
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encoder)
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On the A13, there is one more clock required:
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- 'tcon-ch1': The clock driving the TCON channel 1
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DRC
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---
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The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
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(A31, A23, A33), allows to dynamically adjust pixel
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brightness/contrast based on histogram measurements for LCD content
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adaptive backlight control.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun8i-a33-drc
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the DRC
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* ahb: the DRC interface clock
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* mod: the DRC module clock
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* ram: the DRC DRAM clock
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- clock-names: the clock names mentioned above
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- resets: phandles to the reset line driving the DRC
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the outputs
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Display Engine Backend
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----------------------
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@ -59,6 +87,7 @@ system.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a13-display-backend
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* allwinner,sun8i-a33-display-backend
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- reg: base address and size of the memory-mapped region.
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- clocks: phandles to the clocks feeding the frontend and backend
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* ahb: the backend interface clock
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@ -71,6 +100,14 @@ Required properties:
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the output
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On the A33, some additional properties are required:
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- reg needs to have an additional region corresponding to the SAT
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- reg-names need to be set, with "be" and "sat"
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- clocks and clock-names need to have a phandle to the SAT bus
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clocks, whose name will be "sat"
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- resets and reset-names need to have a phandle to the SAT bus
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resets, whose name will be "sat"
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Display Engine Frontend
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-----------------------
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@ -80,6 +117,7 @@ deinterlacing and color space conversion.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a13-display-frontend
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* allwinner,sun8i-a33-display-frontend
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the frontend and backend
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@ -104,6 +142,7 @@ extra node.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a13-display-engine
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* allwinner,sun8i-a33-display-engine
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- allwinner,pipelines: list of phandle to the display engine
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frontends available.
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@ -17,6 +17,18 @@ Optional properties:
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the lcd controller.
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- max-pixelclock: The maximum pixel clock that can be supported
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by the lcd controller in KHz.
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- blue-and-red-wiring: Recognized values "straight" or "crossed".
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This property deals with the LCDC revision 2 (found on AM335x)
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color errata [1].
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- "straight" indicates normal wiring that supports RGB565,
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BGR888, and XBGR8888 color formats.
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- "crossed" indicates wiring that has blue and red wires
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crossed. This setup supports BGR565, RGB888 and XRGB8888
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formats.
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- If the property is not present or its value is not recognized
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the legacy mode is assumed. This configuration supports RGB565,
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RGB888 and XRGB8888 formats. However, depending on wiring, the red
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and blue colors are swapped in either 16 or 24-bit color modes.
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Optional nodes:
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@ -24,6 +36,18 @@ Optional nodes:
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binding follows Documentation/devicetree/bindings/graph.txt and
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suppors a single port with a single endpoint.
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- See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and
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Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting
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tfp410 DVI encoder or lcd panel to lcdc
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[1] There is an errata about AM335x color wiring. For 16-bit color mode
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the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]),
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but for 24 bit color modes the wiring of blue and red components is
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crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
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for Blue[3-7]. For more details see section 3.1.1 in AM335x
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Silicon Errata:
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http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
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Example:
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fb: fb@4830e000 {
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@ -33,6 +57,8 @@ Example:
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interrupts = <36>;
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ti,hwmods = "lcdc";
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blue-and-red-wiring = "crossed";
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port {
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lcdc_0: endpoint@0 {
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remote-endpoint = <&hdmi_0>;
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