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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
Merge "firmware: qcom_scm: Merge legacy and SMCCC conventions"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
6b47d58c25
1 changed files with 315 additions and 8 deletions
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@ -71,6 +71,83 @@ static DEFINE_MUTEX(qcom_scm_lock);
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#define SMCCC_FIRST_REG_IDX 2
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#define SMCCC_LAST_REG_IDX (SMCCC_FIRST_REG_IDX + SMCCC_N_REG_ARGS - 1)
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#define LEGACY_FUNCNUM(s, c) (((s) << 10) | ((c) & 0x3ff))
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/**
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* struct legacy_command - one SCM command buffer
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* @len: total available memory for command and response
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* @buf_offset: start of command buffer
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* @resp_hdr_offset: start of response buffer
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* @id: command to be executed
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* @buf: buffer returned from legacy_get_command_buffer()
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*
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* An SCM command is laid out in memory as follows:
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*
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* ------------------- <--- struct legacy_command
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* | command header |
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* ------------------- <--- legacy_get_command_buffer()
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* | command buffer |
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* ------------------- <--- struct legacy_response and
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* | response header | legacy_command_to_response()
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* ------------------- <--- legacy_get_response_buffer()
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* | response buffer |
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* -------------------
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*
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* There can be arbitrary padding between the headers and buffers so
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* you should always use the appropriate qcom_scm_get_*_buffer() routines
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* to access the buffers in a safe manner.
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*/
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struct legacy_command {
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__le32 len;
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__le32 buf_offset;
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__le32 resp_hdr_offset;
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__le32 id;
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__le32 buf[0];
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};
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/**
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* struct legacy_response - one SCM response buffer
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* @len: total available memory for response
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* @buf_offset: start of response data relative to start of legacy_response
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* @is_complete: indicates if the command has finished processing
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*/
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struct legacy_response {
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__le32 len;
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__le32 buf_offset;
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__le32 is_complete;
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};
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#define LEGACY_ATOMIC_N_REG_ARGS 5
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#define LEGACY_ATOMIC_FIRST_REG_IDX 2
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#define LEGACY_CLASS_REGISTER (0x2 << 8)
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#define LEGACY_MASK_IRQS BIT(5)
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#define LEGACY_ATOMIC(svc, cmd, n) ((LEGACY_FUNCNUM(svc, cmd) << 12) | \
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LEGACY_CLASS_REGISTER | \
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LEGACY_MASK_IRQS | \
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(n & 0xf))
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#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
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#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
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#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
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#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
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#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
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#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
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#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
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#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
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struct qcom_scm_entry {
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int flag;
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void *entry;
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};
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static struct qcom_scm_entry qcom_scm_wb[] = {
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
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};
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static void __qcom_scm_call_do_quirk(const struct arm_smccc_args *smc,
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struct arm_smccc_res *res)
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{
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@ -90,7 +167,7 @@ static void __qcom_scm_call_do_quirk(const struct arm_smccc_args *smc,
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} while (res->a0 == QCOM_SCM_INTERRUPTED);
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}
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static int ___qcom_scm_call_smccc(struct device *dev,
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static int qcom_scm_call_smccc(struct device *dev,
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struct qcom_scm_desc *desc, bool atomic)
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{
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int arglen = desc->arginfo & 0xf;
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@ -176,6 +253,169 @@ static int ___qcom_scm_call_smccc(struct device *dev,
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return res.a0 ? qcom_scm_remap_error(res.a0) : 0;
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}
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/**
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* legacy_command_to_response() - Get a pointer to a legacy_response
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* @cmd: command
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*
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* Returns a pointer to a response for a command.
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*/
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static inline struct legacy_response *legacy_command_to_response(
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const struct legacy_command *cmd)
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{
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return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
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}
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/**
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* legacy_get_command_buffer() - Get a pointer to a command buffer
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* @cmd: command
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*
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* Returns a pointer to the command buffer of a command.
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*/
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static inline void *legacy_get_command_buffer(const struct legacy_command *cmd)
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{
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return (void *)cmd->buf;
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}
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/**
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* legacy_get_response_buffer() - Get a pointer to a response buffer
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* @rsp: response
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*
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* Returns a pointer to a response buffer of a response.
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*/
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static inline void *legacy_get_response_buffer(
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const struct legacy_response *rsp)
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{
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return (void *)rsp + le32_to_cpu(rsp->buf_offset);
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}
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static void __qcom_scm_call_do(const struct arm_smccc_args *smc,
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struct arm_smccc_res *res)
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{
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do {
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arm_smccc_smc(smc->a[0], smc->a[1], smc->a[2], smc->a[3],
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smc->a[4], smc->a[5], smc->a[6], smc->a[7], res);
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} while (res->a0 == QCOM_SCM_INTERRUPTED);
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}
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/**
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* qcom_scm_call_legacy() - Send an SCM command
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* @dev: struct device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @cmd_buf: command buffer
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* @cmd_len: length of the command buffer
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* @resp_buf: response buffer
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* @resp_len: length of the response buffer
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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*
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* A note on cache maintenance:
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* Note that any buffers that are expected to be accessed by the secure world
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* must be flushed before invoking qcom_scm_call and invalidated in the cache
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* immediately after qcom_scm_call returns. Cache maintenance on the command
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* and response buffers is taken care of by qcom_scm_call; however, callers are
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* responsible for any other cached buffers passed over to the secure world.
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*/
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static int qcom_scm_call_legacy(struct device *dev, struct qcom_scm_desc *desc)
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{
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int arglen = desc->arginfo & 0xf;
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int ret = 0, context_id;
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size_t i;
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struct legacy_command *cmd;
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struct legacy_response *rsp;
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struct arm_smccc_args smc = {{0}};
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struct arm_smccc_res res;
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const size_t cmd_len = arglen * sizeof(__le32);
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const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32);
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size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
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dma_addr_t cmd_phys;
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__le32 *arg_buf;
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__le32 *res_buf;
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cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
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cmd->len = cpu_to_le32(alloc_len);
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cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
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cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
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cmd->id = cpu_to_le32(LEGACY_FUNCNUM(desc->svc, desc->cmd));
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arg_buf = legacy_get_command_buffer(cmd);
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for (i = 0; i < arglen; i++)
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arg_buf[i] = cpu_to_le32(desc->args[i]);
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rsp = legacy_command_to_response(cmd);
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cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, cmd_phys)) {
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kfree(cmd);
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return -ENOMEM;
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}
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smc.a[0] = 1;
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smc.a[1] = (unsigned long)&context_id;
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smc.a[2] = cmd_phys;
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mutex_lock(&qcom_scm_lock);
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__qcom_scm_call_do(&smc, &res);
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if (res.a0 < 0)
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ret = qcom_scm_remap_error(res.a0);
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mutex_unlock(&qcom_scm_lock);
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if (ret)
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goto out;
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do {
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dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
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sizeof(*rsp), DMA_FROM_DEVICE);
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} while (!rsp->is_complete);
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dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
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le32_to_cpu(rsp->buf_offset),
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resp_len, DMA_FROM_DEVICE);
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res_buf = legacy_get_response_buffer(rsp);
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for (i = 0; i < MAX_QCOM_SCM_RETS; i++)
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desc->res[i] = le32_to_cpu(res_buf[i]);
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out:
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dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
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kfree(cmd);
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return ret;
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}
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/**
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* qcom_scm_call_atomic_legacy() - Send an atomic SCM command with up to
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* 5 arguments and 3 return values
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*
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* This shall only be used with commands that are guaranteed to be
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* uninterruptable, atomic and SMP safe.
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*/
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static int qcom_scm_call_atomic_legacy(struct device *dev,
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struct qcom_scm_desc *desc)
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{
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int context_id;
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struct arm_smccc_args smc = {{0}};
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struct arm_smccc_res res;
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size_t i, arglen = desc->arginfo & 0xf;
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BUG_ON(arglen > LEGACY_ATOMIC_N_REG_ARGS);
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smc.a[0] = LEGACY_ATOMIC(desc->svc, desc->cmd, arglen);
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smc.a[1] = (unsigned long)&context_id;
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for (i = 0; i < arglen; i++)
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smc.a[i + LEGACY_ATOMIC_FIRST_REG_IDX] = desc->args[i];
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arm_smccc_smc(smc.a[0], smc.a[1], smc.a[2], smc.a[3],
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smc.a[4], smc.a[5], smc.a[6], smc.a[7], &res);
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desc->res[0] = res.a1;
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desc->res[1] = res.a2;
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desc->res[2] = res.a3;
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return res.a0;
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}
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/**
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* qcom_scm_call() - Invoke a syscall in the secure world
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* @dev: device
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@ -189,7 +429,7 @@ static int ___qcom_scm_call_smccc(struct device *dev,
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static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc)
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{
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might_sleep();
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return ___qcom_scm_call_smccc(dev, desc, false);
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return qcom_scm_call_smccc(dev, desc, false);
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}
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/**
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@ -205,7 +445,7 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc)
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*/
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static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc)
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{
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return ___qcom_scm_call_smccc(dev, desc, true);
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return qcom_scm_call_smccc(dev, desc, true);
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}
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/**
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@ -219,7 +459,35 @@ static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc)
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int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
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const cpumask_t *cpus)
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{
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return -ENOTSUPP;
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int flags = 0;
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int cpu;
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int scm_cb_flags[] = {
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QCOM_SCM_FLAG_COLDBOOT_CPU0,
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QCOM_SCM_FLAG_COLDBOOT_CPU1,
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QCOM_SCM_FLAG_COLDBOOT_CPU2,
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QCOM_SCM_FLAG_COLDBOOT_CPU3,
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};
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_ADDR,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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if (!cpus || (cpus && cpumask_empty(cpus)))
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return -EINVAL;
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for_each_cpu(cpu, cpus) {
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if (cpu < ARRAY_SIZE(scm_cb_flags))
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flags |= scm_cb_flags[cpu];
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else
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set_cpu_present(cpu, false);
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}
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desc.args[0] = flags;
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desc.args[1] = virt_to_phys(entry);
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call_atomic(dev, &desc);
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}
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/**
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@ -234,7 +502,37 @@ int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
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int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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const cpumask_t *cpus)
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{
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return -ENOTSUPP;
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int ret;
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int flags = 0;
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int cpu;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_ADDR,
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};
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/*
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* Reassign only if we are switching from hotplug entry point
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* to cpuidle entry point or vice versa.
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*/
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for_each_cpu(cpu, cpus) {
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if (entry == qcom_scm_wb[cpu].entry)
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continue;
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flags |= qcom_scm_wb[cpu].flag;
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}
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/* No change in entry function */
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if (!flags)
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return 0;
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desc.args[0] = virt_to_phys(entry);
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desc.args[1] = flags;
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ret = qcom_scm_call(dev, &desc);
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if (!ret) {
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for_each_cpu(cpu, cpus)
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qcom_scm_wb[cpu].entry = entry;
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}
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return ret;
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}
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/**
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@ -247,6 +545,15 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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*/
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void __qcom_scm_cpu_power_down(struct device *dev, u32 flags)
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{
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_TERMINATE_PC,
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.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
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.arginfo = QCOM_SCM_ARGS(1),
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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qcom_scm_call_atomic(dev, &desc);
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}
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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@ -279,7 +586,7 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, &desc);
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return qcom_scm_call_atomic(dev, &desc);
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}
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bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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@ -403,7 +710,7 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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desc.args[0] = addr;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc);
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ret = qcom_scm_call_atomic(dev, &desc);
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if (ret >= 0)
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*val = desc.res[0];
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@ -422,7 +729,7 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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desc.args[1] = val;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, &desc);
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return qcom_scm_call_atomic(dev, &desc);
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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