mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 13:49:24 -04:00
Merge "pci: msm: Enable support for PCI Express ASPM control driver"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
6b5ddba4b3
1 changed files with 146 additions and 84 deletions
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@ -59,10 +59,13 @@
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#define PCIE_GEN3_EQ_FMDC_T_MIN_PHASE23_MASK (0x1f)
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#define PCIE_GEN3_MISC_CONTROL (0x08bc)
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#define DBI_RO_WR_EN (BIT(0))
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#define PCIE_PL_16GT_CAP (0x168)
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#define PCIE20_PARF_SYS_CTRL (0x00)
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#define CORE_CLK_2AUX_CLK_MUX_DIS (BIT(3))
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#define PCIE20_PARF_PM_CTRL (0x20)
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#define PCIE20_PARF_PM_STTS (0x24)
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#define PCIE20_PARF_PHY_CTRL (0x40)
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@ -103,6 +106,10 @@
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#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
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#define PCIE_CAP_DLL_ACTIVE BIT(29)
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#define PCIE20_CAP_LINKCAP (PCIE20_CAP + 0xc)
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#define PCIE_CAP_ASPM_L0S (BIT(10))
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#define PCIE_CAP_ASPM_L1 (BIT(11))
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#define PCIE20_COMMAND_STATUS (0x04)
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#define PCIE20_HEADER_TYPE (0x0c)
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#define PCIE20_BRIDGE_CTRL (0x3c)
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@ -793,6 +800,8 @@ struct msm_pcie_dev_t {
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bool l1_2_aspm_supported;
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uint32_t l1_2_th_scale;
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uint32_t l1_2_th_value;
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uint32_t t_pwr_on_val;
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uint32_t t_pwr_on_scale;
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bool common_clk_en;
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bool clk_power_manage_en;
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bool aux_clk_sync;
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@ -1287,7 +1296,7 @@ static void msm_pcie_config_l1ss_enable_all(struct msm_pcie_dev_t *dev);
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static void msm_pcie_check_l1ss_support_all(struct msm_pcie_dev_t *dev);
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static void msm_pcie_config_link_pm(struct msm_pcie_dev_t *dev, bool enable);
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static void msm_pcie_config_aspm(struct msm_pcie_dev_t *dev);
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static u32 msm_pcie_reg_copy(struct msm_pcie_dev_t *pcie_dev,
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u8 *buf, u32 size, void __iomem *base,
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@ -1665,6 +1674,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
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dev->l1_2_th_scale);
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PCIE_DBG_FS(dev, "l1_2_th_value is %d\n",
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dev->l1_2_th_value);
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PCIE_DBG_FS(dev, "t_pwr_on_scale is %u\n", dev->t_pwr_on_scale);
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PCIE_DBG_FS(dev, "t_pwr_on_val is %u\n", dev->t_pwr_on_val);
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PCIE_DBG_FS(dev, "common_clk_en is %d\n",
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dev->common_clk_en);
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PCIE_DBG_FS(dev, "clk_power_manage_en is %d\n",
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@ -3653,6 +3664,126 @@ static void msm_pcie_config_controller_phy(struct msm_pcie_dev_t *pcie_dev)
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}
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}
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static u32 msm_pcie_find_ext_capability(struct msm_pcie_dev_t *pcie_dev,
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u32 cap_id)
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{
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int total;
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u32 header;
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int pos = PCI_CFG_SPACE_SIZE;
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total = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
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header = readl_relaxed(pcie_dev->dm_core + PCIE_EXT_CAP_OFFSET);
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if (!header)
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return 0;
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while (total-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap_id && pos != 0)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < PCI_CFG_SPACE_SIZE)
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break;
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header = readl_relaxed(pcie_dev->dm_core + pos);
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}
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return 0;
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}
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static void msm_pcie_config_aspm(struct msm_pcie_dev_t *pcie_dev)
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{
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u32 reg;
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u32 l1ss_cap_id_offset, l1ss_cap_offset;
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/* enable write access to RO register */
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msm_pcie_write_mask(pcie_dev->dm_core + PCIE_GEN3_MISC_CONTROL, 0,
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DBI_RO_WR_EN);
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reg = readl_relaxed(pcie_dev->dm_core + PCIE20_CAP_LINKCAP);
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reg >>= 10;
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if (pcie_dev->l0s_supported) {
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if (!(reg & PCI_EXP_LNKCTL_ASPM_L0S)) {
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PCIE_ERR(pcie_dev, "PCIe: RC%d: L0s not supported\n",
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pcie_dev->rc_idx);
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pcie_dev->l0s_supported = false;
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}
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} else {
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if (reg & PCI_EXP_LNKCTL_ASPM_L0S)
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msm_pcie_write_mask(pcie_dev->dm_core + PCIE20_CAP_LINKCAP,
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PCIE_CAP_ASPM_L0S, 0);
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}
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if (pcie_dev->l1_supported) {
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if (!(reg & PCI_EXP_LNKCTL_ASPM_L1)) {
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PCIE_ERR(pcie_dev, "PCIe: RC%d: L1 not supported\n",
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pcie_dev->rc_idx);
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pcie_dev->l1_supported = false;
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goto done;
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}
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} else {
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if (reg & PCI_EXP_LNKCTL_ASPM_L1)
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msm_pcie_write_mask(
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pcie_dev->dm_core + PCIE20_CAP_LINKCAP,
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PCIE_CAP_ASPM_L1, 0);
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}
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l1ss_cap_id_offset = msm_pcie_find_ext_capability(pcie_dev,
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PCI_EXT_CAP_ID_L1SS);
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if (!l1ss_cap_id_offset) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: L1ss capability register not found\n",
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pcie_dev->rc_idx);
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pcie_dev->l1ss_supported = false;
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goto done;
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}
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l1ss_cap_offset = l1ss_cap_id_offset + PCI_L1SS_CAP;
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reg = readl_relaxed(pcie_dev->dm_core + l1ss_cap_offset);
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if (pcie_dev->l1ss_supported) {
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if (!(reg & PCI_L1SS_CAP_PCIPM_L1_2) &&
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!(reg & PCI_L1SS_CAP_PCIPM_L1_1) &&
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!(reg & PCI_L1SS_CAP_ASPM_L1_2) &&
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!(reg & PCI_L1SS_CAP_ASPM_L1_1)) {
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PCIE_ERR(pcie_dev, "PCIe: RC%d: L1ss not supported\n",
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pcie_dev->rc_idx);
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pcie_dev->l1ss_supported = false;
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goto done;
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}
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if (pcie_dev->t_pwr_on_scale <= 0x3 &&
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pcie_dev->t_pwr_on_val <= 0x1f) {
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reg |= (pcie_dev->t_pwr_on_scale << 16) |
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pcie_dev->t_pwr_on_val << 19;
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writel_relaxed(reg,
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pcie_dev->dm_core + l1ss_cap_offset);
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}
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/* Enable AUX clk and Core clk async for L1SS */
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if (!pcie_dev->aux_clk_sync)
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msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_SYS_CTRL,
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CORE_CLK_2AUX_CLK_MUX_DIS, 0);
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} else {
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msm_pcie_write_mask(pcie_dev->dm_core + l1ss_cap_offset,
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PCI_L1SS_CTL1_PCIPM_L1_1 |
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PCI_L1SS_CTL1_PCIPM_L1_2 |
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PCI_L1SS_CTL1_ASPM_L1_1 |
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PCI_L1SS_CTL1_ASPM_L1_2, 0);
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/* Disable AUX clk and Core Clock async - L1SS disabled */
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if (!pcie_dev->aux_clk_sync)
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msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_SYS_CTRL, 0,
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CORE_CLK_2AUX_CLK_MUX_DIS);
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}
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done:
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/* disable write access to RO register */
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msm_pcie_write_mask(pcie_dev->dm_core + PCIE_GEN3_MISC_CONTROL,
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DBI_RO_WR_EN, 0);
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}
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static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
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{
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PCIE_DBG(dev, "RC%d\n", dev->rc_idx);
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@ -3705,6 +3836,8 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
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PCIE_DBG(dev, "RC's PCIE20_CAP_DEVCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->dm_core + PCIE20_CAP_DEVCTRLSTATUS));
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}
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msm_pcie_config_aspm(dev);
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}
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static int msm_pcie_get_clk(struct msm_pcie_dev_t *pcie_dev)
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@ -4611,6 +4744,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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ep_up_timeout = jiffies + usecs_to_jiffies(EP_UP_TIMEOUT_US);
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msm_pcie_config_sid(dev);
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msm_pcie_config_controller(dev);
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ret = msm_pcie_link_train(dev);
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if (ret)
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goto link_fail;
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@ -4630,9 +4766,6 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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msleep(dev->switch_latency);
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}
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msm_pcie_config_sid(dev);
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msm_pcie_config_controller(dev);
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/* check endpoint configuration space is accessible */
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while (time_before(jiffies, ep_up_timeout)) {
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if (readl_relaxed(dev->conf) != PCIE_LINK_DOWN)
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@ -4655,10 +4788,8 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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goto link_fail;
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}
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if (dev->enumerated) {
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if (dev->enumerated)
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msm_msi_config(dev_get_msi_domain(&dev->dev->dev));
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msm_pcie_config_link_pm(dev, true);
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}
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/* bring eps out of reset */
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if (dev->i2c_ctrl.client && dev->i2c_ctrl.client_i2c_reset)
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@ -4981,8 +5112,6 @@ int msm_pcie_enumerate(u32 rc_idx)
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pci_walk_bus(dev->dev->bus, msm_pcie_config_device_table, dev);
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msm_pcie_check_l1ss_support_all(dev);
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msm_pcie_config_link_pm(dev, true);
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out:
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mutex_unlock(&dev->enumerate_lock);
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@ -5546,64 +5675,6 @@ static int msm_pcie_check_l1ss_support(struct pci_dev *pdev, void *dev)
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return 0;
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}
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static int msm_pcie_config_common_clock_enable(struct pci_dev *pdev,
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void *dev)
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{
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struct msm_pcie_dev_t *pcie_dev = (struct msm_pcie_dev_t *)dev;
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PCIE_DBG(pcie_dev, "PCIe: RC%d: PCI device %02x:%02x.%01x\n",
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pcie_dev->rc_idx, pdev->bus->number, PCI_SLOT(pdev->devfn),
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PCI_FUNC(pdev->devfn));
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msm_pcie_config_clear_set_dword(pdev, pdev->pcie_cap + PCI_EXP_LNKCTL,
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0, PCI_EXP_LNKCTL_CCC);
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return 0;
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}
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static void msm_pcie_config_common_clock_enable_all(struct msm_pcie_dev_t *dev)
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{
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if (dev->common_clk_en)
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pci_walk_bus(dev->dev->bus,
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msm_pcie_config_common_clock_enable, dev);
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}
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static int msm_pcie_config_clock_power_management_enable(struct pci_dev *pdev,
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void *dev)
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{
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struct msm_pcie_dev_t *pcie_dev = (struct msm_pcie_dev_t *)dev;
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u32 val;
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/* enable only for upstream ports */
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if (pci_is_root_bus(pdev->bus))
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return 0;
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PCIE_DBG(pcie_dev, "PCIe: RC%d: PCI device %02x:%02x.%01x\n",
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pcie_dev->rc_idx, pdev->bus->number, PCI_SLOT(pdev->devfn),
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PCI_FUNC(pdev->devfn));
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pci_read_config_dword(pdev, pdev->pcie_cap + PCI_EXP_LNKCAP, &val);
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if (val & PCI_EXP_LNKCAP_CLKPM)
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msm_pcie_config_clear_set_dword(pdev,
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pdev->pcie_cap + PCI_EXP_LNKCTL, 0,
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PCI_EXP_LNKCTL_CLKREQ_EN);
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else
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: PCI device %02x:%02x.%01x does not support clock power management\n",
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pcie_dev->rc_idx, pdev->bus->number,
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PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
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return 0;
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}
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static void msm_pcie_config_clock_power_management_enable_all(
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struct msm_pcie_dev_t *dev)
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{
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if (dev->clk_power_manage_en)
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pci_walk_bus(dev->dev->bus,
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msm_pcie_config_clock_power_management_enable, dev);
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}
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static void msm_pcie_config_l0s(struct msm_pcie_dev_t *dev,
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struct pci_dev *pdev, bool enable)
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{
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@ -5854,23 +5925,6 @@ static void msm_pcie_config_l1ss_enable_all(struct msm_pcie_dev_t *dev)
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}
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}
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static void msm_pcie_config_link_pm(struct msm_pcie_dev_t *dev, bool enable)
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{
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struct pci_bus *bus = dev->dev->bus;
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if (enable) {
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msm_pcie_config_common_clock_enable_all(dev);
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msm_pcie_config_clock_power_management_enable_all(dev);
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msm_pcie_config_l1ss_enable_all(dev);
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msm_pcie_config_l1_enable_all(dev);
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msm_pcie_config_l0s_enable_all(dev);
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} else {
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msm_pcie_config_l0s_disable_all(dev, bus);
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msm_pcie_config_l1_disable_all(dev, bus);
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msm_pcie_config_l1ss_disable_all(dev, bus);
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}
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}
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static void msm_pcie_check_l1ss_support_all(struct msm_pcie_dev_t *dev)
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{
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pci_walk_bus(dev->dev->bus, msm_pcie_check_l1ss_support, dev);
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@ -6055,6 +6109,14 @@ static int msm_pcie_probe(struct platform_device *pdev)
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pcie_dev->rc_idx, pcie_dev->l1_2_th_scale,
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pcie_dev->l1_2_th_value);
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of_property_read_u32(of_node, "qcom,tpwr-on-scale",
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&pcie_dev->t_pwr_on_scale);
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of_property_read_u32(of_node, "qcom,tpwr-on-value",
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&pcie_dev->t_pwr_on_val);
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PCIE_DBG(pcie_dev, "PCIe: RC%d: t_power on scale: %u value: %u.\n",
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pcie_dev->rc_idx, pcie_dev->t_pwr_on_scale,
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pcie_dev->t_pwr_on_val);
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pcie_dev->common_clk_en = of_property_read_bool(of_node,
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"qcom,common-clk-en");
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PCIE_DBG(pcie_dev, "Common clock is %s enabled.\n",
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