From 53fae8abf28801959b239764f512970c6b943452 Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Wed, 6 May 2020 14:04:10 +0530 Subject: [PATCH] ARM: dts: msm: Add DPC and capacity-dmips-mhz for Holi Add Dynamic power co-efficient (DPC) and capacity-dmips-mhz values, which are used by energy aware scheduler for taskplacement decisions. Change-Id: I2eff5f16dde27eb4728cba5aa6b58145ca6edb11 --- qcom/holi.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index ea53d85d2508..e0cf5a4241c9 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -24,6 +24,8 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -43,6 +45,8 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -57,6 +61,8 @@ reg = <0x0 0x200>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -71,6 +77,8 @@ reg = <0x0 0x300>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -85,6 +93,8 @@ reg = <0x0 0x400>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -99,6 +109,8 @@ reg = <0x0 0x500>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -113,6 +125,8 @@ reg = <0x0 0x600>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <324>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -127,6 +141,8 @@ reg = <0x0 0x700>; enable-method = "psci"; cpu-release-addr = <0x0 0x50000000>; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <324>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache";