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Merge "ARM: dts: msm: Add scuba-iot files on 5.4"

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qctecmdr 2020-10-14 04:23:01 -07:00 • committed by Gerrit - the friendly Code Review server
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4
bindings/arm/msm/msm.txt
View file

@ -83,6 +83,9 @@ SoCs:
- SDXLEMUR
compatible = "qcom,sdxlemur"
- SCUBA
compatible = "qcom,scuba-iot"
- SDMMAGPIE
compatible = "qcom,sdmmagpie"
@ -244,3 +247,4 @@ compatible = "qcom,holi-mtp"
compatible = "qcom,holi-cdp"
compatible = "qcom,holi-qrd"
compatible = "qcom,holi-atp"
compatible = "qcom,scuba-idp"

195
bindings/pinctrl/qcom,scuba-pinctrl.yaml Normal file
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@ -0,0 +1,195 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,scuba-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SCUBA TLMM block
description: |
This binding describes the Top Level Mode Multiplexer block found in the
SCUBA platform.
properties:
compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,scuba-pinctrl"
reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
#interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
#gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
wakeup-parent:
Usage: optional
Value type: <phandle>
Definition: A phandle to the wakeup interrupt controller for the SoC.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins:
gpio0-gpio155
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values:
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
gpio
bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven high.
Not valid for sdc pins.
output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven low.
Not valid for sdc pins.
drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
examples:
- |
tlmm: pinctrl@400000 {
compatible = "qcom,scuba-pinctrl";
reg = <0x400000 0x800000>;
interrupts = <0 227 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

6
qcom/Makefile
View file

@ -75,6 +75,12 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \
lahaina-mtp-v2.1.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SCUBA) += scuba-iot-idp-overlay.dtbo
scuba-iot-idp-overlay.dtbo-base := scuba-iot.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \
holi-mtp-overlay.dtbo \

198
qcom/msm-arm-smmu-scuba.dtsi Normal file
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@ -0,0 +1,198 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
kgsl_smmu: kgsl-smmu@0x59a0000 {
status = "disabled";
compatible = "qcom,qsmmu-v500";
reg = <0x59a0000 0x10000>,
<0x59c2000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,no-dynamic-asid;
qcom,use-3-lvl-tables;
#global-interrupts = <1>;
qcom,regulator-names = "vdd";
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
qcom,actlr =
/* ALL CBs of GFX: +15 deep PF */
<0x0 0x3ff 0x30B>;
gfx_0_tbu: gfx_0_tbu@0x59c5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x59c5000 0x1000>,
<0x59c2200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
};
};
apps_smmu: apps-smmu@0xc600000 {
status = "disabled";
compatible = "qcom,qsmmu-v500";
reg = <0xc600000 0x80000>,
<0xc782000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,actlr =
/* For rt TBU +3 deep PF */
<0x400 0x3ff 0x103>,
/* For nrt TBU +3 deep PF */
<0x800 0x3ff 0x103>;
anoc_1_tbu: anoc_1_tbu@0xc785000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0xc785000 0x1000>,
<0xc782200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <2>;
};
mm_rt_tbu: mm_rt_tbu@0xc789000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0xc789000 0x1000>,
<0xc782208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
qcom,regulator-names = "vdd";
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <2>;
};
mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0xc78d000 0x1000>,
<0xc782210 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x800 0x400>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
qcom,regulator-names = "vdd";
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <2>;
};
};
kgsl_iommu_test_device {
compatible = "iommu-debug-test";
qcom,iommu-dma = "disabled";
iommus = <&kgsl_smmu 0x7 0x0>;
status = "disabled";
};
apps_iommu_test_device {
compatible = "iommu-debug-test";
qcom,iommu-dma = "disabled";
iommus = <&apps_smmu 0x1E0 0x0>;
status = "disabled";
};
apps_iommu_coherent_test_device {
compatible = "iommu-debug-test";
qcom,iommu-dma = "disabled";
iommus = <&apps_smmu 0x1E1 0x0>;
dma-coherent;
status = "disabled";
};
};

439
qcom/pm2250-rpm-regulator.dtsi Normal file
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@ -0,0 +1,439 @@
&rpm_bus {
rpm-regulator-smpa1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <1>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s1";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-smpa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <2>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-smpa3 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <3>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s3";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-smpa4 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <4>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s4";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <1>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <2>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l2";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa3 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <3>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l3";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa4 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <4>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l4";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa5 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <5>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l5 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l5";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa6 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <6>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l6 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l6";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa7 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <7>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l7 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l7";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa8 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <8>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l8 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l8";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa9 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <9>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l9 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l9";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa10 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <10>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l10 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l10";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa11 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <11>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l11 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l11";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa12 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <12>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l12 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l12";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa13 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <13>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l13 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l13";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa14 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <14>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l14 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l14";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa15 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <15>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l15 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l15";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa16 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <16>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l16 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l16";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa17 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <17>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l17 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l17";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa18 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <18>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l18 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l18";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa19 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <19>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l19 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l19";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa20 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <20>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l20 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l20";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa21 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <21>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l21 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l21";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa22 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <22>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l22 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l22";
qcom,set = <3>;
status = "disabled";
};
};
};

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#include <dt-bindings/input/input.h>
#include <dt-bindings/input/qcom,qpnp-power-on.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm2250@0 {
compatible = "qcom,spmi-pmic";
reg = <0 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
pm2250_revid: qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100 0x100>;
};
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800 0x100>;
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "kpdpwr", "resin";
qcom,pon-dbc-delay = <15625>;
qcom,kpdpwr-sw-debounce;
qcom,system-reset;
qcom,store-hard-reset-reason;
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
qcom,pull-up = <1>;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
qcom,pull-up = <1>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
pm2250_tz: qcom,temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400 0x100>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pm2250_vadc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
qcom,temperature-threshold-set = <1>;
};
pm2250_vadc: vadc@3100 {
compatible = "qcom,spmi-adc5-lite";
reg = <0x3100 0x100>;
reg-names = "adc5-usr-base";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eoc-int-en-set";
#io-channel-cells = <1>;
io-channel-ranges;
/* Channel nodes */
ref_gnd {
reg = <ADC5_REF_GND>;
label = "ref_gnd";
qcom,pre-scaling = <1 1>;
};
vref_1p25 {
reg = <ADC5_1P25VREF>;
label = "vref_1p25";
qcom,pre-scaling = <1 1>;
};
die_temp {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
qcom,pre-scaling = <1 1>;
};
vph_pwr {
reg = <ADC5_VPH_PWR>;
label = "vph_pwr";
qcom,pre-scaling = <1 3>;
};
vbat_sns {
reg = <ADC5_VBAT_SNS>;
label = "vbat_sns";
qcom,pre-scaling = <1 3>;
};
usb_in_v_div_16 {
reg = <ADC5_USB_IN_V_16>;
label = "usb_in_v_div_16";
qcom,pre-scaling = <1 16>;
};
chg_temp {
reg = <ADC5_CHG_TEMP>;
label = "chg_temp";
qcom,pre-scaling = <1 1>;
};
bat_therm {
reg = <ADC5_BAT_THERM_100K_PU>;
label = "bat_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_30k {
reg = <ADC5_BAT_THERM_30K_PU>;
label = "bat_therm_30k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_400k {
reg = <ADC5_BAT_THERM_400K_PU>;
label = "bat_therm_400k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
i_parallel {
reg = <ADC5_PARALLEL_ISENSE>;
label = "i_parallel";
qcom,pre-scaling = <1 1>;
};
bat_id {
reg = <ADC5_BAT_ID_100K_PU>;
label = "bat_id";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
pm2250_gpios: pinctrl@c000 {
compatible = "qcom,spmi-gpio";
reg = <0xc000 0xa00>;
interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
<0x0 0xc1 0 IRQ_TYPE_NONE>,
<0x0 0xc2 0 IRQ_TYPE_NONE>,
<0x0 0xc3 0 IRQ_TYPE_NONE>,
<0x0 0xc4 0 IRQ_TYPE_NONE>,
<0x0 0xc5 0 IRQ_TYPE_NONE>,
<0x0 0xc6 0 IRQ_TYPE_NONE>,
<0x0 0xc7 0 IRQ_TYPE_NONE>,
<0x0 0xc8 0 IRQ_TYPE_NONE>,
<0x0 0xc9 0 IRQ_TYPE_NONE>;
interrupt-names = "pm2250_gpio1", "pm2250_gpio2",
"pm2250_gpio3", "pm2250_gpio4",
"pm2250_gpio5", "pm2250_gpio6",
"pm2250_gpio7", "pm2250_gpio8",
"pm2250_gpio9", "pm2250_gpio10";
gpio-controller;
#gpio-cells = <2>;
};
pm2250_rtc: qcom,pm2250_rtc {
compatible = "qcom,pm8941-rtc";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
};
pm2250_qg: qpnp,qg {
compatible = "qcom,qpnp-qg-lite";
#address-cells = <1>;
#size-cells = <1>;
qcom,vbatt-cutoff-mv = <3400>;
qcom,vbatt-low-mv = <3500>;
qcom,vbatt-low-cold-mv = <3800>;
qcom,vbatt-empty-mv = <3200>;
qcom,vbatt-empty-cold-mv = <3000>;
qcom,s3-entry-fifo-length = <2>;
qcom,pmic-revid = <&pm2250_revid>;
io-channels = <&pm2250_vadc ADC5_BAT_THERM_100K_PU>,
<&pm2250_vadc ADC5_BAT_ID_100K_PU>;
io-channel-names = "batt-therm", "batt-id";
qcom,qgauge@4800 {
status = "okay";
reg = <0x4800 0x100>;
interrupts =
<0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>,
<0x0 0x48 0x5 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "qg-vbat-empty",
"qg-fifo-done",
"qg-good-ocv";
};
qcom,qg-sdam@b600 {
status = "okay";
reg = <0xb600 0x100>;
};
};
pm2250_charger: qcom,qpnp-smblite {
compatible = "qcom,qpnp-smblite";
#address-cells = <1>;
#size-cells = <1>;
#cooling-cells = <2>;
qcom,pmic-revid = <&pm2250_revid>;
qcom,chgr@1000 {
reg = <0x1000 0x100>;
interrupts =
<0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "chgr-error",
"chg-state-change",
"buck-oc",
"vph-ov";
};
qcom,dcdc@1100 {
reg = <0x1100 0x100>;
interrupts =
<0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "otg-fail",
"otg-fault",
"skip-mode",
"input-current-limiting",
"switcher-power-ok";
};
qcom,batif@1200 {
reg = <0x1200 0x100>;
interrupts =
<0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "bat-temp",
"bat-therm-or-id-missing",
"bat-low",
"bat-ov",
"bsm-active";
};
qcom,usb@1300 {
reg = <0x1300 0x100>;
interrupts =
<0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usbin-plugin",
"usbin-collapse",
"usbin-uv",
"usbin-ov",
"usbin-gtvt",
"usbin-icl-change";
};
qcom,typec@1500 {
reg = <0x1500 0x100>;
interrupts =
<0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "typec-or-rid-detect-change",
"typec-vpd-detect",
"typec-cc-state-change",
"typec-vbus-change",
"typec-attach-detach",
"typec-legacy-cable-detect",
"typec-try-snk-src-detect";
};
qcom,misc@1600 {
reg = <0x1600 0x100>;
interrupts =
<0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "wdog-snarl",
"wdog-bark",
"aicl-fail",
"aicl-done",
"imp-trigger",
"all-chnl-cond-done",
"temp-change";
};
qcom,schgm-flashlite@a600 {
reg = <0xa600 0x100>;
interrupts =
<0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0xa6 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "flash-state-change",
"ilim1-s1",
"ilim2-s2",
"vreg-ok";
};
};
};
pm2250_1: qcom,pm2250@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
pm2250_vib: qcom,vibrator@5600 {
compatible = "qcom,qpnp-vibrator-ldo";
reg = <0x5600 0x100>;
qcom,vib-ldo-volt-uv = <3000000>;
qcom,disable-overdrive;
};
pm2250_pwm1: qcom,pwms@bc00 {
compatible = "qcom,pwm-lpg";
reg = <0xbc00 0x100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
pm2250_pwm2: qcom,pwms@bd00 {
compatible = "qcom,pwm-lpg";
reg = <0xbd00 0x100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
pm2250_pwm3: qcom,pwms@be00 {
compatible = "qcom,pwm-lpg";
reg = <0xbe00 0x100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
};
};

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&soc {
qcom,ion {
compatible = "qcom,msm-ion";
#address-cells = <1>;
#size-cells = <0>;
system_heap: qcom,ion-heap@25 {
reg = <25>;
qcom,ion-heap-type = "SYSTEM";
};
system_secure_heap: qcom,ion-heap@9 {
reg = <9>;
qcom,ion-heap-type = "SYSTEM_SECURE";
};
qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
reg = <10>;
memory-region = <&secure_display_memory>;
qcom,ion-heap-type = "HYP_CMA";
};
qcom,ion-heap@27 { /* QSEECOM HEAP */
reg = <27>;
memory-region = <&qseecom_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@19 { /* QSEECOM HEAP */
reg = <19>;
memory-region = <&qseecom_ta_mem>;
qcom,ion-heap-type = "DMA";
};
};
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "scuba-iot-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Scuba IDP";
compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
qcom,msm-id = <441 0x10000>, <471 0x10000>;
qcom,board-id = <34 0>;
};

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#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&soc {
scuba_batterydata: qcom,battery-data {
qcom,batt-id-range-pct = <15>;
#include "qg-batterydata-alium-3600mah.dtsi"
#include "qg-batterydata-atl466271_3300mAh.dtsi"
};
};
&pm2250_qg {
qcom,battery-data = <&scuba_batterydata>;
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
qcom,tcss-enable;
qcom,fvss-enable;
qcom,fvss-vbatt-mv = <3500>;
qcom,bass-enable;
};
&pm2250_charger {
interrupts-extended = <&tlmm 89 0>;
interrupt-names = "usb_id_irq";
qcom,usb-id-gpio = <&tlmm 89 0>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_interrupt>;
qcom,auto-recharge-soc = <98>;
qcom,suspend-input-on-debug-batt;
qcom,battery-data = <&scuba_batterydata>;
io-channels = <&pm2250_vadc ADC5_USB_IN_V_16>,
<&pm2250_vadc ADC5_CHG_TEMP>;
io-channel-names = "usb_in_voltage",
"chg_temp";
qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;
};

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/dts-v1/;
#include "scuba-iot.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Scuba IOT SoC";
compatible = "qcom,scuba-iot";
qcom,board-id = <0 0>;
};

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#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/spmi/spmi.h>
/ {
model = "Qualcomm Technologies, Inc. SCUBA";
compatible = "qcom,scuba";
qcom,msm-id = <441 0x10000>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_1: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_2: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_3: l1-dcache {
compatible = "arm,arch-cache";
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_region: hyp_region@45700000 {
no-map;
reg = <0x0 0x45700000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@45e00000 {
no-map;
reg = <0x0 0x45e00000 0x0 0x100000>;
};
sec_apps_mem: sec_apps_region@45fff000 {
no-map;
reg = <0x0 0x45fff000 0x0 0x1000>;
};
smem_region: smem@46000000 {
no-map;
reg = <0x0 0x46000000 0x0 0x200000>;
};
pil_modem_mem: modem_region@4ab00000 {
no-map;
reg = <0x0 0x4ab00000 0x0 0x6900000>;
};
pil_video_mem: pil_video_region@51400000 {
no-map;
reg = <0x0 0x51400000 0x0 0x500000>;
};
wlan_msa_mem: wlan_msa_region@51900000 {
no-map;
reg = <0x0 0x51900000 0x0 0x100000>;
};
pil_adsp_mem: adsp_regions@51a00000 {
no-map;
reg = <0x0 0x51a00000 0x0 0x1c00000>;
};
pil_ipa_fw_mem: ips_fw_region@53600000 {
no-map;
reg = <0x0 0x53600000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi_region@53610000 {
no-map;
reg = <0x0 0x53610000 0x0 0x5000>;
};
pil_gpu_mem: gpu_region@53615000 {
no-map;
reg = <0x0 0x53615000 0x0 0x2000>;
};
removed_region: removed_region@60000000 {
no-map;
reg = <0x0 0x60000000 0x0 0x3900000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x800000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x800000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x5c00000>;
};
cont_splash_memory: cont_splash_region@5c000000 {
reg = <0x0 0x5c000000 0x0 0x00f00000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region@5cf00000 {
reg = <0x0 0x5cf00000 0x0 0x0100000>;
label = "dfps_data_region";
};
disp_rdump_memory: disp_rdump_region@5c000000 {
reg = <0x0 0x5c000000 0x0 0x00f00000>;
label = "disp_rdump_region";
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
};
chosen {
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0xf200000 0x10000>, /* GICD */
<0xf300000 0x100000>; /* GICR * 8 */
interrupts = <1 9 4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 1 0xf08>,
<1 2 0xf08>,
<1 3 0xf08>,
<1 0 0xf08>;
clock-frequency = <19200000>;
};
timer@f120000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xf120000 0x1000>;
clock-frequency = <19200000>;
frame@f121000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 7 0x4>;
reg = <0xf121000 0x1000>,
<0xf122000 0x1000>;
};
frame@f123000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0xf123000 0x1000>;
status = "disabled";
};
frame@f124000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0xf124000 0x1000>;
status = "disabled";
};
frame@f125000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0xf125000 0x1000>;
status = "disabled";
};
frame@f126000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0xf126000 0x1000>;
status = "disabled";
};
frame@f127000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0xf127000 0x1000>;
status = "disabled";
};
frame@f128000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0xf128000 0x1000>;
status = "disabled";
};
};
qcom,msm-imem@c125000 {
compatible = "qcom,msm-imem";
reg = <0xc125000 0x1000>;
ranges = <0x0 0xc125000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
restart@440b000 {
compatible = "qcom,pshold";
reg = <0x440b000 0x4>,
<0x03d3000 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
status="disabled";
};
qcom,mpm2-sleep-counter@4403000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x4403000 0x1000>;
clock-frequency = <32768>;
status="disabled";
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
status="disabled";
};
qcom,chd_silver {
compatible = "qcom,core-hang-detect";
label = "silver";
qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
0x0f1a80b0 0x0f1b80b0>;
qcom,config-arr = <0x0f1880b8 0x0f1980b8
0x0f1a80b8 0x0f1b80b8>;
status="disabled";
};
qfprom: qfprom@1b40000 {
compatible = "qcom,qfprom";
reg = <0x1b40000 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
status="disabled";
feat_conf5: feat_conf5@6018 {
reg = <0x6018 0x4>;
};
};
wdog: qcom,wdt@f017000 {
compatible = "qcom,msm-watchdog";
reg = <0xf017000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
qcom,bark-time = <11000>;
qcom,pet-time = <9360>;
qcom,ipi-ping;
qcom,wakeup-enable;
status = "disabled";
};
dcc: dcc_v2@1be2000 {
compatible = "qcom,dcc-v2";
reg = <0x1be2000 0x1000>,
<0x1bee000 0x2000>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x2000>;
status = "disabled";
};
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-smd";
rpm-channel-name = "rpm_requests";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
rpm-channel-type = <15>; /* SMD_APPS_RPM */
};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
};
c1_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
c2_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
c3_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
l1_icache0 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x60>;
};
l1_icache1 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x61>;
};
l1_icache2 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x62>;
};
l1_icache3 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x63>;
};
l1_dcache0 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x80>;
};
l1_dcache1 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x81>;
};
l1_dcache2 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x82>;
};
l1_dcache3 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x83>;
};
l2_tlb0 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x120>;
};
l2_tlb1 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x121>;
};
l2_tlb2 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x122>;
};
l2_tlb3 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x123>;
};
};
spmi_bus: qcom,spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x1c40000 0x1100>,
<0x1e00000 0x2000000>,
<0x3e00000 0x100000>,
<0x3f00000 0xa0000>,
<0x1c0a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
};
#include "pm2250.dtsi"
#include "pm2250-rpm-regulator.dtsi"
#include "scuba-regulator.dtsi"
#include "scuba-iot-pinctrl.dtsi"
#include "scuba-ion.dtsi"
#include "msm-arm-smmu-scuba.dtsi"
&pm2250_vadc {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&conn_therm_default &skin_therm_default>;
xo_therm {
reg = <ADC5_XO_THERM_100K_PU>;
label = "xo_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pa_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
label = "pa_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
quiet_therm {
reg = <ADC5_AMUX_THM2_100K_PU>;
label = "quiet_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
msm_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
label = "msm_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
label = "skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
conn_therm {
reg = <ADC5_GPIO4_100K_PU>;
label = "conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pm2250_gpios {
skin_therm {
skin_therm_default: skin_therm_default {
pins = "gpio5";
bias-high-impedance;
};
};
conn_therm {
conn_therm_default: conn_therm_default {
pins = "gpio6";
bias-high-impedance;
};
};
};
&spmi_bus {
qcom,pm2250@0 {
pm2250_adc_tm_iio: adc_tm@3400 {
compatible = "qcom,adc-tm5-iio";
reg = <0x3400 0x100>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>,
<&pm2250_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm2250_vadc ADC5_AMUX_THM2_100K_PU>,
<&pm2250_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm2250_vadc ADC5_GPIO3_100K_PU>,
<&pm2250_vadc ADC5_GPIO4_100K_PU>,
<&pm2250_vadc ADC5_SBUx>;
xo_therm {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pa_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
quiet_therm {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
msm_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
conn_therm {
reg = <ADC5_GPIO4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
s3_die_temp {
reg = <ADC5_SBUx>;
};
};
};
};

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#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
&rpm_bus {
/* PM2250 S2 - VDD_CX supply */
rpm-regulator-smpa2 {
status = "okay";
qcom,resource-name = "rwcx";
qcom,resource-id = <0>;
VDD_CX_LEVEL:
VDD_GFX_LEVEL:
VDD_MSS_LEVEL:
S2A_LEVEL: pm2250_s2_level: regulator-s2-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
VDD_CX_FLOOR_LEVEL:
VDD_MSS_FLOOR_LEVEL:
S2A_FLOOR_LEVEL:
pm2250_s2_floor_level: regulator-s2-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2_floor_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
VDD_CX_LEVEL_AO:
VDD_MSS_LEVEL_AO:
S2A_LEVEL_AO: pm2250_s2_level_ao: regulator-s2-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
/* PM2250 L1 - VDD_MX/WCSS_MX supply */
rpm-regulator-ldoa1 {
status = "okay";
qcom,resource-name = "rwmx";
qcom,resource-id = <0>;
VDD_MX_LEVEL:
L1A_LEVEL: pm2250_l1_level: regulator-l1-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
VDD_MX_FLOOR_LEVEL:
L1A_FLOOR_LEVEL:
pm2250_l1_floor_level: regulator-l1-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1_floor_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
VDD_MX_LEVEL_AO:
L1A_LEVEL_AO: pm2250_l1_level_ao: regulator-l1-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
rpm-regulator-smpa3 {
status = "okay";
S3A: pm2250_s3: regulator-s3 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1662500>;
qcom,init-voltage = <400000>;
status = "okay";
};
};
rpm-regulator-smpa4 {
status = "okay";
S4A: pm2250_s4: regulator-s4 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2350000>;
qcom,init-voltage = <1200000>;
status = "okay";
};
};
/* VDD_LPI_CX supply */
rpm-regulator-ldoa8 {
status = "okay";
qcom,resource-name = "rwlc";
qcom,resource-id = <0>;
VDD_LPI_CX_LEVEL:
L8A_LEVEL: pm2250_l8_level: regulator-l8-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l8_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
/* VDD_LPI_MX supply */
rpm-regulator-ldoa9 {
status = "okay";
qcom,resource-name = "rwlm";
qcom,resource-id = <0>;
VDD_LPI_MX_LEVEL:
L9A_LEVEL: pm2250_l9_level: regulator-l9-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l9_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
rpm-regulator-ldoa2 {
status = "okay";
L2A: pm2250_l2: regulator-l2 {
regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1300000>;
qcom,init-voltage = <1060000>;
status = "okay";
};
};
rpm-regulator-ldoa3 {
status = "okay";
L3A: pm2250_l3: regulator-l3 {
regulator-min-microvolt = <570000>;
regulator-max-microvolt = <650000>;
qcom,init-voltage = <570000>;
status = "okay";
};
};
rpm-regulator-ldoa4 {
status = "okay";
L4A: pm2250_l4: regulator-l4 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3050000>;
qcom,init-voltage = <1650000>;
status = "okay";
};
};
rpm-regulator-ldoa5 {
status = "okay";
L5A: pm2250_l5: regulator-l5 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1312000>;
qcom,init-voltage = <1100000>;
status = "okay";
};
};
rpm-regulator-ldoa6 {
status = "okay";
L6A: pm2250_l6: regulator-l6 {
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <1000000>;
qcom,init-voltage = <488000>;
status = "okay";
};
};
/* WCSS_CX */
rpm-regulator-ldoa7 {
status = "okay";
WCSS_CX:
L7A: pm2250_l7: regulator-l7 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <728000>;
qcom,init-voltage = <400000>;
status = "okay";
};
};
rpm-regulator-ldoa10 {
status = "okay";
L10A: pm2250_l10: regulator-l10 {
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1380000>;
qcom,init-voltage = <1150000>;
status = "okay";
};
};
rpm-regulator-ldoa11 {
status = "okay";
L11A: pm2250_l11: regulator-l11 {
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,init-voltage = <950000>;
status = "okay";
};
};
rpm-regulator-ldoa12 {
status = "okay";
L12A: pm2250_l12: regulator-l12 {
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <1000000>;
qcom,init-voltage = <488000>;
status = "okay";
};
};
rpm-regulator-ldoa13 {
status = "okay";
L13A: pm2250_l13: regulator-l13 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1650000>;
status = "okay";
};
};
rpm-regulator-ldoa14 {
status = "okay";
L14A: pm2250_l14: regulator-l14 {
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1700000>;
status = "okay";
};
};
rpm-regulator-ldoa15 {
status = "okay";
L15A: pm2250_l15: regulator-l15 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1200000>;
status = "okay";
};
};
rpm-regulator-ldoa16 {
status = "okay";
L16A: pm2250_l16: regulator-l16 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1500000>;
status = "okay";
};
};
rpm-regulator-ldoa17 {
status = "okay";
L17A: pm2250_l17: regulator-l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
qcom,init-voltage = <3000000>;
status = "okay";
};
};
rpm-regulator-ldoa18 {
status = "okay";
L18A: pm2250_l18: regulator-l18 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
status = "okay";
};
};
rpm-regulator-ldoa19 {
status = "okay";
L19A: pm2250_l19: regulator-l19 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
status = "okay";
};
};
rpm-regulator-ldoa20 {
status = "okay";
L20A: pm2250_l20: regulator-l20 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3600000>;
qcom,init-voltage = <2400000>;
status = "okay";
};
};
rpm-regulator-ldoa21 {
status = "okay";
L21A: pm2250_l21: regulator-l21 {
regulator-min-microvolt = <2921000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <2921000>;
status = "okay";
};
};
rpm-regulator-ldoa22 {
status = "okay";
L22A: pm2250_l22: regulator-l22 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3400000>;
qcom,init-voltage = <2850000>;
status = "okay";
};
};
};