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[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.
Check the cpu type in the OBP device tree before committing to using the optimized Niagara memcpy and memset implementation. If we don't recognize the cpu type, use a completely generic version. Signed-off-by: David S. Miller <[email protected]>
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13 changed files with 604 additions and 37 deletions
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@ -1,8 +1,7 @@
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/* $Id: oplib.h,v 1.14 2001/12/19 00:29:51 davem Exp $
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* oplib.h: Describes the interface and available routines in the
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/* oplib.h: Describes the interface and available routines in the
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* Linux Prom library.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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@ -31,8 +30,10 @@ extern int prom_chosen_node;
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extern const char prom_peer_name[];
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extern const char prom_compatible_name[];
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extern const char prom_root_compatible[];
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extern const char prom_cpu_compatible[];
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extern const char prom_finddev_name[];
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extern const char prom_chosen_path[];
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extern const char prom_cpu_path[];
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extern const char prom_getprop_name[];
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extern const char prom_mmu_name[];
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extern const char prom_callmethod_name[];
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@ -38,6 +38,11 @@
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#define L1DCACHE_SIZE 0x4000
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#define SUN4V_CHIP_INVALID 0x00
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#define SUN4V_CHIP_NIAGARA1 0x01
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#define SUN4V_CHIP_NIAGARA2 0x02
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#define SUN4V_CHIP_UNKNOWN 0xff
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#ifndef __ASSEMBLY__
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enum ultra_tlb_layout {
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@ -49,6 +54,8 @@ enum ultra_tlb_layout {
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extern enum ultra_tlb_layout tlb_type;
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extern int sun4v_chip_type;
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extern int cheetah_pcache_forced_on;
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extern void cheetah_enable_pcache(void);
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@ -63,4 +63,8 @@ static struct xor_block_template xor_block_niagara = {
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/* For VIS for everything except Niagara. */
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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(tlb_type == hypervisor ? &xor_block_niagara : &xor_block_VIS)
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((tlb_type == hypervisor && \
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(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
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sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \
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&xor_block_niagara : \
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&xor_block_VIS)
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