mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
ARM: SoC platform changes for 3.19
New and updated SoC support, notable changes include:
* bcm: brcmstb SMP support
* bcm: initial iproc/cygnus support
* exynos: Exynos4415 SoC support
* exynos: PMU and suspend support for Exynos5420
* exynos: PMU support for Exynos3250
* exynos: pm related maintenance
* imx: new LS1021A SoC support
* imx: vybrid 610 global timer support
* integrator: convert to using multiplatform configuration
* mediatek: earlyprintk support for mt8127/mt8135
* meson: meson8 soc and l2 cache controller support
* mvebu: Armada 38x CPU hotplug support
* mvebu: drop support for prerelease Armada 375 Z1 stepping
* mvebu: extended suspend support, now works on Armada 370/XP
* omap: hwmod related maintenance
* omap: prcm cleanup
* pxa: initial pxa27x DT handling
* rockchip: SMP support for rk3288
* rockchip: add cpu frequency scaling support
* shmobile: r8a7740 power domain support
* shmobile: various small restart, timer, pci apmu changes
* sunxi: Allwinner A80 (sun9i) earlyprintk support
* ux500: power domain support
Overall, a significant chunk of changes, coming mostly from
the usual suspects: omap, shmobile, samsung and mvebu, all of
which already contain a lot of platform specific code in
arch/arm.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
This commit is contained in:
Linus Torvalds
commit
6cd94d5e57
214 changed files with 6329 additions and 2353 deletions
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@ -23,6 +23,7 @@
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#include <linux/list.h>
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#include <linux/of.h>
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#include <linux/bitops.h>
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#include <linux/pm.h>
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#include <asm/bug.h>
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#include <asm/signal.h>
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@ -48,6 +49,7 @@ struct brcmstb_gisb_arb_device {
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struct list_head next;
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u32 valid_mask;
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const char *master_names[sizeof(u32) * BITS_PER_BYTE];
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u32 saved_timeout;
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};
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static LIST_HEAD(brcmstb_gisb_arb_device_list);
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@ -160,12 +162,6 @@ static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
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return ret;
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}
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void __init brcmstb_hook_fault_code(void)
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{
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hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
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"imprecise external abort");
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}
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static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
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{
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brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
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@ -261,12 +257,48 @@ static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
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list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
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hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
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"imprecise external abort");
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dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
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gdev->base, timeout_irq, tea_irq);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int brcmstb_gisb_arb_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
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gdev->saved_timeout = ioread32(gdev->base + ARB_TIMER);
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return 0;
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}
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/* Make sure we provide the same timeout value that was configured before, and
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* do this before the GISB timeout interrupt handler has any chance to run.
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*/
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static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
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iowrite32(gdev->saved_timeout, gdev->base + ARB_TIMER);
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return 0;
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}
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#else
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#define brcmstb_gisb_arb_suspend NULL
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#define brcmstb_gisb_arb_resume_noirq NULL
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#endif
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static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
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.suspend = brcmstb_gisb_arb_suspend,
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.resume_noirq = brcmstb_gisb_arb_resume_noirq,
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};
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static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
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{ .compatible = "brcm,gisb-arb" },
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{ },
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@ -278,6 +310,7 @@ static struct platform_driver brcmstb_gisb_arb_driver = {
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.name = "brcm-gisb-arb",
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.owner = THIS_MODULE,
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.of_match_table = brcmstb_gisb_arb_of_match,
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.pm = &brcmstb_gisb_arb_pm_ops,
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},
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};
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@ -57,6 +57,7 @@
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#include <linux/of_address.h>
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#include <linux/debugfs.h>
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#include <linux/log2.h>
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#include <linux/syscore_ops.h>
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/*
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* DDR target is the same on all platforms.
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@ -94,20 +95,42 @@
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#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
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/* Relative to mbusbridge_base */
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#define MBUS_BRIDGE_CTRL_OFF 0x0
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#define MBUS_BRIDGE_BASE_OFF 0x4
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/* Maximum number of windows, for all known platforms */
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#define MBUS_WINS_MAX 20
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struct mvebu_mbus_state;
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struct mvebu_mbus_soc_data {
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unsigned int num_wins;
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unsigned int num_remappable_wins;
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bool has_mbus_bridge;
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unsigned int (*win_cfg_offset)(const int win);
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void (*setup_cpu_target)(struct mvebu_mbus_state *s);
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int (*save_cpu_target)(struct mvebu_mbus_state *s,
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u32 *store_addr);
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int (*show_cpu_target)(struct mvebu_mbus_state *s,
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struct seq_file *seq, void *v);
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};
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/*
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* Used to store the state of one MBus window accross suspend/resume.
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*/
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struct mvebu_mbus_win_data {
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u32 ctrl;
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u32 base;
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u32 remap_lo;
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u32 remap_hi;
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};
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struct mvebu_mbus_state {
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void __iomem *mbuswins_base;
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void __iomem *sdramwins_base;
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void __iomem *mbusbridge_base;
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phys_addr_t sdramwins_phys_base;
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struct dentry *debugfs_root;
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struct dentry *debugfs_sdram;
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struct dentry *debugfs_devs;
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@ -115,6 +138,11 @@ struct mvebu_mbus_state {
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struct resource pcie_io_aperture;
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const struct mvebu_mbus_soc_data *soc;
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int hw_io_coherency;
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/* Used during suspend/resume */
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u32 mbus_bridge_ctrl;
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u32 mbus_bridge_base;
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struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
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};
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static struct mvebu_mbus_state mbus_state;
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@ -516,6 +544,28 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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mvebu_mbus_dram_info.num_cs = cs;
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}
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static int
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mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
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u32 *store_addr)
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{
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int i;
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for (i = 0; i < 4; i++) {
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u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
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store_addr++);
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writel(base, store_addr++);
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writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
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store_addr++);
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writel(size, store_addr++);
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}
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/* We've written 16 words to the store address */
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return 16;
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}
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static void __init
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mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
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{
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@ -546,10 +596,35 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
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mvebu_mbus_dram_info.num_cs = cs;
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}
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static int
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mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
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u32 *store_addr)
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{
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int i;
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for (i = 0; i < 2; i++) {
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u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
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writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
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store_addr++);
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writel(map, store_addr++);
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}
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/* We've written 4 words to the store address */
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return 4;
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}
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int mvebu_mbus_save_cpu_target(u32 *store_addr)
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{
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return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
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}
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static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
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.num_wins = 20,
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.num_remappable_wins = 8,
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.has_mbus_bridge = true,
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.win_cfg_offset = armada_370_xp_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -558,6 +633,7 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -566,6 +642,7 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_dove_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_dove,
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};
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@ -578,6 +655,7 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -586,6 +664,7 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 2,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -594,6 +673,7 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
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.num_wins = 14,
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.num_remappable_wins = 8,
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.win_cfg_offset = mv78xx0_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -698,11 +778,73 @@ static __init int mvebu_mbus_debugfs_init(void)
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}
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fs_initcall(mvebu_mbus_debugfs_init);
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static int mvebu_mbus_suspend(void)
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{
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struct mvebu_mbus_state *s = &mbus_state;
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int win;
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if (!s->mbusbridge_base)
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return -ENODEV;
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for (win = 0; win < s->soc->num_wins; win++) {
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void __iomem *addr = s->mbuswins_base +
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s->soc->win_cfg_offset(win);
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s->wins[win].base = readl(addr + WIN_BASE_OFF);
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s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
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if (win >= s->soc->num_remappable_wins)
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continue;
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s->wins[win].remap_lo = readl(addr + WIN_REMAP_LO_OFF);
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s->wins[win].remap_hi = readl(addr + WIN_REMAP_HI_OFF);
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}
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s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
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MBUS_BRIDGE_CTRL_OFF);
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s->mbus_bridge_base = readl(s->mbusbridge_base +
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MBUS_BRIDGE_BASE_OFF);
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|
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return 0;
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}
|
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|
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static void mvebu_mbus_resume(void)
|
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{
|
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struct mvebu_mbus_state *s = &mbus_state;
|
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int win;
|
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|
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writel(s->mbus_bridge_ctrl,
|
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s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
|
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writel(s->mbus_bridge_base,
|
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s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
|
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|
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for (win = 0; win < s->soc->num_wins; win++) {
|
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void __iomem *addr = s->mbuswins_base +
|
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s->soc->win_cfg_offset(win);
|
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|
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writel(s->wins[win].base, addr + WIN_BASE_OFF);
|
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writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
|
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|
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if (win >= s->soc->num_remappable_wins)
|
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continue;
|
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|
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writel(s->wins[win].remap_lo, addr + WIN_REMAP_LO_OFF);
|
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writel(s->wins[win].remap_hi, addr + WIN_REMAP_HI_OFF);
|
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}
|
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}
|
||||
|
||||
struct syscore_ops mvebu_mbus_syscore_ops = {
|
||||
.suspend = mvebu_mbus_suspend,
|
||||
.resume = mvebu_mbus_resume,
|
||||
};
|
||||
|
||||
static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
|
||||
phys_addr_t mbuswins_phys_base,
|
||||
size_t mbuswins_size,
|
||||
phys_addr_t sdramwins_phys_base,
|
||||
size_t sdramwins_size)
|
||||
size_t sdramwins_size,
|
||||
phys_addr_t mbusbridge_phys_base,
|
||||
size_t mbusbridge_size)
|
||||
{
|
||||
int win;
|
||||
|
||||
|
|
@ -716,11 +858,26 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mbus->sdramwins_phys_base = sdramwins_phys_base;
|
||||
|
||||
if (mbusbridge_phys_base) {
|
||||
mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
|
||||
mbusbridge_size);
|
||||
if (!mbus->mbusbridge_base) {
|
||||
iounmap(mbus->sdramwins_base);
|
||||
iounmap(mbus->mbuswins_base);
|
||||
return -ENOMEM;
|
||||
}
|
||||
} else
|
||||
mbus->mbusbridge_base = NULL;
|
||||
|
||||
for (win = 0; win < mbus->soc->num_wins; win++)
|
||||
mvebu_mbus_disable_window(mbus, win);
|
||||
|
||||
mbus->soc->setup_cpu_target(mbus);
|
||||
|
||||
register_syscore_ops(&mvebu_mbus_syscore_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -746,7 +903,7 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
|
|||
mbuswins_phys_base,
|
||||
mbuswins_size,
|
||||
sdramwins_phys_base,
|
||||
sdramwins_size);
|
||||
sdramwins_size, 0, 0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
|
@ -887,7 +1044,7 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
|
|||
|
||||
int __init mvebu_mbus_dt_init(bool is_coherent)
|
||||
{
|
||||
struct resource mbuswins_res, sdramwins_res;
|
||||
struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
|
||||
struct device_node *np, *controller;
|
||||
const struct of_device_id *of_id;
|
||||
const __be32 *prop;
|
||||
|
|
@ -923,6 +1080,19 @@ int __init mvebu_mbus_dt_init(bool is_coherent)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the resource to 0 so that it can be left unmapped by
|
||||
* mvebu_mbus_common_init() if the DT doesn't carry the
|
||||
* necessary information. This is needed to preserve backward
|
||||
* compatibility.
|
||||
*/
|
||||
memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
|
||||
|
||||
if (mbus_state.soc->has_mbus_bridge) {
|
||||
if (of_address_to_resource(controller, 2, &mbusbridge_res))
|
||||
pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
|
||||
}
|
||||
|
||||
mbus_state.hw_io_coherency = is_coherent;
|
||||
|
||||
/* Get optional pcie-{mem,io}-aperture properties */
|
||||
|
|
@ -933,7 +1103,9 @@ int __init mvebu_mbus_dt_init(bool is_coherent)
|
|||
mbuswins_res.start,
|
||||
resource_size(&mbuswins_res),
|
||||
sdramwins_res.start,
|
||||
resource_size(&sdramwins_res));
|
||||
resource_size(&sdramwins_res),
|
||||
mbusbridge_res.start,
|
||||
resource_size(&mbusbridge_res));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue