mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
ARM: SoC platform changes for 3.19
New and updated SoC support, notable changes include:
* bcm: brcmstb SMP support
* bcm: initial iproc/cygnus support
* exynos: Exynos4415 SoC support
* exynos: PMU and suspend support for Exynos5420
* exynos: PMU support for Exynos3250
* exynos: pm related maintenance
* imx: new LS1021A SoC support
* imx: vybrid 610 global timer support
* integrator: convert to using multiplatform configuration
* mediatek: earlyprintk support for mt8127/mt8135
* meson: meson8 soc and l2 cache controller support
* mvebu: Armada 38x CPU hotplug support
* mvebu: drop support for prerelease Armada 375 Z1 stepping
* mvebu: extended suspend support, now works on Armada 370/XP
* omap: hwmod related maintenance
* omap: prcm cleanup
* pxa: initial pxa27x DT handling
* rockchip: SMP support for rk3288
* rockchip: add cpu frequency scaling support
* shmobile: r8a7740 power domain support
* shmobile: various small restart, timer, pci apmu changes
* sunxi: Allwinner A80 (sun9i) earlyprintk support
* ux500: power domain support
Overall, a significant chunk of changes, coming mostly from
the usual suspects: omap, shmobile, samsung and mvebu, all of
which already contain a lot of platform specific code in
arch/arm.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAVIcjyGCrR//JCVInAQJJCRAA1Tm+HZGiAiTvXEAcm/T9tIA08uqtawHt
cqyEAUyrnE8QxE4EhUd2pTw4EunVusqKF5EsDxOzw7b3ukUdLAWZE7bqBOSIJLqn
hrfsQQ8dXLbyC7T/CHPnBVeM+pn9LiIc9qzpZ0YToiMnHBBI4vKFQntBjd31yoRE
hN08I6AmDjQolOzzlqR1fuM0uZaKiHIcytdauTt3Vfqgg7FTHcTy3u1kClHTR1Lp
m/KuDothGpR5OKjSnUQz7EO5V3KJEnaKey8z2xM1a7DLLAvJ6r2+DUaDopv9Dbz1
W/V3H7fi5tLvillVa8xmlmzqWZbPc1xw8MWqvHZSWIMRZqloAHpC1VWKn0ZuH4SW
5Bj4ubSrpYjJxjKYfrxtjmuzru3A2jWBNTSP5A4nsny0C3AUsXkfRmRS0VNdegF8
sUdQ1MF8vEMpQT3QPH88+ccFHeIgqbcayhKqLPf7r8q0kwlym5N7Y2amU2A/O6qz
+324r+yzfSA70VgJZ5EhXxWVDOPB4Lc8EtoWnH6T/kjncIMwzEsbEbyB3X1OaREW
pVn3PNo06VjHLYoiHX+8G99pOFR/JZvaQs6jGCXLs+Orjp5WfP+kafkWqcB5GAKU
Pfd3AQsl6rKAITdu0XsTdPiICNS4CmBiWYPepQsTa3pQaNgB7fwZNQKelNRIdGc+
dF1lnQ7CXLQ=
=lFoH
-----END PGP SIGNATURE-----
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
This commit is contained in:
Linus Torvalds
commit
6cd94d5e57
214 changed files with 6329 additions and 2353 deletions
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
|
@ -177,14 +178,17 @@ struct clk_gating_ctrl {
|
|||
spinlock_t *lock;
|
||||
struct clk **gates;
|
||||
int num_gates;
|
||||
void __iomem *base;
|
||||
u32 saved_reg;
|
||||
};
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
static struct clk_gating_ctrl *ctrl;
|
||||
|
||||
static struct clk *clk_gating_get_src(
|
||||
struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
|
||||
int n;
|
||||
|
||||
if (clkspec->args_count < 1)
|
||||
|
|
@ -199,15 +203,35 @@ static struct clk *clk_gating_get_src(
|
|||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
static int mvebu_clk_gating_suspend(void)
|
||||
{
|
||||
ctrl->saved_reg = readl(ctrl->base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mvebu_clk_gating_resume(void)
|
||||
{
|
||||
writel(ctrl->saved_reg, ctrl->base);
|
||||
}
|
||||
|
||||
static struct syscore_ops clk_gate_syscore_ops = {
|
||||
.suspend = mvebu_clk_gating_suspend,
|
||||
.resume = mvebu_clk_gating_resume,
|
||||
};
|
||||
|
||||
void __init mvebu_clk_gating_setup(struct device_node *np,
|
||||
const struct clk_gating_soc_desc *desc)
|
||||
{
|
||||
struct clk_gating_ctrl *ctrl;
|
||||
struct clk *clk;
|
||||
void __iomem *base;
|
||||
const char *default_parent = NULL;
|
||||
int n;
|
||||
|
||||
if (ctrl) {
|
||||
pr_err("mvebu-clk-gating: cannot instantiate more than one gatable clock device\n");
|
||||
return;
|
||||
}
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
|
|
@ -225,6 +249,8 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
|
|||
/* lock must already be initialized */
|
||||
ctrl->lock = &ctrl_gating_lock;
|
||||
|
||||
ctrl->base = base;
|
||||
|
||||
/* Count, allocate, and register clock gates */
|
||||
for (n = 0; desc[n].name;)
|
||||
n++;
|
||||
|
|
@ -246,6 +272,8 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
|
|||
|
||||
of_clk_add_provider(np, clk_gating_get_src, ctrl);
|
||||
|
||||
register_syscore_ops(&clk_gate_syscore_ops);
|
||||
|
||||
return;
|
||||
gates_out:
|
||||
kfree(ctrl);
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
|
@ -23,6 +25,8 @@
|
|||
#define CPU_CLK_STATUS 0xfc
|
||||
#define MISC_DOUT1 0x558
|
||||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
/* parent clock name list */
|
||||
PNAME(mout_armclk_p) = { "cplla", "cpllb" };
|
||||
PNAME(mout_spi_p) = { "div125", "div200" };
|
||||
|
|
@ -89,10 +93,30 @@ static const struct of_device_id ext_clk_match[] __initconst = {
|
|||
{},
|
||||
};
|
||||
|
||||
static int exynos5440_clk_restart_notify(struct notifier_block *this,
|
||||
unsigned long code, void *unused)
|
||||
{
|
||||
u32 val, status;
|
||||
|
||||
status = readl_relaxed(reg_base + 0xbc);
|
||||
val = readl_relaxed(reg_base + 0xcc);
|
||||
val = (val & 0xffff0000) | (status & 0xffff);
|
||||
writel_relaxed(val, reg_base + 0xcc);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Exynos5440 Clock restart notifier, handles restart functionality
|
||||
*/
|
||||
static struct notifier_block exynos5440_clk_restart_handler = {
|
||||
.notifier_call = exynos5440_clk_restart_notify,
|
||||
.priority = 128,
|
||||
};
|
||||
|
||||
/* register exynos5440 clocks */
|
||||
static void __init exynos5440_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_provider *ctx;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
|
|
@ -125,6 +149,9 @@ static void __init exynos5440_clk_init(struct device_node *np)
|
|||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
if (register_restart_handler(&exynos5440_clk_restart_handler))
|
||||
pr_warn("exynos5440 clock can't register restart handler\n");
|
||||
|
||||
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
|
||||
pr_info("exynos5440 clock initialization complete\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,6 +33,9 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
|
|||
.recalc_rate = &omap4_dpll_regm4xen_recalc,
|
||||
.round_rate = &omap4_dpll_regm4xen_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.set_parent = &omap3_noncore_dpll_set_parent,
|
||||
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
|
||||
.determine_rate = &omap4_dpll_regm4xen_determine_rate,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
};
|
||||
#else
|
||||
|
|
@ -53,6 +56,9 @@ static const struct clk_ops dpll_ck_ops = {
|
|||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.set_parent = &omap3_noncore_dpll_set_parent,
|
||||
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
|
||||
.determine_rate = &omap3_noncore_dpll_determine_rate,
|
||||
.get_parent = &omap2_init_dpll_parent,
|
||||
};
|
||||
|
||||
|
|
@ -61,6 +67,9 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
|
|||
.get_parent = &omap2_init_dpll_parent,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.set_parent = &omap3_noncore_dpll_set_parent,
|
||||
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
|
||||
.determine_rate = &omap3_noncore_dpll_determine_rate,
|
||||
};
|
||||
#else
|
||||
static const struct clk_ops dpll_core_ck_ops = {};
|
||||
|
|
@ -97,6 +106,9 @@ static const struct clk_ops omap3_dpll_ck_ops = {
|
|||
.get_parent = &omap2_init_dpll_parent,
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.set_rate = &omap3_noncore_dpll_set_rate,
|
||||
.set_parent = &omap3_noncore_dpll_set_parent,
|
||||
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
|
||||
.determine_rate = &omap3_noncore_dpll_determine_rate,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
};
|
||||
|
||||
|
|
@ -106,6 +118,9 @@ static const struct clk_ops omap3_dpll_per_ck_ops = {
|
|||
.get_parent = &omap2_init_dpll_parent,
|
||||
.recalc_rate = &omap3_dpll_recalc,
|
||||
.set_rate = &omap3_dpll4_set_rate,
|
||||
.set_parent = &omap3_noncore_dpll_set_parent,
|
||||
.set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
|
||||
.determine_rate = &omap3_noncore_dpll_determine_rate,
|
||||
.round_rate = &omap2_dpll_round_rate,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue