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msm: kgsl: Remove soft fault registers from a5xx

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All 5xx targets use hardware based fault detection so we don't need to
define soft fault registers that will never get used.

Change-Id: Ic0dedbad7e5029db3b70a333c59c9844251df6ae
Signed-off-by: Jordan Crouse <[email protected]>
This commit is contained in:
Jordan Crouse 2020-01-22 15:39:02 -07:00
commit 6cf52e12f4
1 changed files with 0 additions and 9 deletions
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9
drivers/gpu/msm/adreno_a5xx.c
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@ -2314,13 +2314,6 @@ static struct adreno_perfcounters a5xx_perfcounters = {
ARRAY_SIZE(a5xx_perfcounter_groups),
};
static struct adreno_ft_perf_counters a5xx_ft_perf_counters[] = {
{KGSL_PERFCOUNTER_GROUP_SP, A5XX_SP_ALU_ACTIVE_CYCLES},
{KGSL_PERFCOUNTER_GROUP_SP, A5XX_SP0_ICL1_MISSES},
{KGSL_PERFCOUNTER_GROUP_SP, A5XX_SP_FS_CFLOW_INSTRUCTIONS},
{KGSL_PERFCOUNTER_GROUP_TSE, A5XX_TSE_INPUT_PRIM_NUM},
};
/* Register offset defines for A5XX, in order of enum adreno_regs */
static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A5XX_CP_RB_BASE),
@ -2958,8 +2951,6 @@ static struct adreno_coresight a5xx_coresight = {
struct adreno_gpudev adreno_a5xx_gpudev = {
.reg_offsets = a5xx_register_offsets,
.ft_perf_counters = a5xx_ft_perf_counters,
.ft_perf_counters_count = ARRAY_SIZE(a5xx_ft_perf_counters),
#ifdef CONFIG_QCOM_KGSL_CORESIGHT
.coresight = {&a5xx_coresight},
#endif