mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 14:19:09 -04:00
Merge "ARM: dts: msm: Adding CoreTech sa8195 DT Changes to Mainline 5.4"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
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8 changed files with 2588 additions and 59 deletions
832
qcom/sa8195-qupv3.dtsi
Normal file
832
qcom/sa8195-qupv3.dtsi
Normal file
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@ -0,0 +1,832 @@
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#include <dt-bindings/interconnect/qcom,scshrike.h>
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&soc {
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/* QUPv3 West Instances
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* West 0 : SE 0
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* West 1 : SE 1
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* West 2 : SE 2
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* West 3 : SE 3
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* West 4 : SE 4
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* West 5 : SE 5
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* West 6 : SE 6
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* West 7 : SE 7
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*
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* QUPv3 East0 and East1 Instances
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* East1 0 : SE 8
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* East1 1 : SE 9
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* East1 2 : SE 10
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* East1 3 : SE 11
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* East1 4 : SE 12
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* East1 5 : SE 16
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* East1 0 : SE 17
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* East0 1 : SE 18
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* East0 2 : SE 19
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* East0 3 : SE 13
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* East0 4 : SE 14
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* East0 5 : SE 15
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*/
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x8c0000 0x6000>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_0 SLAVE_EBI1>;
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iommus = <&apps_smmu 0x4c3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok"
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};
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/* I2C */
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qupv3_se0_i2c: i2c@880000 {
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compatible = "qcom,i2c-geni";
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reg = <0x880000 0x4000>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@884000 {
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compatible = "qcom,i2c-geni";
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reg = <0x884000 0x4000>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@88c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x88c000 0x4000>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@890000 {
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compatible = "qcom,i2c-geni";
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reg = <0x890000 0x4000>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@894000 {
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compatible = "qcom,i2c-geni";
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reg = <0x894000 0x4000>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se6_i2c: i2c@898000 {
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compatible = "qcom,i2c-geni";
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reg = <0x898000 0x4000>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se7_i2c: i2c@89c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x89c000 0x4000>;
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_i2c_active>;
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pinctrl-1 = <&qupv3_se7_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* SPI */
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qupv3_se0_spi: spi@880000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x880000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_spi: spi@884000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x884000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_spi_active>;
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_spi: spi@888000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x888000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_spi: spi@88c000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x88c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_spi_active>;
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pinctrl-1 = <&qupv3_se3_spi_sleep>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_spi: spi@890000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x890000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_spi_active>;
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pinctrl-1 = <&qupv3_se4_spi_sleep>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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||||
spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
|
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status = "disabled";
|
||||
};
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||||
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qupv3_se5_spi: spi@894000 {
|
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compatible = "qcom,spi-geni";
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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reg = <0x894000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
|
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
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pinctrl-names = "default", "sleep";
|
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pinctrl-0 = <&qupv3_se5_spi_active>;
|
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pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
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spi-max-frequency = <50000000>;
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||||
qcom,wrapper-core = <&qupv3_0>;
|
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status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_spi: spi@898000 {
|
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compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x898000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_spi: spi@89c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x89c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se7_spi_sleep>;
|
||||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* QUPv3 East1 Instances */
|
||||
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0xac0000 0x6000>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-bus-ids =
|
||||
<MASTER_QUP_1 SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x603 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
/* Debug UART Instance for CDP/MTP platform */
|
||||
qupv3_se12_2uart: qcom,qup_uart@0xa90000 {
|
||||
compatible = "qcom,msm-geni-console";
|
||||
reg = <0xa90000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se12_2uart_active>;
|
||||
pinctrl-1 = <&qupv3_se12_2uart_sleep>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* 4-wire UART */
|
||||
qupv3_se13_4uart: qcom,qup_uart@0xc8c000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0xc8c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "active", "sleep";
|
||||
pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>,
|
||||
<&qupv3_se13_default_tx>;
|
||||
pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
|
||||
<&qupv3_se13_tx>;
|
||||
pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
|
||||
<&qupv3_se13_tx>;
|
||||
interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 46 0>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I2C */
|
||||
qupv3_se8_i2c: i2c@a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_i2c: i2c@a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_i2c: i2c@a88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa88000 0x4000>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se11_i2c: i2c@a8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se11_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se12_i2c: i2c@a90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se12_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SPI */
|
||||
qupv3_se8_spi: spi@a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa80000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se8_spi_active>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_spi: spi@a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa84000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_spi: spi@a88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa88000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se11_spi: spi@a8c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa8c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se11_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se11_spi_sleep>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se12_spi: spi@a90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa90000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se12_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se12_spi_sleep>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* QUPv3 East Instances */
|
||||
qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0xcc0000 0x6000>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-bus-ids =
|
||||
<MASTER_QUP_2 SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x7a3 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
/* I2C */
|
||||
qupv3_se13_i2c: i2c@c8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xc8c000 0x4000>;
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se13_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se14_i2c: i2c@0xc90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xc90000 0x4000>;
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se14_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se15_i2c: i2c@0xc94000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xc94000 0x4000>;
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se15_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se16_i2c: i2c@0xa94000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa94000 0x4000>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se16_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se16_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se17_i2c: i2c@0xc80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xc80000 0x4000>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se17_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se17_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se18_i2c: i2c@0xc84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xc84000 0x4000>;
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se18_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se18_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se19_i2c: i2c@0xc88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xc88000 0x4000>;
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se19_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se19_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SPI */
|
||||
qupv3_se13_spi: spi@c8c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc8c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se13_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se13_spi_sleep>;
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se14_spi: spi@c90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc90000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se14_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se14_spi_sleep>;
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se15_spi: spi@c94000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc94000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se15_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se15_spi_sleep>;
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se16_spi: spi@a94000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa94000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se16_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se16_spi_sleep>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se17_spi: spi@c80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc80000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se17_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se17_spi_sleep>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se18_spi: spi@c84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc84000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se18_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se18_spi_sleep>;
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se19_spi: spi@c88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc88000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se19_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se19_spi_sleep>;
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
109
qcom/sa8195-ssc-qupv3.dtsi
Normal file
109
qcom/sa8195-ssc-qupv3.dtsi
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
#include <dt-bindings/interconnect/qcom,scshrike.h>
|
||||
|
||||
&soc {
|
||||
/* QUPv3 SSC Instance */
|
||||
qupv3_3: qcom,qupv3_3_geni_se@26c0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0x26c0000 0x6000>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-bus-ids =
|
||||
<MASTER_SENSORS_AHB SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x4e3 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I2C*/
|
||||
qupv3_se20_i2c: i2c@2680000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x2680000 0x4000>;
|
||||
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE0_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se20_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se20_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se21_i2c: i2c@2684000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x2684000 0x4000>;
|
||||
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE1_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se21_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se21_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se22_i2c: i2c@2688000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x2688000 0x4000>;
|
||||
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE2_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se22_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se22_i2c_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SPI */
|
||||
qupv3_se21_spi: spi@2684000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x2684000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE1_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se21_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se21_spi_sleep>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_3>;
|
||||
qcom,disable-dma;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se22_spi: spi@2688000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x2688000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&scc SCC_QUPV3_SE2_CLK>,
|
||||
<&scc SCC_QUPV3_M_HCLK_CLK>,
|
||||
<&scc SCC_QUPV3_S_HCLK_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se22_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se22_spi_sleep>;
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_3>;
|
||||
qcom,disable-dma;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
203
qcom/sa8195-usb.dtsi
Normal file
203
qcom/sa8195-usb.dtsi
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
#include <dt-bindings/clock/qcom,gcc-scshrike.h>
|
||||
|
||||
&soc {
|
||||
/* Primary USB port related controller */
|
||||
usb0: ssusb@a600000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0x0a600000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
iommus = <&apps_smmu 0x140 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"ss_phy_irq", "dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_prim_gdsc>;
|
||||
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"utmi_clk", "sleep_clk", "xo";
|
||||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
|
||||
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
interconnect-names = "usb-ddr", "ddr-usb";
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
|
||||
|
||||
dwc3@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0a600000 0xcd00>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x0>;
|
||||
snps,is-utmi-l1-suspend;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
qcom,usbbam@a704000 {
|
||||
compatible = "qcom,usb-bam-msm";
|
||||
reg = <0xa704000 0x17000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
|
||||
qcom,usb-bam-num-pipes = <4>;
|
||||
qcom,disable-clk-gating;
|
||||
qcom,usb-bam-override-threshold = <0x4001>;
|
||||
qcom,usb-bam-max-mbps-highspeed = <400>;
|
||||
qcom,usb-bam-max-mbps-superspeed = <3600>;
|
||||
qcom,reset-bam-on-connect;
|
||||
|
||||
qcom,pipe0 {
|
||||
label = "ssusb-qdss-in-0";
|
||||
qcom,usb-bam-mem-type = <2>;
|
||||
qcom,dir = <1>;
|
||||
qcom,pipe-num = <0>;
|
||||
qcom,peer-bam = <0>;
|
||||
qcom,peer-bam-physical-address = <0x6064000>;
|
||||
qcom,src-bam-pipe-index = <0>;
|
||||
qcom,dst-bam-pipe-index = <0>;
|
||||
qcom,data-fifo-offset = <0x0>;
|
||||
qcom,data-fifo-size = <0x1800>;
|
||||
qcom,descriptor-fifo-offset = <0x1800>;
|
||||
qcom,descriptor-fifo-size = <0x800>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Primary USB port related High Speed PHY */
|
||||
usb2_phy0: hsphy@88e2000 {
|
||||
compatible = "qcom,usb-hsphy-snps-femto";
|
||||
reg = <0x88e2000 0x110>,
|
||||
<0x007801f8 0x4>;
|
||||
reg-names = "hsusb_phy_base",
|
||||
"phy_rcal_reg";
|
||||
|
||||
vdd-supply = <&pm8150_2_l5>;
|
||||
vdda18-supply = <&pm8150_1_l12>;
|
||||
vdda33-supply = <&pm8150_2_l16>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "ref_clk_src";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
qcom,param-override-seq = <0x43 0x70>;
|
||||
qcom,rcal-mask = <0x1e00000>;
|
||||
};
|
||||
|
||||
usb_nop_phy: usb_nop_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
/* Secondary USB port related controller */
|
||||
usb1: ssusb@a800000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0x0a800000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
iommus = <&apps_smmu 0x160 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"ss_phy_irq", "dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
qcom,default-mode-host;
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_sec_gdsc>;
|
||||
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"utmi_clk", "sleep_clk", "xo";
|
||||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
|
||||
|
||||
interconnect-names = "usb-ddr", "ddr-usb";
|
||||
interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
|
||||
|
||||
dwc3@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0a800000 0xcd00>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x0>;
|
||||
snps,is-utmi-l1-suspend;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
|
||||
/* Secondary USB port related High Speed PHY */
|
||||
usb2_phy1: hsphy@88e3000 {
|
||||
compatible = "qcom,usb-hsphy-snps-femto";
|
||||
reg = <0x88e3000 0x110>,
|
||||
<0x007801f8 0x4>;
|
||||
reg-names = "hsusb_phy_base",
|
||||
"phy_rcal_reg";
|
||||
|
||||
vdd-supply = <&pm8150_2_l5>;
|
||||
vdda18-supply = <&pm8150_1_l12>;
|
||||
vdda33-supply = <&pm8150_2_l16>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "ref_clk_src";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
qcom,param-override-seq = <0x43 0x70>;
|
||||
qcom,rcal-mask = <0x1e00000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,5 +1,27 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&qupv3_id_1 {
|
||||
&qupv3_3 {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&qupv3_se12_2uart {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
vdd-supply = <&pm8195_1_l10>;
|
||||
qcom,vdd-voltage-level = <2950000 2960000>;
|
||||
qcom,vdd-current-level = <200 800000>;
|
||||
|
||||
vdd-io-supply = <&pm8195_1_l2>;
|
||||
qcom,vdd-io-voltage-level = <1808000 2960000>;
|
||||
qcom,vdd-io-current-level = <200 22000>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_on>;
|
||||
pinctrl-1 = <&sdc2_off>;
|
||||
|
||||
cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "ok"
|
||||
};
|
||||
|
|
|
|||
1326
qcom/sa8195p-pcie.dtsi
Normal file
1326
qcom/sa8195p-pcie.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,6 @@
|
|||
#include "sdmshrike-v2.dtsi"
|
||||
#include "sa8195-pmic.dtsi"
|
||||
#include "sa8195p-pcie.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195P";
|
||||
|
|
@ -41,3 +42,16 @@
|
|||
|
||||
status= "ok"
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
vdd-supply = <&pm8195_3_l5>;
|
||||
vdda18-supply = <&pm8195_1_l12>;
|
||||
vdda33-supply = <&pm8195_3_l16>;
|
||||
};
|
||||
|
||||
|
||||
&usb2_phy1 {
|
||||
vdd-supply = <&pm8195_3_l5>;
|
||||
vdda18-supply = <&pm8195_1_l12>;
|
||||
vdda33-supply = <&pm8195_3_l16>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2645,77 +2645,55 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdc2_clk_on: sdc2_clk_on {
|
||||
config {
|
||||
sdc2_on: sdc2_on {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <16>; /* 16 MA */
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
|
||||
sd-cd {
|
||||
pins = "gpio96";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_clk_off: sdc2_clk_off {
|
||||
config {
|
||||
sdc2_off: sdc2_off {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable; /* NO pull */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cmd_on: sdc2_cmd_on {
|
||||
config {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cmd_off: sdc2_cmd_off {
|
||||
config {
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_data_on: sdc2_data_on {
|
||||
config {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <10>; /* 10 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_data_off: sdc2_data_off {
|
||||
config {
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cd_on: cd_on {
|
||||
mux {
|
||||
pins = "gpio96"; /* sdcard_det */
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
sd-cd {
|
||||
pins = "gpio96";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cd_off: cd_off {
|
||||
mux {
|
||||
pins = "gpio96";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio96";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
bias-disable; /* pull up */
|
||||
drive-strength = <2>; /* 2 MA */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -28,8 +28,9 @@
|
|||
memory { device_type = "memory"; reg = <0 0 0 0>; };
|
||||
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
|
||||
serial0 = &qupv3_se12_2uart;
|
||||
sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -1409,19 +1410,60 @@
|
|||
};
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x00ac0000 0x6000>;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
sdhc_2: sdhci@8804000 {
|
||||
compatible = "qcom,sdhci-msm-v5";
|
||||
reg = <0x8804000 0x1000>;
|
||||
reg-names = "hc_mem";
|
||||
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&gcc GCC_SDCC2_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
|
||||
bus-width = <4>;
|
||||
qcom,restore-after-cx-collapse;
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
|
||||
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
||||
|
||||
qcom,msm-bus,name = "sdhc2";
|
||||
qcom,msm-bus,num-cases = <6>;
|
||||
qcom,msm-bus,num-paths = <2>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
/* No vote */
|
||||
<0 0>, <0 0>,
|
||||
/* 25 MB/s */
|
||||
<65360 100000>,<100000 100000>,
|
||||
/* 50 MB/s */
|
||||
<130718 200000>,<100000 100000>,
|
||||
/* 100 MB/s */
|
||||
<261438 200000>,<130000 130000>,
|
||||
/* 200 MB/s */
|
||||
<261438 400000>,<300000 300000>,
|
||||
/* Max. bandwidth */
|
||||
<1338562 4096000>,<1338562 4096000>;
|
||||
qcom,bus-bw-vectors-bps = <0 25000000 50000000
|
||||
100000000 200000000 4294967295>;
|
||||
|
||||
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
||||
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
|
||||
|
||||
qcom,devfreq,freq-table = <50000000 200000000>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
uart2: serial@a90000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x0 0x00a90000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "ok"
|
||||
qos0 {
|
||||
mask = <0x0f>;
|
||||
vote = <70>;
|
||||
};
|
||||
|
||||
qos1 {
|
||||
mask = <0xf0>;
|
||||
vote = <70>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1435,6 +1477,9 @@
|
|||
#include "msm-arm-smmu-sdmshrike.dtsi"
|
||||
#include "sm8150-slpi-pinctrl.dtsi"
|
||||
#include "sdmshrike-ion.dtsi"
|
||||
#include "sa8195-qupv3.dtsi"
|
||||
#include "sa8195-ssc-qupv3.dtsi"
|
||||
#include "sa8195-usb.dtsi"
|
||||
|
||||
&emac_gdsc {
|
||||
status = "ok"
|
||||
|
|
|
|||
Loading…
Reference in a new issue