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[PATCH] ppc64: fix for kexec boot issue

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The kexec boot is not successful on some power machines since all CPUs are
getting removed from global interrupt queue (GIQ) before kexec boot.  Some
systems always expect at least one CPU in GIQ.  Hence, this patch will make
sure that only secondary CPUs are removed from GIQ.

Signed-off-by: Haren Myneni <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
This commit is contained in:
Paul Mackerras 2005-08-04 12:53:37 -07:00 • committed by Linus Torvalds
commit 6d22d85a85
6 changed files with 24 additions and 23 deletions
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6
arch/ppc64/kernel/machine_kexec.c
View file

@ -185,7 +185,7 @@ void kexec_copy_flush(struct kimage *image)
void kexec_smp_down(void *arg)
{
if (ppc_md.cpu_irq_down)
ppc_md.cpu_irq_down();
ppc_md.cpu_irq_down(1);
local_irq_disable();
kexec_smp_wait();
@ -232,7 +232,7 @@ static void kexec_prepare_cpus(void)
/* after we tell the others to go down */
if (ppc_md.cpu_irq_down)
ppc_md.cpu_irq_down();
ppc_md.cpu_irq_down(0);
put_cpu();
@ -255,7 +255,7 @@ static void kexec_prepare_cpus(void)
*/
smp_release_cpus();
if (ppc_md.cpu_irq_down)
ppc_md.cpu_irq_down();
ppc_md.cpu_irq_down(0);
local_irq_disable();
}

4
arch/ppc64/kernel/mpic.c
View file

@ -794,10 +794,10 @@ void mpic_setup_this_cpu(void)
/*
* XXX: someone who knows mpic should check this.
* do we need to eoi the ipi here (see xics comments)?
* do we need to eoi the ipi including for kexec cpu here (see xics comments)?
* or can we reset the mpic in the new kernel?
*/
void mpic_teardown_this_cpu(void)
void mpic_teardown_this_cpu(int secondary)
{
struct mpic *mpic = mpic_primary;
unsigned long flags;

2
arch/ppc64/kernel/mpic.h
View file

@ -256,7 +256,7 @@ extern unsigned int mpic_irq_get_priority(unsigned int irq);
extern void mpic_setup_this_cpu(void);
/* Clean up for kexec (or cpu offline or ...) */
extern void mpic_teardown_this_cpu(void);
extern void mpic_teardown_this_cpu(int secondary);
/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);

31
arch/ppc64/kernel/xics.c
View file

@ -647,29 +647,30 @@ static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
}
}
void xics_teardown_cpu(void)
void xics_teardown_cpu(int secondary)
{
int cpu = smp_processor_id();
int status;
ops->cppr_info(cpu, 0x00);
iosync();
/*
* we need to EOI the IPI if we got here from kexec down IPI
*
* xics doesn't care if we duplicate an EOI as long as we
* don't EOI and raise priority.
*
* probably need to check all the other interrupts too
* should we be flagging idle loop instead?
* or creating some task to be scheduled?
* Some machines need to have at least one cpu in the GIQ,
* so leave the master cpu in the group.
*/
ops->xirr_info_set(cpu, XICS_IPI);
status = rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
(1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
WARN_ON(status != 0);
if (secondary) {
/*
* we need to EOI the IPI if we got here from kexec down IPI
*
* probably need to check all the other interrupts too
* should we be flagging idle loop instead?
* or creating some task to be scheduled?
*/
ops->xirr_info_set(cpu, XICS_IPI);
rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
(1UL << interrupt_server_size) - 1 -
default_distrib_server, 0);
}
}
#ifdef CONFIG_HOTPLUG_CPU