mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
mmc: sh_mmcif: revision-specific CLK_CTRL2 handling
Some newer MMCIF IP revisions contain a CE_CLK_CTRL2 register, that has to be set for proper operation. Support for this feature is added in a way to preserve the current behaviour by default, i.e. when it is not enabled in platform data. Patch is based on work by Nobuyuki HIRAI. Signed-off-by: Guennadi Liakhovetski <[email protected]> Signed-off-by: Chris Ball <[email protected]>
This commit is contained in:
parent
967bcb7717
commit
6d6fd36742
2 changed files with 6 additions and 0 deletions
|
|
@ -247,6 +247,7 @@ struct sh_mmcif_host {
|
|||
bool power;
|
||||
bool card_present;
|
||||
bool ccs_enable; /* Command Completion Signal support */
|
||||
bool clk_ctrl2_enable;
|
||||
struct mutex thread_lock;
|
||||
|
||||
/* DMA support */
|
||||
|
|
@ -497,6 +498,8 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
|
|||
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
|
||||
if (host->ccs_enable)
|
||||
tmp |= SCCSTO_29;
|
||||
if (host->clk_ctrl2_enable)
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
|
||||
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
|
||||
SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
|
||||
/* byte swap on */
|
||||
|
|
@ -1398,6 +1401,7 @@ static int sh_mmcif_probe(struct platform_device *pdev)
|
|||
host->addr = reg;
|
||||
host->timeout = msecs_to_jiffies(1000);
|
||||
host->ccs_enable = !pd || !pd->ccs_unsupported;
|
||||
host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
|
||||
|
||||
host->pd = pdev;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue