mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
Merge branches 'defcfg', 'drivers' and 'cyberpro-next' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'defcfg' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6647/1: add Versatile Express defconfig ARM: 6644/1: mach-ux500: update the U8500 defconfig * 'drivers' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6764/1: pl011: factor out FIFO to TTY code ARM: 6763/1: pl011: add optional RX DMA to PL011 v2 ARM: 6758/1: amba: support pm ops ARM: amba: make amba_driver id_table const ARM: amba: make internal ID table handling const ARM: amba: make probe() functions take const id tables ARM: 6662/1: amba: make amba_bustype non-static ARM: mmci: add dmaengine-based DMA support ARM: mmci: no need for separate host->data_xfered ARM: mmci: avoid unnecessary switch to data available PIO interrupts ARM: mmci: no need to call flush_dcache_page() with sg_miter API ARM: mmci: avoid reporting too many completed bytes on fifo overrun ALSA: AACI: make fifo variables more explanitory ALSA: AACI: no need to call snd_pcm_period_elapsed() for each period ALSA: AACI: use snd_pcm_lib_period_bytes() ALSA: AACI: clean up AACI announcement printk ALSA: AACI: fix channel mask selection ALSA: AACI: fix number of channels for record ALSA: AACI: fix multiple IRQ claiming * 'cyberpro-next' of master.kernel.org:/home/rmk/linux-2.6-arm: VIDEO: cyberpro: remove unused cyber2000fb_get_fb_var() VIDEO: cyberpro: remove useless function extreg pointers VIDEO: cyberpro: update handling of device structures VIDEO: cyberpro: add support for video capture I2C VIDEO: cyberpro: make 'reg_b0_lock' always present VIDEO: cyberpro: add I2C support VIDEO: cyberpro: select lowest multipler/divisor for PLL
This commit is contained in:
Linus Torvalds
commit
6d7ed21d17
25 changed files with 1710 additions and 356 deletions
|
|
@ -2,7 +2,7 @@
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|||
* linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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* Copyright (C) 2010 ST-Ericsson AB.
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* Copyright (C) 2010 ST-Ericsson SA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -25,8 +25,10 @@
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#include <linux/clk.h>
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#include <linux/scatterlist.h>
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#include <linux/gpio.h>
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#include <linux/amba/mmci.h>
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#include <linux/regulator/consumer.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/amba/mmci.h>
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#include <asm/div64.h>
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#include <asm/io.h>
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@ -142,9 +144,6 @@ mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
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host->mrq = NULL;
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host->cmd = NULL;
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if (mrq->data)
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mrq->data->bytes_xfered = host->data_xfered;
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/*
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* Need to drop the host lock here; mmc_request_done may call
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* back into the driver...
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@ -189,6 +188,248 @@ static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
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sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
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}
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/*
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* All the DMA operation mode stuff goes inside this ifdef.
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* This assumes that you have a generic DMA device interface,
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* no custom DMA interfaces are supported.
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*/
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#ifdef CONFIG_DMA_ENGINE
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static void __devinit mmci_dma_setup(struct mmci_host *host)
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{
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struct mmci_platform_data *plat = host->plat;
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const char *rxname, *txname;
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dma_cap_mask_t mask;
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if (!plat || !plat->dma_filter) {
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dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
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return;
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}
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/* Try to acquire a generic DMA engine slave channel */
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/*
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* If only an RX channel is specified, the driver will
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* attempt to use it bidirectionally, however if it is
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* is specified but cannot be located, DMA will be disabled.
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*/
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if (plat->dma_rx_param) {
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host->dma_rx_channel = dma_request_channel(mask,
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plat->dma_filter,
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plat->dma_rx_param);
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/* E.g if no DMA hardware is present */
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if (!host->dma_rx_channel)
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dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
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}
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if (plat->dma_tx_param) {
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host->dma_tx_channel = dma_request_channel(mask,
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plat->dma_filter,
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plat->dma_tx_param);
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if (!host->dma_tx_channel)
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dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
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} else {
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host->dma_tx_channel = host->dma_rx_channel;
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}
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if (host->dma_rx_channel)
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rxname = dma_chan_name(host->dma_rx_channel);
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else
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rxname = "none";
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if (host->dma_tx_channel)
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txname = dma_chan_name(host->dma_tx_channel);
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else
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txname = "none";
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dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
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rxname, txname);
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/*
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* Limit the maximum segment size in any SG entry according to
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* the parameters of the DMA engine device.
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*/
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if (host->dma_tx_channel) {
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struct device *dev = host->dma_tx_channel->device->dev;
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unsigned int max_seg_size = dma_get_max_seg_size(dev);
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if (max_seg_size < host->mmc->max_seg_size)
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host->mmc->max_seg_size = max_seg_size;
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}
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if (host->dma_rx_channel) {
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struct device *dev = host->dma_rx_channel->device->dev;
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unsigned int max_seg_size = dma_get_max_seg_size(dev);
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if (max_seg_size < host->mmc->max_seg_size)
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host->mmc->max_seg_size = max_seg_size;
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}
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}
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/*
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* This is used in __devinit or __devexit so inline it
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* so it can be discarded.
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*/
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static inline void mmci_dma_release(struct mmci_host *host)
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{
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struct mmci_platform_data *plat = host->plat;
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if (host->dma_rx_channel)
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dma_release_channel(host->dma_rx_channel);
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if (host->dma_tx_channel && plat->dma_tx_param)
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dma_release_channel(host->dma_tx_channel);
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host->dma_rx_channel = host->dma_tx_channel = NULL;
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}
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static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
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{
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struct dma_chan *chan = host->dma_current;
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enum dma_data_direction dir;
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u32 status;
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int i;
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/* Wait up to 1ms for the DMA to complete */
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for (i = 0; ; i++) {
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status = readl(host->base + MMCISTATUS);
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if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
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break;
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udelay(10);
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}
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/*
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* Check to see whether we still have some data left in the FIFO -
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* this catches DMA controllers which are unable to monitor the
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* DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
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* contiguous buffers. On TX, we'll get a FIFO underrun error.
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*/
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if (status & MCI_RXDATAAVLBLMASK) {
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dmaengine_terminate_all(chan);
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if (!data->error)
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data->error = -EIO;
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}
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if (data->flags & MMC_DATA_WRITE) {
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dir = DMA_TO_DEVICE;
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} else {
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dir = DMA_FROM_DEVICE;
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}
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dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
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/*
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* Use of DMA with scatter-gather is impossible.
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* Give up with DMA and switch back to PIO mode.
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*/
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if (status & MCI_RXDATAAVLBLMASK) {
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dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
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mmci_dma_release(host);
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}
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}
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static void mmci_dma_data_error(struct mmci_host *host)
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{
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dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
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dmaengine_terminate_all(host->dma_current);
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}
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static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
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{
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struct variant_data *variant = host->variant;
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struct dma_slave_config conf = {
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.src_addr = host->phybase + MMCIFIFO,
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.dst_addr = host->phybase + MMCIFIFO,
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.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.src_maxburst = variant->fifohalfsize >> 2, /* # of words */
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.dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
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};
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struct mmc_data *data = host->data;
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struct dma_chan *chan;
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struct dma_device *device;
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struct dma_async_tx_descriptor *desc;
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int nr_sg;
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host->dma_current = NULL;
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if (data->flags & MMC_DATA_READ) {
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conf.direction = DMA_FROM_DEVICE;
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chan = host->dma_rx_channel;
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} else {
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conf.direction = DMA_TO_DEVICE;
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chan = host->dma_tx_channel;
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}
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/* If there's no DMA channel, fall back to PIO */
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if (!chan)
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return -EINVAL;
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/* If less than or equal to the fifo size, don't bother with DMA */
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if (host->size <= variant->fifosize)
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return -EINVAL;
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device = chan->device;
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nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction);
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if (nr_sg == 0)
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return -EINVAL;
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dmaengine_slave_config(chan, &conf);
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desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
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conf.direction, DMA_CTRL_ACK);
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if (!desc)
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goto unmap_exit;
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/* Okay, go for it. */
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host->dma_current = chan;
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dev_vdbg(mmc_dev(host->mmc),
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"Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
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data->sg_len, data->blksz, data->blocks, data->flags);
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dmaengine_submit(desc);
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dma_async_issue_pending(chan);
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datactrl |= MCI_DPSM_DMAENABLE;
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/* Trigger the DMA transfer */
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writel(datactrl, host->base + MMCIDATACTRL);
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/*
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* Let the MMCI say when the data is ended and it's time
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* to fire next DMA request. When that happens, MMCI will
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* call mmci_data_end()
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*/
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writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
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host->base + MMCIMASK0);
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return 0;
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unmap_exit:
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dmaengine_terminate_all(chan);
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dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction);
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return -ENOMEM;
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}
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#else
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/* Blank functions if the DMA engine is not available */
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static inline void mmci_dma_setup(struct mmci_host *host)
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{
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}
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static inline void mmci_dma_release(struct mmci_host *host)
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{
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}
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static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
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{
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}
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static inline void mmci_dma_data_error(struct mmci_host *host)
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{
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}
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static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
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{
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return -ENOSYS;
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}
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#endif
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static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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{
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struct variant_data *variant = host->variant;
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@ -202,9 +443,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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host->data = data;
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host->size = data->blksz * data->blocks;
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host->data_xfered = 0;
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mmci_init_sg(host, data);
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data->bytes_xfered = 0;
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clks = (unsigned long long)data->timeout_ns * host->cclk;
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do_div(clks, 1000000000UL);
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@ -219,15 +458,29 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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BUG_ON(1 << blksz_bits != data->blksz);
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datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
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if (data->flags & MMC_DATA_READ) {
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if (data->flags & MMC_DATA_READ)
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datactrl |= MCI_DPSM_DIRECTION;
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/*
|
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* Attempt to use DMA operation mode, if this
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* should fail, fall back to PIO mode
|
||||
*/
|
||||
if (!mmci_dma_start_data(host, datactrl))
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return;
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|
||||
/* IRQ mode, map the SG list for CPU reading/writing */
|
||||
mmci_init_sg(host, data);
|
||||
|
||||
if (data->flags & MMC_DATA_READ) {
|
||||
irqmask = MCI_RXFIFOHALFFULLMASK;
|
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|
||||
/*
|
||||
* If we have less than a FIFOSIZE of bytes to transfer,
|
||||
* trigger a PIO interrupt as soon as any data is available.
|
||||
* If we have less than the fifo 'half-full' threshold to
|
||||
* transfer, trigger a PIO interrupt as soon as any data
|
||||
* is available.
|
||||
*/
|
||||
if (host->size < variant->fifosize)
|
||||
if (host->size < variant->fifohalfsize)
|
||||
irqmask |= MCI_RXDATAAVLBLMASK;
|
||||
} else {
|
||||
/*
|
||||
|
|
@ -283,49 +536,51 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
|
|||
if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
|
||||
u32 remain, success;
|
||||
|
||||
/* Calculate how far we are into the transfer */
|
||||
/* Terminate the DMA transfer */
|
||||
if (dma_inprogress(host))
|
||||
mmci_dma_data_error(host);
|
||||
|
||||
/*
|
||||
* Calculate how far we are into the transfer. Note that
|
||||
* the data counter gives the number of bytes transferred
|
||||
* on the MMC bus, not on the host side. On reads, this
|
||||
* can be as much as a FIFO-worth of data ahead. This
|
||||
* matters for FIFO overruns only.
|
||||
*/
|
||||
remain = readl(host->base + MMCIDATACNT);
|
||||
success = data->blksz * data->blocks - remain;
|
||||
|
||||
dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
|
||||
dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
|
||||
status, success);
|
||||
if (status & MCI_DATACRCFAIL) {
|
||||
/* Last block was not successful */
|
||||
host->data_xfered = round_down(success - 1, data->blksz);
|
||||
success -= 1;
|
||||
data->error = -EILSEQ;
|
||||
} else if (status & MCI_DATATIMEOUT) {
|
||||
host->data_xfered = round_down(success, data->blksz);
|
||||
data->error = -ETIMEDOUT;
|
||||
} else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
|
||||
host->data_xfered = round_down(success, data->blksz);
|
||||
} else if (status & MCI_TXUNDERRUN) {
|
||||
data->error = -EIO;
|
||||
} else if (status & MCI_RXOVERRUN) {
|
||||
if (success > host->variant->fifosize)
|
||||
success -= host->variant->fifosize;
|
||||
else
|
||||
success = 0;
|
||||
data->error = -EIO;
|
||||
}
|
||||
|
||||
/*
|
||||
* We hit an error condition. Ensure that any data
|
||||
* partially written to a page is properly coherent.
|
||||
*/
|
||||
if (data->flags & MMC_DATA_READ) {
|
||||
struct sg_mapping_iter *sg_miter = &host->sg_miter;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (sg_miter_next(sg_miter)) {
|
||||
flush_dcache_page(sg_miter->page);
|
||||
sg_miter_stop(sg_miter);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
data->bytes_xfered = round_down(success, data->blksz);
|
||||
}
|
||||
|
||||
if (status & MCI_DATABLOCKEND)
|
||||
dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
|
||||
|
||||
if (status & MCI_DATAEND || data->error) {
|
||||
if (dma_inprogress(host))
|
||||
mmci_dma_unmap(host, data);
|
||||
mmci_stop_data(host);
|
||||
|
||||
if (!data->error)
|
||||
/* The error clause is handled above, success! */
|
||||
host->data_xfered += data->blksz * data->blocks;
|
||||
data->bytes_xfered = data->blksz * data->blocks;
|
||||
|
||||
if (!data->stop) {
|
||||
mmci_request_end(host, data->mrq);
|
||||
|
|
@ -498,9 +753,6 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
|
|||
if (remain)
|
||||
break;
|
||||
|
||||
if (status & MCI_RXACTIVE)
|
||||
flush_dcache_page(sg_miter->page);
|
||||
|
||||
status = readl(base + MMCISTATUS);
|
||||
} while (1);
|
||||
|
||||
|
|
@ -509,10 +761,10 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
|
|||
local_irq_restore(flags);
|
||||
|
||||
/*
|
||||
* If we're nearing the end of the read, switch to
|
||||
* "any data available" mode.
|
||||
* If we have less than the fifo 'half-full' threshold to transfer,
|
||||
* trigger a PIO interrupt as soon as any data is available.
|
||||
*/
|
||||
if (status & MCI_RXACTIVE && host->size < variant->fifosize)
|
||||
if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
|
||||
mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
|
||||
|
||||
/*
|
||||
|
|
@ -713,7 +965,8 @@ static const struct mmc_host_ops mmci_ops = {
|
|||
.get_cd = mmci_get_cd,
|
||||
};
|
||||
|
||||
static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
|
||||
static int __devinit mmci_probe(struct amba_device *dev,
|
||||
const struct amba_id *id)
|
||||
{
|
||||
struct mmci_platform_data *plat = dev->dev.platform_data;
|
||||
struct variant_data *variant = id->data;
|
||||
|
|
@ -776,6 +1029,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
|
|||
dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
|
||||
host->mclk);
|
||||
}
|
||||
host->phybase = dev->res.start;
|
||||
host->base = ioremap(dev->res.start, resource_size(&dev->res));
|
||||
if (!host->base) {
|
||||
ret = -ENOMEM;
|
||||
|
|
@ -903,9 +1157,12 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
|
|||
|
||||
amba_set_drvdata(dev, mmc);
|
||||
|
||||
dev_info(&dev->dev, "%s: PL%03x rev%u at 0x%08llx irq %d,%d\n",
|
||||
mmc_hostname(mmc), amba_part(dev), amba_rev(dev),
|
||||
(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
|
||||
dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
|
||||
mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
|
||||
amba_rev(dev), (unsigned long long)dev->res.start,
|
||||
dev->irq[0], dev->irq[1]);
|
||||
|
||||
mmci_dma_setup(host);
|
||||
|
||||
mmc_add_host(mmc);
|
||||
|
||||
|
|
@ -952,6 +1209,7 @@ static int __devexit mmci_remove(struct amba_device *dev)
|
|||
writel(0, host->base + MMCICOMMAND);
|
||||
writel(0, host->base + MMCIDATACTRL);
|
||||
|
||||
mmci_dma_release(host);
|
||||
free_irq(dev->irq[0], host);
|
||||
if (!host->singleirq)
|
||||
free_irq(dev->irq[1], host);
|
||||
|
|
|
|||
|
|
@ -148,8 +148,10 @@
|
|||
|
||||
struct clk;
|
||||
struct variant_data;
|
||||
struct dma_chan;
|
||||
|
||||
struct mmci_host {
|
||||
phys_addr_t phybase;
|
||||
void __iomem *base;
|
||||
struct mmc_request *mrq;
|
||||
struct mmc_command *cmd;
|
||||
|
|
@ -161,8 +163,6 @@ struct mmci_host {
|
|||
int gpio_cd_irq;
|
||||
bool singleirq;
|
||||
|
||||
unsigned int data_xfered;
|
||||
|
||||
spinlock_t lock;
|
||||
|
||||
unsigned int mclk;
|
||||
|
|
@ -181,5 +181,16 @@ struct mmci_host {
|
|||
struct sg_mapping_iter sg_miter;
|
||||
unsigned int size;
|
||||
struct regulator *vcc;
|
||||
|
||||
#ifdef CONFIG_DMA_ENGINE
|
||||
/* DMA stuff */
|
||||
struct dma_chan *dma_current;
|
||||
struct dma_chan *dma_rx_channel;
|
||||
struct dma_chan *dma_tx_channel;
|
||||
|
||||
#define dma_inprogress(host) ((host)->dma_current)
|
||||
#else
|
||||
#define dma_inprogress(host) (0)
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue