mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
Merge branches 'defcfg', 'drivers' and 'cyberpro-next' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'defcfg' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6647/1: add Versatile Express defconfig ARM: 6644/1: mach-ux500: update the U8500 defconfig * 'drivers' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6764/1: pl011: factor out FIFO to TTY code ARM: 6763/1: pl011: add optional RX DMA to PL011 v2 ARM: 6758/1: amba: support pm ops ARM: amba: make amba_driver id_table const ARM: amba: make internal ID table handling const ARM: amba: make probe() functions take const id tables ARM: 6662/1: amba: make amba_bustype non-static ARM: mmci: add dmaengine-based DMA support ARM: mmci: no need for separate host->data_xfered ARM: mmci: avoid unnecessary switch to data available PIO interrupts ARM: mmci: no need to call flush_dcache_page() with sg_miter API ARM: mmci: avoid reporting too many completed bytes on fifo overrun ALSA: AACI: make fifo variables more explanitory ALSA: AACI: no need to call snd_pcm_period_elapsed() for each period ALSA: AACI: use snd_pcm_lib_period_bytes() ALSA: AACI: clean up AACI announcement printk ALSA: AACI: fix channel mask selection ALSA: AACI: fix number of channels for record ALSA: AACI: fix multiple IRQ claiming * 'cyberpro-next' of master.kernel.org:/home/rmk/linux-2.6-arm: VIDEO: cyberpro: remove unused cyber2000fb_get_fb_var() VIDEO: cyberpro: remove useless function extreg pointers VIDEO: cyberpro: update handling of device structures VIDEO: cyberpro: add support for video capture I2C VIDEO: cyberpro: make 'reg_b0_lock' always present VIDEO: cyberpro: add I2C support VIDEO: cyberpro: select lowest multipler/divisor for PLL
This commit is contained in:
Linus Torvalds
commit
6d7ed21d17
25 changed files with 1710 additions and 356 deletions
|
|
@ -676,7 +676,7 @@ static struct uart_driver amba_reg = {
|
|||
.cons = AMBA_CONSOLE,
|
||||
};
|
||||
|
||||
static int pl010_probe(struct amba_device *dev, struct amba_id *id)
|
||||
static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
|
||||
{
|
||||
struct uart_amba_port *uap;
|
||||
void __iomem *base;
|
||||
|
|
|
|||
|
|
@ -96,6 +96,22 @@ static struct vendor_data vendor_st = {
|
|||
};
|
||||
|
||||
/* Deals with DMA transactions */
|
||||
|
||||
struct pl011_sgbuf {
|
||||
struct scatterlist sg;
|
||||
char *buf;
|
||||
};
|
||||
|
||||
struct pl011_dmarx_data {
|
||||
struct dma_chan *chan;
|
||||
struct completion complete;
|
||||
bool use_buf_b;
|
||||
struct pl011_sgbuf sgbuf_a;
|
||||
struct pl011_sgbuf sgbuf_b;
|
||||
dma_cookie_t cookie;
|
||||
bool running;
|
||||
};
|
||||
|
||||
struct pl011_dmatx_data {
|
||||
struct dma_chan *chan;
|
||||
struct scatterlist sg;
|
||||
|
|
@ -120,11 +136,69 @@ struct uart_amba_port {
|
|||
char type[12];
|
||||
#ifdef CONFIG_DMA_ENGINE
|
||||
/* DMA stuff */
|
||||
bool using_dma;
|
||||
bool using_tx_dma;
|
||||
bool using_rx_dma;
|
||||
struct pl011_dmarx_data dmarx;
|
||||
struct pl011_dmatx_data dmatx;
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Reads up to 256 characters from the FIFO or until it's empty and
|
||||
* inserts them into the TTY layer. Returns the number of characters
|
||||
* read from the FIFO.
|
||||
*/
|
||||
static int pl011_fifo_to_tty(struct uart_amba_port *uap)
|
||||
{
|
||||
u16 status, ch;
|
||||
unsigned int flag, max_count = 256;
|
||||
int fifotaken = 0;
|
||||
|
||||
while (max_count--) {
|
||||
status = readw(uap->port.membase + UART01x_FR);
|
||||
if (status & UART01x_FR_RXFE)
|
||||
break;
|
||||
|
||||
/* Take chars from the FIFO and update status */
|
||||
ch = readw(uap->port.membase + UART01x_DR) |
|
||||
UART_DUMMY_DR_RX;
|
||||
flag = TTY_NORMAL;
|
||||
uap->port.icount.rx++;
|
||||
fifotaken++;
|
||||
|
||||
if (unlikely(ch & UART_DR_ERROR)) {
|
||||
if (ch & UART011_DR_BE) {
|
||||
ch &= ~(UART011_DR_FE | UART011_DR_PE);
|
||||
uap->port.icount.brk++;
|
||||
if (uart_handle_break(&uap->port))
|
||||
continue;
|
||||
} else if (ch & UART011_DR_PE)
|
||||
uap->port.icount.parity++;
|
||||
else if (ch & UART011_DR_FE)
|
||||
uap->port.icount.frame++;
|
||||
if (ch & UART011_DR_OE)
|
||||
uap->port.icount.overrun++;
|
||||
|
||||
ch &= uap->port.read_status_mask;
|
||||
|
||||
if (ch & UART011_DR_BE)
|
||||
flag = TTY_BREAK;
|
||||
else if (ch & UART011_DR_PE)
|
||||
flag = TTY_PARITY;
|
||||
else if (ch & UART011_DR_FE)
|
||||
flag = TTY_FRAME;
|
||||
}
|
||||
|
||||
if (uart_handle_sysrq_char(&uap->port, ch & 255))
|
||||
continue;
|
||||
|
||||
uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
|
||||
}
|
||||
|
||||
return fifotaken;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* All the DMA operation mode stuff goes inside this ifdef.
|
||||
* This assumes that you have a generic DMA device interface,
|
||||
|
|
@ -134,6 +208,31 @@ struct uart_amba_port {
|
|||
|
||||
#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
|
||||
|
||||
static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
|
||||
if (!sg->buf)
|
||||
return -ENOMEM;
|
||||
|
||||
sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
|
||||
|
||||
if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
|
||||
kfree(sg->buf);
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
if (sg->buf) {
|
||||
dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
|
||||
kfree(sg->buf);
|
||||
}
|
||||
}
|
||||
|
||||
static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
|
||||
{
|
||||
/* DMA is the sole user of the platform data right now */
|
||||
|
|
@ -153,7 +252,7 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
|
|||
return;
|
||||
}
|
||||
|
||||
/* Try to acquire a generic DMA engine slave channel */
|
||||
/* Try to acquire a generic DMA engine slave TX channel */
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(DMA_SLAVE, mask);
|
||||
|
||||
|
|
@ -168,6 +267,28 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
|
|||
|
||||
dev_info(uap->port.dev, "DMA channel TX %s\n",
|
||||
dma_chan_name(uap->dmatx.chan));
|
||||
|
||||
/* Optionally make use of an RX channel as well */
|
||||
if (plat->dma_rx_param) {
|
||||
struct dma_slave_config rx_conf = {
|
||||
.src_addr = uap->port.mapbase + UART01x_DR,
|
||||
.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
|
||||
.direction = DMA_FROM_DEVICE,
|
||||
.src_maxburst = uap->fifosize >> 1,
|
||||
};
|
||||
|
||||
chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
|
||||
if (!chan) {
|
||||
dev_err(uap->port.dev, "no RX DMA channel!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
dmaengine_slave_config(chan, &rx_conf);
|
||||
uap->dmarx.chan = chan;
|
||||
|
||||
dev_info(uap->port.dev, "DMA channel RX %s\n",
|
||||
dma_chan_name(uap->dmarx.chan));
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef MODULE
|
||||
|
|
@ -219,9 +340,10 @@ static void pl011_dma_remove(struct uart_amba_port *uap)
|
|||
/* TODO: remove the initcall if it has not yet executed */
|
||||
if (uap->dmatx.chan)
|
||||
dma_release_channel(uap->dmatx.chan);
|
||||
if (uap->dmarx.chan)
|
||||
dma_release_channel(uap->dmarx.chan);
|
||||
}
|
||||
|
||||
|
||||
/* Forward declare this for the refill routine */
|
||||
static int pl011_dma_tx_refill(struct uart_amba_port *uap);
|
||||
|
||||
|
|
@ -380,7 +502,7 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap)
|
|||
*/
|
||||
static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
|
||||
{
|
||||
if (!uap->using_dma)
|
||||
if (!uap->using_tx_dma)
|
||||
return false;
|
||||
|
||||
/*
|
||||
|
|
@ -432,7 +554,7 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
|
|||
{
|
||||
u16 dmacr;
|
||||
|
||||
if (!uap->using_dma)
|
||||
if (!uap->using_tx_dma)
|
||||
return false;
|
||||
|
||||
if (!uap->port.x_char) {
|
||||
|
|
@ -492,7 +614,7 @@ static void pl011_dma_flush_buffer(struct uart_port *port)
|
|||
{
|
||||
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||
|
||||
if (!uap->using_dma)
|
||||
if (!uap->using_tx_dma)
|
||||
return;
|
||||
|
||||
/* Avoid deadlock with the DMA engine callback */
|
||||
|
|
@ -508,9 +630,219 @@ static void pl011_dma_flush_buffer(struct uart_port *port)
|
|||
}
|
||||
}
|
||||
|
||||
static void pl011_dma_rx_callback(void *data);
|
||||
|
||||
static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
|
||||
{
|
||||
struct dma_chan *rxchan = uap->dmarx.chan;
|
||||
struct dma_device *dma_dev;
|
||||
struct pl011_dmarx_data *dmarx = &uap->dmarx;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
struct pl011_sgbuf *sgbuf;
|
||||
|
||||
if (!rxchan)
|
||||
return -EIO;
|
||||
|
||||
/* Start the RX DMA job */
|
||||
sgbuf = uap->dmarx.use_buf_b ?
|
||||
&uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
|
||||
dma_dev = rxchan->device;
|
||||
desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1,
|
||||
DMA_FROM_DEVICE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
/*
|
||||
* If the DMA engine is busy and cannot prepare a
|
||||
* channel, no big deal, the driver will fall back
|
||||
* to interrupt mode as a result of this error code.
|
||||
*/
|
||||
if (!desc) {
|
||||
uap->dmarx.running = false;
|
||||
dmaengine_terminate_all(rxchan);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Some data to go along to the callback */
|
||||
desc->callback = pl011_dma_rx_callback;
|
||||
desc->callback_param = uap;
|
||||
dmarx->cookie = dmaengine_submit(desc);
|
||||
dma_async_issue_pending(rxchan);
|
||||
|
||||
uap->dmacr |= UART011_RXDMAE;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
uap->dmarx.running = true;
|
||||
|
||||
uap->im &= ~UART011_RXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is called when either the DMA job is complete, or
|
||||
* the FIFO timeout interrupt occurred. This must be called
|
||||
* with the port spinlock uap->port.lock held.
|
||||
*/
|
||||
static void pl011_dma_rx_chars(struct uart_amba_port *uap,
|
||||
u32 pending, bool use_buf_b,
|
||||
bool readfifo)
|
||||
{
|
||||
struct tty_struct *tty = uap->port.state->port.tty;
|
||||
struct pl011_sgbuf *sgbuf = use_buf_b ?
|
||||
&uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
|
||||
struct device *dev = uap->dmarx.chan->device->dev;
|
||||
int dma_count = 0;
|
||||
u32 fifotaken = 0; /* only used for vdbg() */
|
||||
|
||||
/* Pick everything from the DMA first */
|
||||
if (pending) {
|
||||
/* Sync in buffer */
|
||||
dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
|
||||
|
||||
/*
|
||||
* First take all chars in the DMA pipe, then look in the FIFO.
|
||||
* Note that tty_insert_flip_buf() tries to take as many chars
|
||||
* as it can.
|
||||
*/
|
||||
dma_count = tty_insert_flip_string(uap->port.state->port.tty,
|
||||
sgbuf->buf, pending);
|
||||
|
||||
/* Return buffer to device */
|
||||
dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
|
||||
|
||||
uap->port.icount.rx += dma_count;
|
||||
if (dma_count < pending)
|
||||
dev_warn(uap->port.dev,
|
||||
"couldn't insert all characters (TTY is full?)\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Only continue with trying to read the FIFO if all DMA chars have
|
||||
* been taken first.
|
||||
*/
|
||||
if (dma_count == pending && readfifo) {
|
||||
/* Clear any error flags */
|
||||
writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
|
||||
uap->port.membase + UART011_ICR);
|
||||
|
||||
/*
|
||||
* If we read all the DMA'd characters, and we had an
|
||||
* incomplete buffer, that could be due to an rx error, or
|
||||
* maybe we just timed out. Read any pending chars and check
|
||||
* the error status.
|
||||
*
|
||||
* Error conditions will only occur in the FIFO, these will
|
||||
* trigger an immediate interrupt and stop the DMA job, so we
|
||||
* will always find the error in the FIFO, never in the DMA
|
||||
* buffer.
|
||||
*/
|
||||
fifotaken = pl011_fifo_to_tty(uap);
|
||||
}
|
||||
|
||||
spin_unlock(&uap->port.lock);
|
||||
dev_vdbg(uap->port.dev,
|
||||
"Took %d chars from DMA buffer and %d chars from the FIFO\n",
|
||||
dma_count, fifotaken);
|
||||
tty_flip_buffer_push(tty);
|
||||
spin_lock(&uap->port.lock);
|
||||
}
|
||||
|
||||
static void pl011_dma_rx_irq(struct uart_amba_port *uap)
|
||||
{
|
||||
struct pl011_dmarx_data *dmarx = &uap->dmarx;
|
||||
struct dma_chan *rxchan = dmarx->chan;
|
||||
struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
|
||||
&dmarx->sgbuf_b : &dmarx->sgbuf_a;
|
||||
size_t pending;
|
||||
struct dma_tx_state state;
|
||||
enum dma_status dmastat;
|
||||
|
||||
/*
|
||||
* Pause the transfer so we can trust the current counter,
|
||||
* do this before we pause the PL011 block, else we may
|
||||
* overflow the FIFO.
|
||||
*/
|
||||
if (dmaengine_pause(rxchan))
|
||||
dev_err(uap->port.dev, "unable to pause DMA transfer\n");
|
||||
dmastat = rxchan->device->device_tx_status(rxchan,
|
||||
dmarx->cookie, &state);
|
||||
if (dmastat != DMA_PAUSED)
|
||||
dev_err(uap->port.dev, "unable to pause DMA transfer\n");
|
||||
|
||||
/* Disable RX DMA - incoming data will wait in the FIFO */
|
||||
uap->dmacr &= ~UART011_RXDMAE;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
uap->dmarx.running = false;
|
||||
|
||||
pending = sgbuf->sg.length - state.residue;
|
||||
BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
|
||||
/* Then we terminate the transfer - we now know our residue */
|
||||
dmaengine_terminate_all(rxchan);
|
||||
|
||||
/*
|
||||
* This will take the chars we have so far and insert
|
||||
* into the framework.
|
||||
*/
|
||||
pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
|
||||
|
||||
/* Switch buffer & re-trigger DMA job */
|
||||
dmarx->use_buf_b = !dmarx->use_buf_b;
|
||||
if (pl011_dma_rx_trigger_dma(uap)) {
|
||||
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
|
||||
"fall back to interrupt mode\n");
|
||||
uap->im |= UART011_RXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
}
|
||||
}
|
||||
|
||||
static void pl011_dma_rx_callback(void *data)
|
||||
{
|
||||
struct uart_amba_port *uap = data;
|
||||
struct pl011_dmarx_data *dmarx = &uap->dmarx;
|
||||
bool lastbuf = dmarx->use_buf_b;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* This completion interrupt occurs typically when the
|
||||
* RX buffer is totally stuffed but no timeout has yet
|
||||
* occurred. When that happens, we just want the RX
|
||||
* routine to flush out the secondary DMA buffer while
|
||||
* we immediately trigger the next DMA job.
|
||||
*/
|
||||
spin_lock_irq(&uap->port.lock);
|
||||
uap->dmarx.running = false;
|
||||
dmarx->use_buf_b = !lastbuf;
|
||||
ret = pl011_dma_rx_trigger_dma(uap);
|
||||
|
||||
pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false);
|
||||
spin_unlock_irq(&uap->port.lock);
|
||||
/*
|
||||
* Do this check after we picked the DMA chars so we don't
|
||||
* get some IRQ immediately from RX.
|
||||
*/
|
||||
if (ret) {
|
||||
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
|
||||
"fall back to interrupt mode\n");
|
||||
uap->im |= UART011_RXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop accepting received characters, when we're shutting down or
|
||||
* suspending this port.
|
||||
* Locking: called with port lock held and IRQs disabled.
|
||||
*/
|
||||
static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
|
||||
{
|
||||
/* FIXME. Just disable the DMA enable */
|
||||
uap->dmacr &= ~UART011_RXDMAE;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
}
|
||||
|
||||
static void pl011_dma_startup(struct uart_amba_port *uap)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!uap->dmatx.chan)
|
||||
return;
|
||||
|
||||
|
|
@ -525,8 +857,33 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
|
|||
|
||||
/* The DMA buffer is now the FIFO the TTY subsystem can use */
|
||||
uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
|
||||
uap->using_dma = true;
|
||||
uap->using_tx_dma = true;
|
||||
|
||||
if (!uap->dmarx.chan)
|
||||
goto skip_rx;
|
||||
|
||||
/* Allocate and map DMA RX buffers */
|
||||
ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
|
||||
DMA_FROM_DEVICE);
|
||||
if (ret) {
|
||||
dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
|
||||
"RX buffer A", ret);
|
||||
goto skip_rx;
|
||||
}
|
||||
|
||||
ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
|
||||
DMA_FROM_DEVICE);
|
||||
if (ret) {
|
||||
dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
|
||||
"RX buffer B", ret);
|
||||
pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
|
||||
DMA_FROM_DEVICE);
|
||||
goto skip_rx;
|
||||
}
|
||||
|
||||
uap->using_rx_dma = true;
|
||||
|
||||
skip_rx:
|
||||
/* Turn on DMA error (RX/TX will be enabled on demand) */
|
||||
uap->dmacr |= UART011_DMAONERR;
|
||||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
|
|
@ -539,11 +896,17 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
|
|||
if (uap->vendor->dma_threshold)
|
||||
writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
|
||||
uap->port.membase + ST_UART011_DMAWM);
|
||||
|
||||
if (uap->using_rx_dma) {
|
||||
if (pl011_dma_rx_trigger_dma(uap))
|
||||
dev_dbg(uap->port.dev, "could not trigger initial "
|
||||
"RX DMA job, fall back to interrupt mode\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void pl011_dma_shutdown(struct uart_amba_port *uap)
|
||||
{
|
||||
if (!uap->using_dma)
|
||||
if (!(uap->using_tx_dma || uap->using_rx_dma))
|
||||
return;
|
||||
|
||||
/* Disable RX and TX DMA */
|
||||
|
|
@ -555,19 +918,39 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
|
|||
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
||||
spin_unlock_irq(&uap->port.lock);
|
||||
|
||||
/* In theory, this should already be done by pl011_dma_flush_buffer */
|
||||
dmaengine_terminate_all(uap->dmatx.chan);
|
||||
if (uap->dmatx.queued) {
|
||||
dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
|
||||
DMA_TO_DEVICE);
|
||||
uap->dmatx.queued = false;
|
||||
if (uap->using_tx_dma) {
|
||||
/* In theory, this should already be done by pl011_dma_flush_buffer */
|
||||
dmaengine_terminate_all(uap->dmatx.chan);
|
||||
if (uap->dmatx.queued) {
|
||||
dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
|
||||
DMA_TO_DEVICE);
|
||||
uap->dmatx.queued = false;
|
||||
}
|
||||
|
||||
kfree(uap->dmatx.buf);
|
||||
uap->using_tx_dma = false;
|
||||
}
|
||||
|
||||
kfree(uap->dmatx.buf);
|
||||
|
||||
uap->using_dma = false;
|
||||
if (uap->using_rx_dma) {
|
||||
dmaengine_terminate_all(uap->dmarx.chan);
|
||||
/* Clean up the RX DMA */
|
||||
pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
|
||||
pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
|
||||
uap->using_rx_dma = false;
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
|
||||
{
|
||||
return uap->using_rx_dma;
|
||||
}
|
||||
|
||||
static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
|
||||
{
|
||||
return uap->using_rx_dma && uap->dmarx.running;
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
/* Blank functions if the DMA engine is not available */
|
||||
static inline void pl011_dma_probe(struct uart_amba_port *uap)
|
||||
|
|
@ -600,6 +983,29 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
|
|||
return false;
|
||||
}
|
||||
|
||||
static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#define pl011_dma_flush_buffer NULL
|
||||
#endif
|
||||
|
||||
|
|
@ -630,6 +1036,8 @@ static void pl011_stop_rx(struct uart_port *port)
|
|||
uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
|
||||
UART011_PEIM|UART011_BEIM|UART011_OEIM);
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
|
||||
pl011_dma_rx_stop(uap);
|
||||
}
|
||||
|
||||
static void pl011_enable_ms(struct uart_port *port)
|
||||
|
|
@ -643,51 +1051,24 @@ static void pl011_enable_ms(struct uart_port *port)
|
|||
static void pl011_rx_chars(struct uart_amba_port *uap)
|
||||
{
|
||||
struct tty_struct *tty = uap->port.state->port.tty;
|
||||
unsigned int status, ch, flag, max_count = 256;
|
||||
|
||||
status = readw(uap->port.membase + UART01x_FR);
|
||||
while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
|
||||
ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
|
||||
flag = TTY_NORMAL;
|
||||
uap->port.icount.rx++;
|
||||
pl011_fifo_to_tty(uap);
|
||||
|
||||
/*
|
||||
* Note that the error handling code is
|
||||
* out of the main execution path
|
||||
*/
|
||||
if (unlikely(ch & UART_DR_ERROR)) {
|
||||
if (ch & UART011_DR_BE) {
|
||||
ch &= ~(UART011_DR_FE | UART011_DR_PE);
|
||||
uap->port.icount.brk++;
|
||||
if (uart_handle_break(&uap->port))
|
||||
goto ignore_char;
|
||||
} else if (ch & UART011_DR_PE)
|
||||
uap->port.icount.parity++;
|
||||
else if (ch & UART011_DR_FE)
|
||||
uap->port.icount.frame++;
|
||||
if (ch & UART011_DR_OE)
|
||||
uap->port.icount.overrun++;
|
||||
|
||||
ch &= uap->port.read_status_mask;
|
||||
|
||||
if (ch & UART011_DR_BE)
|
||||
flag = TTY_BREAK;
|
||||
else if (ch & UART011_DR_PE)
|
||||
flag = TTY_PARITY;
|
||||
else if (ch & UART011_DR_FE)
|
||||
flag = TTY_FRAME;
|
||||
}
|
||||
|
||||
if (uart_handle_sysrq_char(&uap->port, ch & 255))
|
||||
goto ignore_char;
|
||||
|
||||
uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
|
||||
|
||||
ignore_char:
|
||||
status = readw(uap->port.membase + UART01x_FR);
|
||||
}
|
||||
spin_unlock(&uap->port.lock);
|
||||
tty_flip_buffer_push(tty);
|
||||
/*
|
||||
* If we were temporarily out of DMA mode for a while,
|
||||
* attempt to switch back to DMA mode again.
|
||||
*/
|
||||
if (pl011_dma_rx_available(uap)) {
|
||||
if (pl011_dma_rx_trigger_dma(uap)) {
|
||||
dev_dbg(uap->port.dev, "could not trigger RX DMA job "
|
||||
"fall back to interrupt mode again\n");
|
||||
uap->im |= UART011_RXIM;
|
||||
} else
|
||||
uap->im &= ~UART011_RXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
}
|
||||
spin_lock(&uap->port.lock);
|
||||
}
|
||||
|
||||
|
|
@ -767,8 +1148,12 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
|
|||
UART011_RXIS),
|
||||
uap->port.membase + UART011_ICR);
|
||||
|
||||
if (status & (UART011_RTIS|UART011_RXIS))
|
||||
pl011_rx_chars(uap);
|
||||
if (status & (UART011_RTIS|UART011_RXIS)) {
|
||||
if (pl011_dma_rx_running(uap))
|
||||
pl011_dma_rx_irq(uap);
|
||||
else
|
||||
pl011_rx_chars(uap);
|
||||
}
|
||||
if (status & (UART011_DSRMIS|UART011_DCDMIS|
|
||||
UART011_CTSMIS|UART011_RIMIS))
|
||||
pl011_modem_status(uap);
|
||||
|
|
@ -945,10 +1330,14 @@ static int pl011_startup(struct uart_port *port)
|
|||
pl011_dma_startup(uap);
|
||||
|
||||
/*
|
||||
* Finally, enable interrupts
|
||||
* Finally, enable interrupts, only timeouts when using DMA
|
||||
* if initial RX DMA job failed, start in interrupt mode
|
||||
* as well.
|
||||
*/
|
||||
spin_lock_irq(&uap->port.lock);
|
||||
uap->im = UART011_RXIM | UART011_RTIM;
|
||||
uap->im = UART011_RTIM;
|
||||
if (!pl011_dma_rx_running(uap))
|
||||
uap->im |= UART011_RXIM;
|
||||
writew(uap->im, uap->port.membase + UART011_IMSC);
|
||||
spin_unlock_irq(&uap->port.lock);
|
||||
|
||||
|
|
@ -1349,7 +1738,7 @@ static struct uart_driver amba_reg = {
|
|||
.cons = AMBA_CONSOLE,
|
||||
};
|
||||
|
||||
static int pl011_probe(struct amba_device *dev, struct amba_id *id)
|
||||
static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
|
||||
{
|
||||
struct uart_amba_port *uap;
|
||||
struct vendor_data *vendor = id->data;
|
||||
|
|
|
|||
Loading…
Reference in a new issue