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Merge commit 'origin'

Browse source 
Manual fixup of conflicts on:

	arch/powerpc/include/asm/dcr-regs.h
	drivers/net/ibm_newemac/core.h
This commit is contained in:
Benjamin Herrenschmidt 2008-10-15 11:31:54 +11:00
commit 6dc6472581
5097 changed files with 278566 additions and 138302 deletions
Download patch file Download diff file Expand all files Collapse all files

3
include/linux/Kbuild
View file

@ -126,6 +126,7 @@ header-y += pci_regs.h
header-y += pfkeyv2.h
header-y += pg.h
header-y += phantom.h
header-y += phonet.h
header-y += pkt_cls.h
header-y += pkt_sched.h
header-y += posix_types.h
@ -180,6 +181,7 @@ unifdef-y += audit.h
unifdef-y += auto_fs.h
unifdef-y += auxvec.h
unifdef-y += binfmts.h
unifdef-y += blktrace_api.h
unifdef-y += capability.h
unifdef-y += capi.h
unifdef-y += cciss_ioctl.h
@ -232,6 +234,7 @@ unifdef-y += if_fddi.h
unifdef-y += if_frad.h
unifdef-y += if_ltalk.h
unifdef-y += if_link.h
unifdef-y += if_phonet.h
unifdef-y += if_pppol2tp.h
unifdef-y += if_pppox.h
unifdef-y += if_tr.h

129
include/linux/ata.h
View file

@ -30,6 +30,7 @@
#define __LINUX_ATA_H__
#include <linux/types.h>
#include <asm/byteorder.h>
/* defines only for the constants which don't work well as enums */
#define ATA_DMA_BOUNDARY 0xffffUL
@ -88,6 +89,7 @@ enum {
ATA_ID_DLF = 128,
ATA_ID_CSFO = 129,
ATA_ID_CFA_POWER = 160,
ATA_ID_ROT_SPEED = 217,
ATA_ID_PIO4 = (1 << 1),
ATA_ID_SERNO_LEN = 20,
@ -557,6 +559,15 @@ static inline int ata_id_has_flush(const u16 *id)
return id[ATA_ID_COMMAND_SET_2] & (1 << 12);
}
static inline int ata_id_flush_enabled(const u16 *id)
{
if (ata_id_has_flush(id) == 0)
return 0;
if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
return 0;
return id[ATA_ID_CFS_ENABLE_2] & (1 << 12);
}
static inline int ata_id_has_flush_ext(const u16 *id)
{
if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
@ -564,6 +575,19 @@ static inline int ata_id_has_flush_ext(const u16 *id)
return id[ATA_ID_COMMAND_SET_2] & (1 << 13);
}
static inline int ata_id_flush_ext_enabled(const u16 *id)
{
if (ata_id_has_flush_ext(id) == 0)
return 0;
if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
return 0;
/*
* some Maxtor disks have bit 13 defined incorrectly
* so check bit 10 too
*/
return (id[ATA_ID_CFS_ENABLE_2] & 0x2400) == 0x2400;
}
static inline int ata_id_has_lba48(const u16 *id)
{
if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
@ -573,6 +597,15 @@ static inline int ata_id_has_lba48(const u16 *id)
return id[ATA_ID_COMMAND_SET_2] & (1 << 10);
}
static inline int ata_id_lba48_enabled(const u16 *id)
{
if (ata_id_has_lba48(id) == 0)
return 0;
if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
return 0;
return id[ATA_ID_CFS_ENABLE_2] & (1 << 10);
}
static inline int ata_id_hpa_enabled(const u16 *id)
{
/* Yes children, word 83 valid bits cover word 82 data */
@ -644,7 +677,15 @@ static inline unsigned int ata_id_major_version(const u16 *id)
static inline int ata_id_is_sata(const u16 *id)
{
return ata_id_major_version(id) >= 5 && id[ATA_ID_HW_CONFIG] == 0;
/*
* See if word 93 is 0 AND drive is at least ATA-5 compatible
* verifying that word 80 by casting it to a signed type --
* this trick allows us to filter out the reserved values of
* 0x0000 and 0xffff along with the earlier ATA revisions...
*/
if (id[ATA_ID_HW_CONFIG] == 0 && (short)id[ATA_ID_MAJOR_VER] >= 0x0020)
return 1;
return 0;
}
static inline int ata_id_has_tpm(const u16 *id)
@ -667,6 +708,15 @@ static inline int ata_id_has_dword_io(const u16 *id)
return 0;
}
static inline int ata_id_has_unload(const u16 *id)
{
if (ata_id_major_version(id) >= 7 &&
(id[ATA_ID_CFSSE] & 0xC000) == 0x4000 &&
id[ATA_ID_CFSSE] & (1 << 13))
return 1;
return 0;
}
static inline int ata_id_current_chs_valid(const u16 *id)
{
/* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command
@ -691,6 +741,11 @@ static inline int ata_id_is_cfa(const u16 *id)
return 0;
}
static inline int ata_id_is_ssd(const u16 *id)
{
return id[ATA_ID_ROT_SPEED] == 0x01;
}
static inline int ata_drive_40wire(const u16 *dev_id)
{
if (ata_id_is_sata(dev_id))
@ -727,6 +782,76 @@ static inline int atapi_id_dmadir(const u16 *dev_id)
return ata_id_major_version(dev_id) >= 7 && (dev_id[62] & 0x8000);
}
/*
* ata_id_is_lba_capacity_ok() performs a sanity check on
* the claimed LBA capacity value for the device.
*
* Returns 1 if LBA capacity looks sensible, 0 otherwise.
*
* It is called only once for each device.
*/
static inline int ata_id_is_lba_capacity_ok(u16 *id)
{
unsigned long lba_sects, chs_sects, head, tail;
/* No non-LBA info .. so valid! */
if (id[ATA_ID_CYLS] == 0)
return 1;
lba_sects = ata_id_u32(id, ATA_ID_LBA_CAPACITY);
/*
* The ATA spec tells large drives to return
* C/H/S = 16383/16/63 independent of their size.
* Some drives can be jumpered to use 15 heads instead of 16.
* Some drives can be jumpered to use 4092 cyls instead of 16383.
*/
if ((id[ATA_ID_CYLS] == 16383 ||
(id[ATA_ID_CYLS] == 4092 && id[ATA_ID_CUR_CYLS] == 16383)) &&
id[ATA_ID_SECTORS] == 63 &&
(id[ATA_ID_HEADS] == 15 || id[ATA_ID_HEADS] == 16) &&
(lba_sects >= 16383 * 63 * id[ATA_ID_HEADS]))
return 1;
chs_sects = id[ATA_ID_CYLS] * id[ATA_ID_HEADS] * id[ATA_ID_SECTORS];
/* perform a rough sanity check on lba_sects: within 10% is OK */
if (lba_sects - chs_sects < chs_sects/10)
return 1;
/* some drives have the word order reversed */
head = (lba_sects >> 16) & 0xffff;
tail = lba_sects & 0xffff;
lba_sects = head | (tail << 16);
if (lba_sects - chs_sects < chs_sects/10) {
*(__le32 *)&id[ATA_ID_LBA_CAPACITY] = __cpu_to_le32(lba_sects);
return 1; /* LBA capacity is (now) good */
}
return 0; /* LBA capacity value may be bad */
}
static inline void ata_id_to_hd_driveid(u16 *id)
{
#ifdef __BIG_ENDIAN
/* accessed in struct hd_driveid as 8-bit values */
id[ATA_ID_MAX_MULTSECT] = __cpu_to_le16(id[ATA_ID_MAX_MULTSECT]);
id[ATA_ID_CAPABILITY] = __cpu_to_le16(id[ATA_ID_CAPABILITY]);
id[ATA_ID_OLD_PIO_MODES] = __cpu_to_le16(id[ATA_ID_OLD_PIO_MODES]);
id[ATA_ID_OLD_DMA_MODES] = __cpu_to_le16(id[ATA_ID_OLD_DMA_MODES]);
id[ATA_ID_MULTSECT] = __cpu_to_le16(id[ATA_ID_MULTSECT]);
/* as 32-bit values */
*(u32 *)&id[ATA_ID_LBA_CAPACITY] = ata_id_u32(id, ATA_ID_LBA_CAPACITY);
*(u32 *)&id[ATA_ID_SPG] = ata_id_u32(id, ATA_ID_SPG);
/* as 64-bit value */
*(u64 *)&id[ATA_ID_LBA_CAPACITY_2] =
ata_id_u64(id, ATA_ID_LBA_CAPACITY_2);
#endif
}
static inline int is_multi_taskfile(struct ata_taskfile *tf)
{
return (tf->command == ATA_CMD_READ_MULTI) ||
@ -745,7 +870,7 @@ static inline int ata_ok(u8 status)
static inline int lba_28_ok(u64 block, u32 n_block)
{
/* check the ending block number */
return ((block + n_block - 1) < ((u64)1 << 28)) && (n_block <= 256);
return ((block + n_block) < ((u64)1 << 28)) && (n_block <= 256);
}
static inline int lba_48_ok(u64 block, u32 n_block)

108
include/linux/bio.h
View file

@ -26,21 +26,8 @@
#ifdef CONFIG_BLOCK
/* Platforms may set this to teach the BIO layer about IOMMU hardware. */
#include <asm/io.h>
#if defined(BIO_VMERGE_MAX_SIZE) && defined(BIO_VMERGE_BOUNDARY)
#define BIOVEC_VIRT_START_SIZE(x) (bvec_to_phys(x) & (BIO_VMERGE_BOUNDARY - 1))
#define BIOVEC_VIRT_OVERSIZE(x) ((x) > BIO_VMERGE_MAX_SIZE)
#else
#define BIOVEC_VIRT_START_SIZE(x) 0
#define BIOVEC_VIRT_OVERSIZE(x) 0
#endif
#ifndef BIO_VMERGE_BOUNDARY
#define BIO_VMERGE_BOUNDARY 0
#endif
#define BIO_DEBUG
#ifdef BIO_DEBUG
@ -88,25 +75,14 @@ struct bio {
/* Number of segments in this BIO after
* physical address coalescing is performed.
*/
unsigned short bi_phys_segments;
/* Number of segments after physical and DMA remapping
* hardware coalescing is performed.
*/
unsigned short bi_hw_segments;
unsigned int bi_phys_segments;
unsigned int bi_size; /* residual I/O count */
/*
* To keep track of the max hw size, we account for the
* sizes of the first and last virtually mergeable segments
* in this bio
*/
unsigned int bi_hw_front_size;
unsigned int bi_hw_back_size;
unsigned int bi_max_vecs; /* max bvl_vecs we can hold */
unsigned int bi_comp_cpu; /* completion CPU */
struct bio_vec *bi_io_vec; /* the actual vec list */
bio_end_io_t *bi_end_io;
@ -126,11 +102,14 @@ struct bio {
#define BIO_UPTODATE 0 /* ok after I/O completion */
#define BIO_RW_BLOCK 1 /* RW_AHEAD set, and read/write would block */
#define BIO_EOF 2 /* out-out-bounds error */
#define BIO_SEG_VALID 3 /* nr_hw_seg valid */
#define BIO_SEG_VALID 3 /* bi_phys_segments valid */
#define BIO_CLONED 4 /* doesn't own data */
#define BIO_BOUNCED 5 /* bio is a bounce bio */
#define BIO_USER_MAPPED 6 /* contains user pages */
#define BIO_EOPNOTSUPP 7 /* not supported */
#define BIO_CPU_AFFINE 8 /* complete bio on same CPU as submitted */
#define BIO_NULL_MAPPED 9 /* contains invalid user pages */
#define BIO_FS_INTEGRITY 10 /* fs owns integrity data, not block layer */
#define bio_flagged(bio, flag) ((bio)->bi_flags & (1 << (flag)))
/*
@ -144,18 +123,31 @@ struct bio {
/*
* bio bi_rw flags
*
* bit 0 -- read (not set) or write (set)
* bit 0 -- data direction
* If not set, bio is a read from device. If set, it's a write to device.
* bit 1 -- rw-ahead when set
* bit 2 -- barrier
* Insert a serialization point in the IO queue, forcing previously
* submitted IO to be completed before this oen is issued.
* bit 3 -- fail fast, don't want low level driver retries
* bit 4 -- synchronous I/O hint: the block layer will unplug immediately
* Note that this does NOT indicate that the IO itself is sync, just
* that the block layer will not postpone issue of this IO by plugging.
* bit 5 -- metadata request
* Used for tracing to differentiate metadata and data IO. May also
* get some preferential treatment in the IO scheduler
* bit 6 -- discard sectors
* Informs the lower level device that this range of sectors is no longer
* used by the file system and may thus be freed by the device. Used
* for flash based storage.
*/
#define BIO_RW 0
#define BIO_RW_AHEAD 1
#define BIO_RW 0 /* Must match RW in req flags (blkdev.h) */
#define BIO_RW_AHEAD 1 /* Must match FAILFAST in req flags */
#define BIO_RW_BARRIER 2
#define BIO_RW_FAILFAST 3
#define BIO_RW_SYNC 4
#define BIO_RW_META 5
#define BIO_RW_DISCARD 6
/*
* upper 16 bits of bi_rw define the io priority of this bio
@ -185,14 +177,15 @@ struct bio {
#define bio_failfast(bio) ((bio)->bi_rw & (1 << BIO_RW_FAILFAST))
#define bio_rw_ahead(bio) ((bio)->bi_rw & (1 << BIO_RW_AHEAD))
#define bio_rw_meta(bio) ((bio)->bi_rw & (1 << BIO_RW_META))
#define bio_empty_barrier(bio) (bio_barrier(bio) && !(bio)->bi_size)
#define bio_discard(bio) ((bio)->bi_rw & (1 << BIO_RW_DISCARD))
#define bio_empty_barrier(bio) (bio_barrier(bio) && !bio_has_data(bio) && !bio_discard(bio))
static inline unsigned int bio_cur_sectors(struct bio *bio)
{
if (bio->bi_vcnt)
return bio_iovec(bio)->bv_len >> 9;
return 0;
else /* dataless requests such as discard */
return bio->bi_size >> 9;
}
static inline void *bio_data(struct bio *bio)
@ -236,8 +229,6 @@ static inline void *bio_data(struct bio *bio)
((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
#endif
#define BIOVEC_VIRT_MERGEABLE(vec1, vec2) \
((((bvec_to_phys((vec1)) + (vec1)->bv_len) | bvec_to_phys((vec2))) & (BIO_VMERGE_BOUNDARY - 1)) == 0)
#define __BIO_SEG_BOUNDARY(addr1, addr2, mask) \
(((addr1) | (mask)) == (((addr2) - 1) | (mask)))
#define BIOVEC_SEG_BOUNDARY(q, b1, b2) \
@ -319,15 +310,14 @@ struct bio_pair {
atomic_t cnt;
int error;
};
extern struct bio_pair *bio_split(struct bio *bi, mempool_t *pool,
int first_sectors);
extern mempool_t *bio_split_pool;
extern struct bio_pair *bio_split(struct bio *bi, int first_sectors);
extern void bio_pair_release(struct bio_pair *dbio);
extern struct bio_set *bioset_create(int, int);
extern void bioset_free(struct bio_set *);
extern struct bio *bio_alloc(gfp_t, int);
extern struct bio *bio_kmalloc(gfp_t, int);
extern struct bio *bio_alloc_bioset(gfp_t, int, struct bio_set *);
extern void bio_put(struct bio *);
extern void bio_free(struct bio *, struct bio_set *);
@ -335,7 +325,6 @@ extern void bio_free(struct bio *, struct bio_set *);
extern void bio_endio(struct bio *, int);
struct request_queue;
extern int bio_phys_segments(struct request_queue *, struct bio *);
extern int bio_hw_segments(struct request_queue *, struct bio *);
extern void __bio_clone(struct bio *, struct bio *);
extern struct bio *bio_clone(struct bio *, gfp_t);
@ -346,12 +335,14 @@ extern int bio_add_page(struct bio *, struct page *, unsigned int,unsigned int);
extern int bio_add_pc_page(struct request_queue *, struct bio *, struct page *,
unsigned int, unsigned int);
extern int bio_get_nr_vecs(struct block_device *);
extern sector_t bio_sector_offset(struct bio *, unsigned short, unsigned int);
extern struct bio *bio_map_user(struct request_queue *, struct block_device *,
unsigned long, unsigned int, int);
unsigned long, unsigned int, int, gfp_t);
struct sg_iovec;
struct rq_map_data;
extern struct bio *bio_map_user_iov(struct request_queue *,
struct block_device *,
struct sg_iovec *, int, int);
struct sg_iovec *, int, int, gfp_t);
extern void bio_unmap_user(struct bio *);
extern struct bio *bio_map_kern(struct request_queue *, void *, unsigned int,
gfp_t);
@ -359,14 +350,24 @@ extern struct bio *bio_copy_kern(struct request_queue *, void *, unsigned int,
gfp_t, int);
extern void bio_set_pages_dirty(struct bio *bio);
extern void bio_check_pages_dirty(struct bio *bio);
extern struct bio *bio_copy_user(struct request_queue *, unsigned long, unsigned int, int);
extern struct bio *bio_copy_user_iov(struct request_queue *, struct sg_iovec *,
int, int);
extern struct bio *bio_copy_user(struct request_queue *, struct rq_map_data *,
unsigned long, unsigned int, int, gfp_t);
extern struct bio *bio_copy_user_iov(struct request_queue *,
struct rq_map_data *, struct sg_iovec *,
int, int, gfp_t);
extern int bio_uncopy_user(struct bio *);
void zero_fill_bio(struct bio *bio);
extern struct bio_vec *bvec_alloc_bs(gfp_t, int, unsigned long *, struct bio_set *);
extern unsigned int bvec_nr_vecs(unsigned short idx);
/*
* Allow queuer to specify a completion CPU for this bio
*/
static inline void bio_set_completion_cpu(struct bio *bio, unsigned int cpu)
{
bio->bi_comp_cpu = cpu;
}
/*
* bio_set is used to allow other portions of the IO system to
* allocate their own private memory pools for bio and iovec structures.
@ -445,6 +446,14 @@ static inline char *__bio_kmap_irq(struct bio *bio, unsigned short idx,
__bio_kmap_irq((bio), (bio)->bi_idx, (flags))
#define bio_kunmap_irq(buf,flags) __bio_kunmap_irq(buf, flags)
/*
* Check whether this bio carries any data or not. A NULL bio is allowed.
*/
static inline int bio_has_data(struct bio *bio)
{
return bio && bio->bi_io_vec != NULL;
}
#if defined(CONFIG_BLK_DEV_INTEGRITY)
#define bip_vec_idx(bip, idx) (&(bip->bip_vec[(idx)]))
@ -458,14 +467,7 @@ static inline char *__bio_kmap_irq(struct bio *bio, unsigned short idx,
#define bip_for_each_vec(bvl, bip, i) \
__bip_for_each_vec(bvl, bip, i, (bip)->bip_idx)
static inline int bio_integrity(struct bio *bio)
{
#if defined(CONFIG_BLK_DEV_INTEGRITY)
return bio->bi_integrity != NULL;
#else
return 0;
#endif
}
#define bio_integrity(bio) (bio->bi_integrity != NULL)
extern struct bio_integrity_payload *bio_integrity_alloc_bioset(struct bio *, gfp_t, unsigned int, struct bio_set *);
extern struct bio_integrity_payload *bio_integrity_alloc(struct bio *, gfp_t, unsigned int);

153
include/linux/blkdev.h
View file

@ -16,7 +16,9 @@
#include <linux/bio.h>
#include <linux/module.h>
#include <linux/stringify.h>
#include <linux/gfp.h>
#include <linux/bsg.h>
#include <linux/smp.h>
#include <asm/scatterlist.h>
@ -54,7 +56,6 @@ enum rq_cmd_type_bits {
REQ_TYPE_PM_SUSPEND, /* suspend request */
REQ_TYPE_PM_RESUME, /* resume request */
REQ_TYPE_PM_SHUTDOWN, /* shutdown request */
REQ_TYPE_FLUSH, /* flush request */
REQ_TYPE_SPECIAL, /* driver defined type */
REQ_TYPE_LINUX_BLOCK, /* generic block layer message */
/*
@ -76,19 +77,18 @@ enum rq_cmd_type_bits {
*
*/
enum {
/*
* just examples for now
*/
REQ_LB_OP_EJECT = 0x40, /* eject request */
REQ_LB_OP_FLUSH = 0x41, /* flush device */
REQ_LB_OP_FLUSH = 0x41, /* flush request */
REQ_LB_OP_DISCARD = 0x42, /* discard sectors */
};
/*
* request type modified bits. first three bits match BIO_RW* bits, important
* request type modified bits. first two bits match BIO_RW* bits, important
*/
enum rq_flag_bits {
__REQ_RW, /* not set, read. set, write */
__REQ_FAILFAST, /* no low level driver retries */
__REQ_DISCARD, /* request to discard sectors */
__REQ_SORTED, /* elevator knows about this request */
__REQ_SOFTBARRIER, /* may not be passed by ioscheduler */
__REQ_HARDBARRIER, /* may not be passed by drive either */
@ -111,6 +111,7 @@ enum rq_flag_bits {
};
#define REQ_RW (1 << __REQ_RW)
#define REQ_DISCARD (1 << __REQ_DISCARD)
#define REQ_FAILFAST (1 << __REQ_FAILFAST)
#define REQ_SORTED (1 << __REQ_SORTED)
#define REQ_SOFTBARRIER (1 << __REQ_SOFTBARRIER)
@ -140,12 +141,14 @@ enum rq_flag_bits {
*/
struct request {
struct list_head queuelist;
struct list_head donelist;
struct call_single_data csd;
int cpu;
struct request_queue *q;
unsigned int cmd_flags;
enum rq_cmd_type_bits cmd_type;
unsigned long atomic_flags;
/* Maintain bio traversal state for part by part I/O submission.
* hard_* are block layer internals, no driver should touch them!
@ -190,13 +193,6 @@ struct request {
*/
unsigned short nr_phys_segments;
/* Number of scatter-gather addr+len pairs after
* physical and DMA remapping hardware coalescing is performed.
* This is the number of scatter-gather entries the driver
* will actually have to deal with after DMA mapping is done.
*/
unsigned short nr_hw_segments;
unsigned short ioprio;
void *special;
@ -220,6 +216,8 @@ struct request {
void *data;
void *sense;
unsigned long deadline;
struct list_head timeout_list;
unsigned int timeout;
int retries;
@ -233,6 +231,11 @@ struct request {
struct request *next_rq;
};
static inline unsigned short req_get_ioprio(struct request *req)
{
return req->ioprio;
}
/*
* State information carried for REQ_TYPE_PM_SUSPEND and REQ_TYPE_PM_RESUME
* requests. Some step values could eventually be made generic.
@ -252,6 +255,7 @@ typedef void (request_fn_proc) (struct request_queue *q);
typedef int (make_request_fn) (struct request_queue *q, struct bio *bio);
typedef int (prep_rq_fn) (struct request_queue *, struct request *);
typedef void (unplug_fn) (struct request_queue *);
typedef int (prepare_discard_fn) (struct request_queue *, struct request *);
struct bio_vec;
struct bvec_merge_data {
@ -265,6 +269,15 @@ typedef int (merge_bvec_fn) (struct request_queue *, struct bvec_merge_data *,
typedef void (prepare_flush_fn) (struct request_queue *, struct request *);
typedef void (softirq_done_fn)(struct request *);
typedef int (dma_drain_needed_fn)(struct request *);
typedef int (lld_busy_fn) (struct request_queue *q);
enum blk_eh_timer_return {
BLK_EH_NOT_HANDLED,
BLK_EH_HANDLED,
BLK_EH_RESET_TIMER,
};
typedef enum blk_eh_timer_return (rq_timed_out_fn)(struct request *);
enum blk_queue_state {
Queue_down,
@ -307,10 +320,13 @@ struct request_queue
make_request_fn *make_request_fn;
prep_rq_fn *prep_rq_fn;
unplug_fn *unplug_fn;
prepare_discard_fn *prepare_discard_fn;
merge_bvec_fn *merge_bvec_fn;
prepare_flush_fn *prepare_flush_fn;
softirq_done_fn *softirq_done_fn;
rq_timed_out_fn *rq_timed_out_fn;
dma_drain_needed_fn *dma_drain_needed;
lld_busy_fn *lld_busy_fn;
/*
* Dispatch queue sorting
@ -385,6 +401,10 @@ struct request_queue
unsigned int nr_sorted;
unsigned int in_flight;
unsigned int rq_timeout;
struct timer_list timeout;
struct list_head timeout_list;
/*
* sg stuff
*/
@ -421,6 +441,10 @@ struct request_queue
#define QUEUE_FLAG_ELVSWITCH 8 /* don't use elevator, just do FIFO */
#define QUEUE_FLAG_BIDI 9 /* queue supports bidi requests */
#define QUEUE_FLAG_NOMERGES 10 /* disable merge attempts */
#define QUEUE_FLAG_SAME_COMP 11 /* force complete on same CPU */
#define QUEUE_FLAG_FAIL_IO 12 /* fake timeout */
#define QUEUE_FLAG_STACKABLE 13 /* supports request stacking */
#define QUEUE_FLAG_NONROT 14 /* non-rotational device (SSD) */
static inline int queue_is_locked(struct request_queue *q)
{
@ -526,7 +550,10 @@ enum {
#define blk_queue_tagged(q) test_bit(QUEUE_FLAG_QUEUED, &(q)->queue_flags)
#define blk_queue_stopped(q) test_bit(QUEUE_FLAG_STOPPED, &(q)->queue_flags)
#define blk_queue_nomerges(q) test_bit(QUEUE_FLAG_NOMERGES, &(q)->queue_flags)
#define blk_queue_nonrot(q) test_bit(QUEUE_FLAG_NONROT, &(q)->queue_flags)
#define blk_queue_flushing(q) ((q)->ordseq)
#define blk_queue_stackable(q) \
test_bit(QUEUE_FLAG_STACKABLE, &(q)->queue_flags)
#define blk_fs_request(rq) ((rq)->cmd_type == REQ_TYPE_FS)
#define blk_pc_request(rq) ((rq)->cmd_type == REQ_TYPE_BLOCK_PC)
@ -536,16 +563,18 @@ enum {
#define blk_noretry_request(rq) ((rq)->cmd_flags & REQ_FAILFAST)
#define blk_rq_started(rq) ((rq)->cmd_flags & REQ_STARTED)
#define blk_account_rq(rq) (blk_rq_started(rq) && blk_fs_request(rq))
#define blk_account_rq(rq) (blk_rq_started(rq) && (blk_fs_request(rq) || blk_discard_rq(rq)))
#define blk_pm_suspend_request(rq) ((rq)->cmd_type == REQ_TYPE_PM_SUSPEND)
#define blk_pm_resume_request(rq) ((rq)->cmd_type == REQ_TYPE_PM_RESUME)
#define blk_pm_request(rq) \
(blk_pm_suspend_request(rq) || blk_pm_resume_request(rq))
#define blk_rq_cpu_valid(rq) ((rq)->cpu != -1)
#define blk_sorted_rq(rq) ((rq)->cmd_flags & REQ_SORTED)
#define blk_barrier_rq(rq) ((rq)->cmd_flags & REQ_HARDBARRIER)
#define blk_fua_rq(rq) ((rq)->cmd_flags & REQ_FUA)
#define blk_discard_rq(rq) ((rq)->cmd_flags & REQ_DISCARD)
#define blk_bidi_rq(rq) ((rq)->next_rq != NULL)
#define blk_empty_barrier(rq) (blk_barrier_rq(rq) && blk_fs_request(rq) && !(rq)->hard_nr_sectors)
/* rq->queuelist of dequeued request must be list_empty() */
@ -592,7 +621,8 @@ static inline void blk_clear_queue_full(struct request_queue *q, int rw)
#define RQ_NOMERGE_FLAGS \
(REQ_NOMERGE | REQ_STARTED | REQ_HARDBARRIER | REQ_SOFTBARRIER)
#define rq_mergeable(rq) \
(!((rq)->cmd_flags & RQ_NOMERGE_FLAGS) && blk_fs_request((rq)))
(!((rq)->cmd_flags & RQ_NOMERGE_FLAGS) && \
(blk_discard_rq(rq) || blk_fs_request((rq))))
/*
* q->prep_rq_fn return values
@ -637,6 +667,12 @@ static inline void blk_queue_bounce(struct request_queue *q, struct bio **bio)
}
#endif /* CONFIG_MMU */
struct rq_map_data {
struct page **pages;
int page_order;
int nr_entries;
};
struct req_iterator {
int i;
struct bio *bio;
@ -664,6 +700,10 @@ extern void __blk_put_request(struct request_queue *, struct request *);
extern struct request *blk_get_request(struct request_queue *, int, gfp_t);
extern void blk_insert_request(struct request_queue *, struct request *, int, void *);
extern void blk_requeue_request(struct request_queue *, struct request *);
extern int blk_rq_check_limits(struct request_queue *q, struct request *rq);
extern int blk_lld_busy(struct request_queue *q);
extern int blk_insert_cloned_request(struct request_queue *q,
struct request *rq);
extern void blk_plug_device(struct request_queue *);
extern void blk_plug_device_unlocked(struct request_queue *);
extern int blk_remove_plug(struct request_queue *);
@ -705,11 +745,14 @@ extern void __blk_stop_queue(struct request_queue *q);
extern void __blk_run_queue(struct request_queue *);
extern void blk_run_queue(struct request_queue *);
extern void blk_start_queueing(struct request_queue *);
extern int blk_rq_map_user(struct request_queue *, struct request *, void __user *, unsigned long);
extern int blk_rq_map_user(struct request_queue *, struct request *,
struct rq_map_data *, void __user *, unsigned long,
gfp_t);
extern int blk_rq_unmap_user(struct bio *);
extern int blk_rq_map_kern(struct request_queue *, struct request *, void *, unsigned int, gfp_t);
extern int blk_rq_map_user_iov(struct request_queue *, struct request *,
struct sg_iovec *, int, unsigned int);
struct rq_map_data *, struct sg_iovec *, int,
unsigned int, gfp_t);
extern int blk_execute_rq(struct request_queue *, struct gendisk *,
struct request *, int);
extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *,
@ -750,12 +793,15 @@ extern int __blk_end_request(struct request *rq, int error,
extern int blk_end_bidi_request(struct request *rq, int error,
unsigned int nr_bytes, unsigned int bidi_bytes);
extern void end_request(struct request *, int);
extern void end_queued_request(struct request *, int);
extern void end_dequeued_request(struct request *, int);
extern int blk_end_request_callback(struct request *rq, int error,
unsigned int nr_bytes,
int (drv_callback)(struct request *));
extern void blk_complete_request(struct request *);
extern void __blk_complete_request(struct request *);
extern void blk_abort_request(struct request *);
extern void blk_abort_queue(struct request_queue *);
extern void blk_update_request(struct request *rq, int error,
unsigned int nr_bytes);
/*
* blk_end_request() takes bytes instead of sectors as a complete size.
@ -790,12 +836,16 @@ extern void blk_queue_update_dma_pad(struct request_queue *, unsigned int);
extern int blk_queue_dma_drain(struct request_queue *q,
dma_drain_needed_fn *dma_drain_needed,
void *buf, unsigned int size);
extern void blk_queue_lld_busy(struct request_queue *q, lld_busy_fn *fn);
extern void blk_queue_segment_boundary(struct request_queue *, unsigned long);
extern void blk_queue_prep_rq(struct request_queue *, prep_rq_fn *pfn);
extern void blk_queue_merge_bvec(struct request_queue *, merge_bvec_fn *);
extern void blk_queue_dma_alignment(struct request_queue *, int);
extern void blk_queue_update_dma_alignment(struct request_queue *, int);
extern void blk_queue_softirq_done(struct request_queue *, softirq_done_fn *);
extern void blk_queue_set_discard(struct request_queue *, prepare_discard_fn *);
extern void blk_queue_rq_timed_out(struct request_queue *, rq_timed_out_fn *);
extern void blk_queue_rq_timeout(struct request_queue *, unsigned int);
extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev);
extern int blk_queue_ordered(struct request_queue *, unsigned, prepare_flush_fn *);
extern int blk_do_ordered(struct request_queue *, struct request **);
@ -837,14 +887,22 @@ static inline struct request *blk_map_queue_find_tag(struct blk_queue_tag *bqt,
}
extern int blkdev_issue_flush(struct block_device *, sector_t *);
extern int blkdev_issue_discard(struct block_device *,
sector_t sector, sector_t nr_sects, gfp_t);
static inline int sb_issue_discard(struct super_block *sb,
sector_t block, sector_t nr_blocks)
{
block <<= (sb->s_blocksize_bits - 9);
nr_blocks <<= (sb->s_blocksize_bits - 9);
return blkdev_issue_discard(sb->s_bdev, block, nr_blocks, GFP_KERNEL);
}
/*
* command filter functions
*/
extern int blk_verify_command(struct blk_cmd_filter *filter,
unsigned char *cmd, int has_write_perm);
extern int blk_register_filter(struct gendisk *disk);
extern void blk_unregister_filter(struct gendisk *disk);
extern void blk_set_cmd_filter_defaults(struct blk_cmd_filter *filter);
#define MAX_PHYS_SEGMENTS 128
@ -876,6 +934,13 @@ static inline int queue_dma_alignment(struct request_queue *q)
return q ? q->dma_alignment : 511;
}
static inline int blk_rq_aligned(struct request_queue *q, void *addr,
unsigned int len)
{
unsigned int alignment = queue_dma_alignment(q) | q->dma_pad_mask;
return !((unsigned long)addr & alignment) && !(len & alignment);
}
/* assumes size > 256 */
static inline unsigned int blksize_bits(unsigned int size)
{
@ -902,7 +967,7 @@ static inline void put_dev_sector(Sector p)
}
struct work_struct;
int kblockd_schedule_work(struct work_struct *work);
int kblockd_schedule_work(struct request_queue *q, struct work_struct *work);
void kblockd_flush_work(struct work_struct *work);
#define MODULE_ALIAS_BLOCKDEV(major,minor) \
@ -947,49 +1012,19 @@ struct blk_integrity {
extern int blk_integrity_register(struct gendisk *, struct blk_integrity *);
extern void blk_integrity_unregister(struct gendisk *);
extern int blk_integrity_compare(struct block_device *, struct block_device *);
extern int blk_integrity_compare(struct gendisk *, struct gendisk *);
extern int blk_rq_map_integrity_sg(struct request *, struct scatterlist *);
extern int blk_rq_count_integrity_sg(struct request *);
static inline unsigned short blk_integrity_tuple_size(struct blk_integrity *bi)
{
if (bi)
return bi->tuple_size;
return 0;
}
static inline struct blk_integrity *bdev_get_integrity(struct block_device *bdev)
static inline
struct blk_integrity *bdev_get_integrity(struct block_device *bdev)
{
return bdev->bd_disk->integrity;
}
static inline unsigned int bdev_get_tag_size(struct block_device *bdev)
static inline struct blk_integrity *blk_get_integrity(struct gendisk *disk)
{
struct blk_integrity *bi = bdev_get_integrity(bdev);
if (bi)
return bi->tag_size;
return 0;
}
static inline int bdev_integrity_enabled(struct block_device *bdev, int rw)
{
struct blk_integrity *bi = bdev_get_integrity(bdev);
if (bi == NULL)
return 0;
if (rw == READ && bi->verify_fn != NULL &&
(bi->flags & INTEGRITY_FLAG_READ))
return 1;
if (rw == WRITE && bi->generate_fn != NULL &&
(bi->flags & INTEGRITY_FLAG_WRITE))
return 1;
return 0;
return disk->integrity;
}
static inline int blk_integrity_rq(struct request *rq)
@ -1006,7 +1041,7 @@ static inline int blk_integrity_rq(struct request *rq)
#define blk_rq_count_integrity_sg(a) (0)
#define blk_rq_map_integrity_sg(a, b) (0)
#define bdev_get_integrity(a) (0)
#define bdev_get_tag_size(a) (0)
#define blk_get_integrity(a) (0)
#define blk_integrity_compare(a, b) (0)
#define blk_integrity_register(a, b) (0)
#define blk_integrity_unregister(a) do { } while (0);

62
include/linux/blktrace_api.h
View file

@ -1,8 +1,10 @@
#ifndef BLKTRACE_H
#define BLKTRACE_H
#ifdef __KERNEL__
#include <linux/blkdev.h>
#include <linux/relay.h>
#endif
/*
* Trace categories
@ -21,6 +23,7 @@ enum blktrace_cat {
BLK_TC_NOTIFY = 1 << 10, /* special message */
BLK_TC_AHEAD = 1 << 11, /* readahead */
BLK_TC_META = 1 << 12, /* metadata */
BLK_TC_DISCARD = 1 << 13, /* discard requests */
BLK_TC_END = 1 << 15, /* only 16-bits, reminder */
};
@ -47,6 +50,7 @@ enum blktrace_act {
__BLK_TA_SPLIT, /* bio was split */
__BLK_TA_BOUNCE, /* bio was bounced */
__BLK_TA_REMAP, /* bio was remapped */
__BLK_TA_ABORT, /* request aborted */
};
/*
@ -77,6 +81,7 @@ enum blktrace_notify {
#define BLK_TA_SPLIT (__BLK_TA_SPLIT)
#define BLK_TA_BOUNCE (__BLK_TA_BOUNCE)
#define BLK_TA_REMAP (__BLK_TA_REMAP | BLK_TC_ACT(BLK_TC_QUEUE))
#define BLK_TA_ABORT (__BLK_TA_ABORT | BLK_TC_ACT(BLK_TC_QUEUE))
#define BLK_TN_PROCESS (__BLK_TN_PROCESS | BLK_TC_ACT(BLK_TC_NOTIFY))
#define BLK_TN_TIMESTAMP (__BLK_TN_TIMESTAMP | BLK_TC_ACT(BLK_TC_NOTIFY))
@ -89,17 +94,17 @@ enum blktrace_notify {
* The trace itself
*/
struct blk_io_trace {
u32 magic; /* MAGIC << 8 | version */
u32 sequence; /* event number */
u64 time; /* in microseconds */
u64 sector; /* disk offset */
u32 bytes; /* transfer length */
u32 action; /* what happened */
u32 pid; /* who did it */
u32 device; /* device number */
u32 cpu; /* on what cpu did it happen */
u16 error; /* completion error */
u16 pdu_len; /* length of data after this trace */
__u32 magic; /* MAGIC << 8 | version */
__u32 sequence; /* event number */
__u64 time; /* in microseconds */
__u64 sector; /* disk offset */
__u32 bytes; /* transfer length */
__u32 action; /* what happened */
__u32 pid; /* who did it */
__u32 device; /* device number */
__u32 cpu; /* on what cpu did it happen */
__u16 error; /* completion error */
__u16 pdu_len; /* length of data after this trace */
};
/*
@ -117,6 +122,23 @@ enum {
Blktrace_stopped,
};
#define BLKTRACE_BDEV_SIZE 32
/*
* User setup structure passed with BLKTRACESTART
*/
struct blk_user_trace_setup {
char name[BLKTRACE_BDEV_SIZE]; /* output */
__u16 act_mask; /* input */
__u32 buf_size; /* input */
__u32 buf_nr; /* input */
__u64 start_lba;
__u64 end_lba;
__u32 pid;
};
#ifdef __KERNEL__
#if defined(CONFIG_BLK_DEV_IO_TRACE)
struct blk_trace {
int trace_state;
struct rchan *rchan;
@ -133,21 +155,6 @@ struct blk_trace {
atomic_t dropped;
};
/*
* User setup structure passed with BLKTRACESTART
*/
struct blk_user_trace_setup {
char name[BDEVNAME_SIZE]; /* output */
u16 act_mask; /* input */
u32 buf_size; /* input */
u32 buf_nr; /* input */
u64 start_lba;
u64 end_lba;
u32 pid;
};
#ifdef __KERNEL__
#if defined(CONFIG_BLK_DEV_IO_TRACE)
extern int blk_trace_ioctl(struct block_device *, unsigned, char __user *);
extern void blk_trace_shutdown(struct request_queue *);
extern void __blk_add_trace(struct blk_trace *, sector_t, int, int, u32, int, int, void *);
@ -195,6 +202,9 @@ static inline void blk_add_trace_rq(struct request_queue *q, struct request *rq,
if (likely(!bt))
return;
if (blk_discard_rq(rq))
rw |= (1 << BIO_RW_DISCARD);
if (blk_pc_request(rq)) {
what |= BLK_TC_ACT(BLK_TC_PC);
__blk_add_trace(bt, 0, rq->data_len, rw, what, rq->errors, sizeof(rq->cmd), rq->cmd);

80
include/linux/cnt32_to_63.h Normal file
View file

@ -0,0 +1,80 @@
/*
* Extend a 32-bit counter to 63 bits
*
* Author: Nicolas Pitre
* Created: December 3, 2006
* Copyright: MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*/
#ifndef __LINUX_CNT32_TO_63_H__
#define __LINUX_CNT32_TO_63_H__
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/byteorder.h>
/* this is used only to give gcc a clue about good code generation */
union cnt32_to_63 {
struct {
#if defined(__LITTLE_ENDIAN)
u32 lo, hi;
#elif defined(__BIG_ENDIAN)
u32 hi, lo;
#endif
};
u64 val;
};
/**
* cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
* @cnt_lo: The low part of the counter
*
* Many hardware clock counters are only 32 bits wide and therefore have
* a relatively short period making wrap-arounds rather frequent. This
* is a problem when implementing sched_clock() for example, where a 64-bit
* non-wrapping monotonic value is expected to be returned.
*
* To overcome that limitation, let's extend a 32-bit counter to 63 bits
* in a completely lock free fashion. Bits 0 to 31 of the clock are provided
* by the hardware while bits 32 to 62 are stored in memory. The top bit in
* memory is used to synchronize with the hardware clock half-period. When
* the top bit of both counters (hardware and in memory) differ then the
* memory is updated with a new value, incrementing it when the hardware
* counter wraps around.
*
* Because a word store in memory is atomic then the incremented value will
* always be in synch with the top bit indicating to any potential concurrent
* reader if the value in memory is up to date or not with regards to the
* needed increment. And any race in updating the value in memory is harmless
* as the same value would simply be stored more than once.
*
* The only restriction for the algorithm to work properly is that this
* code must be executed at least once per each half period of the 32-bit
* counter to properly update the state bit in memory. This is usually not a
* problem in practice, but if it is then a kernel timer could be scheduled
* to manage for this code to be executed often enough.
*
* Note that the top bit (bit 63) in the returned value should be considered
* as garbage. It is not cleared here because callers are likely to use a
* multiplier on the returned value which can get rid of the top bit
* implicitly by making the multiplier even, therefore saving on a runtime
* clear-bit instruction. Otherwise caller must remember to clear the top
* bit explicitly.
*/
#define cnt32_to_63(cnt_lo) \
({ \
static volatile u32 __m_cnt_hi; \
union cnt32_to_63 __x; \
__x.hi = __m_cnt_hi; \
__x.lo = (cnt_lo); \
if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
__m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
__x.val; \
})
#endif

4
include/linux/compiler.h
View file

@ -190,7 +190,9 @@ extern void __chk_io_ptr(const volatile void __iomem *);
* ACCESS_ONCE() in different C statements.
*
* This macro does absolutely -nothing- to prevent the CPU from reordering,
* merging, or refetching absolutely anything at any time.
* merging, or refetching absolutely anything at any time. Its main intended
* use is to mediate communication between process-level code and irq/NMI
* handlers, all running on the same CPU.
*/
#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))

41
include/linux/completion.h
View file

@ -10,6 +10,18 @@
#include <linux/wait.h>
/**
* struct completion - structure used to maintain state for a "completion"
*
* This is the opaque structure used to maintain the state for a "completion".
* Completions currently use a FIFO to queue threads that have to wait for
* the "completion" event.
*
* See also: complete(), wait_for_completion() (and friends _timeout,
* _interruptible, _interruptible_timeout, and _killable), init_completion(),
* and macros DECLARE_COMPLETION(), DECLARE_COMPLETION_ONSTACK(), and
* INIT_COMPLETION().
*/
struct completion {
unsigned int done;
wait_queue_head_t wait;
@ -21,6 +33,14 @@ struct completion {
#define COMPLETION_INITIALIZER_ONSTACK(work) \
({ init_completion(&work); work; })
/**
* DECLARE_COMPLETION: - declare and initialize a completion structure
* @work: identifier for the completion structure
*
* This macro declares and initializes a completion structure. Generally used
* for static declarations. You should use the _ONSTACK variant for automatic
* variables.
*/
#define DECLARE_COMPLETION(work) \
struct completion work = COMPLETION_INITIALIZER(work)
@ -29,6 +49,13 @@ struct completion {
* completions - so we use the _ONSTACK() variant for those that
* are on the kernel stack:
*/
/**
* DECLARE_COMPLETION_ONSTACK: - declare and initialize a completion structure
* @work: identifier for the completion structure
*
* This macro declares and initializes a completion structure on the kernel
* stack.
*/
#ifdef CONFIG_LOCKDEP
# define DECLARE_COMPLETION_ONSTACK(work) \
struct completion work = COMPLETION_INITIALIZER_ONSTACK(work)
@ -36,6 +63,13 @@ struct completion {
# define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work)
#endif
/**
* init_completion: - Initialize a dynamically allocated completion
* @x: completion structure that is to be initialized
*
* This inline function will initialize a dynamically created completion
* structure.
*/
static inline void init_completion(struct completion *x)
{
x->done = 0;
@ -55,6 +89,13 @@ extern bool completion_done(struct completion *x);
extern void complete(struct completion *);
extern void complete_all(struct completion *);
/**
* INIT_COMPLETION: - reinitialize a completion structure
* @x: completion structure to be reinitialized
*
* This macro should be used to reinitialize a completion structure so it can
* be reused. This is especially important after complete_all() is used.
*/
#define INIT_COMPLETION(x) ((x).done = 0)

1
include/linux/console_struct.h
View file

@ -53,7 +53,6 @@ struct vc_data {
unsigned short vc_hi_font_mask; /* [#] Attribute set for upper 256 chars of font or 0 if not supported */
struct console_font vc_font; /* Current VC font set */
unsigned short vc_video_erase_char; /* Background erase character */
unsigned short vc_scrl_erase_char; /* Erase character for scroll */
/* VT terminal data */
unsigned int vc_state; /* Escape sequence parser state */
unsigned int vc_npar,vc_par[NPAR]; /* Parameters of current escape sequence */

1
include/linux/cpu.h
View file

@ -69,6 +69,7 @@ static inline void unregister_cpu_notifier(struct notifier_block *nb)
#endif
int cpu_up(unsigned int cpu);
void notify_cpu_starting(unsigned int cpu);
extern void cpu_hotplug_init(void);
extern void cpu_maps_update_begin(void);
extern void cpu_maps_update_done(void);

7
include/linux/cpufreq.h
View file

@ -187,7 +187,8 @@ extern int __cpufreq_driver_target(struct cpufreq_policy *policy,
unsigned int relation);
extern int __cpufreq_driver_getavg(struct cpufreq_policy *policy);
extern int __cpufreq_driver_getavg(struct cpufreq_policy *policy,
unsigned int cpu);
int cpufreq_register_governor(struct cpufreq_governor *governor);
void cpufreq_unregister_governor(struct cpufreq_governor *governor);
@ -226,7 +227,9 @@ struct cpufreq_driver {
unsigned int (*get) (unsigned int cpu);
/* optional */
unsigned int (*getavg) (unsigned int cpu);
unsigned int (*getavg) (struct cpufreq_policy *policy,
unsigned int cpu);
int (*exit) (struct cpufreq_policy *policy);
int (*suspend) (struct cpufreq_policy *policy, pm_message_t pmsg);
int (*resume) (struct cpufreq_policy *policy);

35
include/linux/crypto.h
View file

@ -38,6 +38,7 @@
#define CRYPTO_ALG_TYPE_DIGEST 0x00000008
#define CRYPTO_ALG_TYPE_HASH 0x00000009
#define CRYPTO_ALG_TYPE_AHASH 0x0000000a
#define CRYPTO_ALG_TYPE_RNG 0x0000000c
#define CRYPTO_ALG_TYPE_HASH_MASK 0x0000000e
#define CRYPTO_ALG_TYPE_AHASH_MASK 0x0000000c
@ -60,6 +61,14 @@
*/
#define CRYPTO_ALG_GENIV 0x00000200
/*
* Set if the algorithm has passed automated run-time testing. Note that
* if there is no run-time testing for a given algorithm it is considered
* to have passed.
*/
#define CRYPTO_ALG_TESTED 0x00000400
/*
* Transform masks and values (for crt_flags).
*/
@ -105,6 +114,7 @@ struct crypto_aead;
struct crypto_blkcipher;
struct crypto_hash;
struct crypto_ahash;
struct crypto_rng;
struct crypto_tfm;
struct crypto_type;
struct aead_givcrypt_request;
@ -290,6 +300,15 @@ struct compress_alg {
unsigned int slen, u8 *dst, unsigned int *dlen);
};
struct rng_alg {
int (*rng_make_random)(struct crypto_rng *tfm, u8 *rdata,
unsigned int dlen);
int (*rng_reset)(struct crypto_rng *tfm, u8 *seed, unsigned int slen);
unsigned int seedsize;
};
#define cra_ablkcipher cra_u.ablkcipher
#define cra_aead cra_u.aead
#define cra_blkcipher cra_u.blkcipher
@ -298,6 +317,7 @@ struct compress_alg {
#define cra_hash cra_u.hash
#define cra_ahash cra_u.ahash
#define cra_compress cra_u.compress
#define cra_rng cra_u.rng
struct crypto_alg {
struct list_head cra_list;
@ -325,6 +345,7 @@ struct crypto_alg {
struct hash_alg hash;
struct ahash_alg ahash;
struct compress_alg compress;
struct rng_alg rng;
} cra_u;
int (*cra_init)(struct crypto_tfm *tfm);
@ -430,6 +451,12 @@ struct compress_tfm {
u8 *dst, unsigned int *dlen);
};
struct rng_tfm {
int (*rng_gen_random)(struct crypto_rng *tfm, u8 *rdata,
unsigned int dlen);
int (*rng_reset)(struct crypto_rng *tfm, u8 *seed, unsigned int slen);
};
#define crt_ablkcipher crt_u.ablkcipher
#define crt_aead crt_u.aead
#define crt_blkcipher crt_u.blkcipher
@ -437,6 +464,7 @@ struct compress_tfm {
#define crt_hash crt_u.hash
#define crt_ahash crt_u.ahash
#define crt_compress crt_u.compress
#define crt_rng crt_u.rng
struct crypto_tfm {
@ -450,6 +478,7 @@ struct crypto_tfm {
struct hash_tfm hash;
struct ahash_tfm ahash;
struct compress_tfm compress;
struct rng_tfm rng;
} crt_u;
struct crypto_alg *__crt_alg;
@ -481,6 +510,10 @@ struct crypto_hash {
struct crypto_tfm base;
};
struct crypto_rng {
struct crypto_tfm base;
};
enum {
CRYPTOA_UNSPEC,
CRYPTOA_ALG,
@ -515,6 +548,8 @@ struct crypto_tfm *crypto_alloc_tfm(const char *alg_name, u32 tfm_flags);
struct crypto_tfm *crypto_alloc_base(const char *alg_name, u32 type, u32 mask);
void crypto_free_tfm(struct crypto_tfm *tfm);
int alg_test(const char *driver, const char *alg, u32 type, u32 mask);
/*
* Transform helpers which query the underlying algorithm.
*/

18
include/linux/device-mapper.h
View file

@ -13,7 +13,6 @@
struct dm_target;
struct dm_table;
struct dm_dev;
struct mapped_device;
struct bio_vec;
@ -84,6 +83,12 @@ void dm_error(const char *message);
*/
void dm_set_device_limits(struct dm_target *ti, struct block_device *bdev);
struct dm_dev {
struct block_device *bdev;
int mode;
char name[16];
};
/*
* Constructors should call these functions to ensure destination devices
* are opened/closed correctly.
@ -202,6 +207,7 @@ int dm_copy_name_and_uuid(struct mapped_device *md, char *name, char *uuid);
struct gendisk *dm_disk(struct mapped_device *md);
int dm_suspended(struct mapped_device *md);
int dm_noflush_suspending(struct dm_target *ti);
union map_info *dm_get_mapinfo(struct bio *bio);
/*
* Geometry functions.
@ -231,6 +237,11 @@ int dm_table_add_target(struct dm_table *t, const char *type,
*/
int dm_table_complete(struct dm_table *t);
/*
* Unplug all devices in a table.
*/
void dm_table_unplug_all(struct dm_table *t);
/*
* Table reference counting.
*/
@ -256,6 +267,11 @@ void dm_table_event(struct dm_table *t);
*/
int dm_swap_table(struct mapped_device *md, struct dm_table *t);
/*
* A wrapper around vmalloc.
*/
void *dm_vcalloc(unsigned long nmemb, unsigned long elem_size);
/*-----------------------------------------------------------------
* Macros.
*---------------------------------------------------------------*/

14
include/linux/device.h
View file

@ -199,6 +199,11 @@ struct class {
struct class_private *p;
};
struct class_dev_iter {
struct klist_iter ki;
const struct device_type *type;
};
extern struct kobject *sysfs_dev_block_kobj;
extern struct kobject *sysfs_dev_char_kobj;
extern int __must_check __class_register(struct class *class,
@ -213,6 +218,13 @@ extern void class_unregister(struct class *class);
__class_register(class, &__key); \
})
extern void class_dev_iter_init(struct class_dev_iter *iter,
struct class *class,
struct device *start,
const struct device_type *type);
extern struct device *class_dev_iter_next(struct class_dev_iter *iter);
extern void class_dev_iter_exit(struct class_dev_iter *iter);
extern int class_for_each_device(struct class *class, struct device *start,
void *data,
int (*fn)(struct device *dev, void *data));
@ -396,7 +408,7 @@ struct device {
spinlock_t devres_lock;
struct list_head devres_head;
struct list_head node;
struct klist_node knode_class;
struct class *class;
dev_t devt; /* dev_t, creates the sysfs "dev" */
struct attribute_group **groups; /* optional groups */

31
include/linux/devpts_fs.h
View file

@ -17,20 +17,31 @@
#ifdef CONFIG_UNIX98_PTYS
int devpts_new_index(void);
void devpts_kill_index(int idx);
int devpts_pty_new(struct tty_struct *tty); /* mknod in devpts */
struct tty_struct *devpts_get_tty(int number); /* get tty structure */
void devpts_pty_kill(int number); /* unlink */
int devpts_new_index(struct inode *ptmx_inode);
void devpts_kill_index(struct inode *ptmx_inode, int idx);
/* mknod in devpts */
int devpts_pty_new(struct inode *ptmx_inode, struct tty_struct *tty);
/* get tty structure */
struct tty_struct *devpts_get_tty(struct inode *pts_inode, int number);
/* unlink */
void devpts_pty_kill(struct tty_struct *tty);
#else
/* Dummy stubs in the no-pty case */
static inline int devpts_new_index(void) { return -EINVAL; }
static inline void devpts_kill_index(int idx) { }
static inline int devpts_pty_new(struct tty_struct *tty) { return -EINVAL; }
static inline struct tty_struct *devpts_get_tty(int number) { return NULL; }
static inline void devpts_pty_kill(int number) { }
static inline int devpts_new_index(struct inode *ptmx_inode) { return -EINVAL; }
static inline void devpts_kill_index(struct inode *ptmx_inode, int idx) { }
static inline int devpts_pty_new(struct inode *ptmx_inode,
struct tty_struct *tty)
{
return -EINVAL;
}
static inline struct tty_struct *devpts_get_tty(struct inode *pts_inode,
int number)
{
return NULL;
}
static inline void devpts_pty_kill(struct tty_struct *tty) { }
#endif

5
include/linux/dlm.h
View file

@ -2,7 +2,7 @@
*******************************************************************************
**
** Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved.
** Copyright (C) 2004-2007 Red Hat, Inc. All rights reserved.
** Copyright (C) 2004-2008 Red Hat, Inc. All rights reserved.
**
** This copyrighted material is made available to anyone wishing to use,
** modify, copy, or redistribute it subject to the terms and conditions
@ -65,9 +65,12 @@ struct dlm_lksb {
char * sb_lvbptr;
};
/* dlm_new_lockspace() flags */
#define DLM_LSFL_NODIR 0x00000001
#define DLM_LSFL_TIMEWARN 0x00000002
#define DLM_LSFL_FS 0x00000004
#define DLM_LSFL_NEWEXCL 0x00000008
#ifdef __KERNEL__

2
include/linux/dlm_device.h
View file

@ -26,7 +26,7 @@
/* Version of the device interface */
#define DLM_DEVICE_VERSION_MAJOR 6
#define DLM_DEVICE_VERSION_MINOR 0
#define DLM_DEVICE_VERSION_PATCH 0
#define DLM_DEVICE_VERSION_PATCH 1
/* struct passed to the lock write */
struct dlm_lock_params {

12
include/linux/dma-mapping.h
View file

@ -48,6 +48,11 @@ static inline int is_device_dma_capable(struct device *dev)
return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
}
static inline int is_buffer_dma_capable(u64 mask, dma_addr_t addr, size_t size)
{
return addr + size <= mask;
}
#ifdef CONFIG_HAS_DMA
#include <asm/dma-mapping.h>
#else
@ -58,6 +63,13 @@ static inline int is_device_dma_capable(struct device *dev)
#define dma_sync_single dma_sync_single_for_cpu
#define dma_sync_sg dma_sync_sg_for_cpu
static inline u64 dma_get_mask(struct device *dev)
{
if (dev && dev->dma_mask && *dev->dma_mask)
return *dev->dma_mask;
return DMA_32BIT_MASK;
}
extern u64 dma_get_required_mask(struct device *dev);
static inline unsigned int dma_get_max_seg_size(struct device *dev)

127
include/linux/dmar.h
View file

@ -25,9 +25,99 @@
#include <linux/types.h>
#include <linux/msi.h>
#ifdef CONFIG_DMAR
#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
struct intel_iommu;
struct dmar_drhd_unit {
struct list_head list; /* list of drhd units */
struct acpi_dmar_header *hdr; /* ACPI header */
u64 reg_base_addr; /* register base address*/
struct pci_dev **devices; /* target device array */
int devices_cnt; /* target device count */
u8 ignored:1; /* ignore drhd */
u8 include_all:1;
struct intel_iommu *iommu;
};
extern struct list_head dmar_drhd_units;
#define for_each_drhd_unit(drhd) \
list_for_each_entry(drhd, &dmar_drhd_units, list)
extern int dmar_table_init(void);
extern int early_dmar_detect(void);
extern int dmar_dev_scope_init(void);
/* Intel IOMMU detection */
extern void detect_intel_iommu(void);
extern int parse_ioapics_under_ir(void);
extern int alloc_iommu(struct dmar_drhd_unit *);
#else
static inline void detect_intel_iommu(void)
{
return;
}
static inline int dmar_table_init(void)
{
return -ENODEV;
}
#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
#ifdef CONFIG_INTR_REMAP
extern int intr_remapping_enabled;
extern int enable_intr_remapping(int);
struct irte {
union {
struct {
__u64 present : 1,
fpd : 1,
dst_mode : 1,
redir_hint : 1,
trigger_mode : 1,
dlvry_mode : 3,
avail : 4,
__reserved_1 : 4,
vector : 8,
__reserved_2 : 8,
dest_id : 32;
};
__u64 low;
};
union {
struct {
__u64 sid : 16,
sq : 2,
svt : 2,
__reserved_3 : 44;
};
__u64 high;
};
};
extern int get_irte(int irq, struct irte *entry);
extern int modify_irte(int irq, struct irte *irte_modified);
extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
u16 sub_handle);
extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
extern int flush_irte(int irq);
extern int free_irte(int irq);
extern int irq_remapped(int irq);
extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
extern struct intel_iommu *map_ioapic_to_ir(int apic);
#else
#define irq_remapped(irq) (0)
#define enable_intr_remapping(mode) (-1)
#define intr_remapping_enabled (0)
#endif
#ifdef CONFIG_DMAR
extern const char *dmar_get_fault_reason(u8 fault_reason);
/* Can't use the common MSI interrupt functions
@ -40,47 +130,30 @@ extern void dmar_msi_write(int irq, struct msi_msg *msg);
extern int dmar_set_interrupt(struct intel_iommu *iommu);
extern int arch_setup_dmar_msi(unsigned int irq);
/* Intel IOMMU detection and initialization functions */
extern void detect_intel_iommu(void);
extern int intel_iommu_init(void);
extern int dmar_table_init(void);
extern int early_dmar_detect(void);
extern struct list_head dmar_drhd_units;
extern int iommu_detected, no_iommu;
extern struct list_head dmar_rmrr_units;
struct dmar_drhd_unit {
struct list_head list; /* list of drhd units */
u64 reg_base_addr; /* register base address*/
struct pci_dev **devices; /* target device array */
int devices_cnt; /* target device count */
u8 ignored:1; /* ignore drhd */
u8 include_all:1;
struct intel_iommu *iommu;
};
struct dmar_rmrr_unit {
struct list_head list; /* list of rmrr units */
struct acpi_dmar_header *hdr; /* ACPI header */
u64 base_address; /* reserved base address*/
u64 end_address; /* reserved end address */
struct pci_dev **devices; /* target devices */
int devices_cnt; /* target device count */
};
#define for_each_drhd_unit(drhd) \
list_for_each_entry(drhd, &dmar_drhd_units, list)
#define for_each_rmrr_units(rmrr) \
list_for_each_entry(rmrr, &dmar_rmrr_units, list)
/* Intel DMAR initialization functions */
extern int intel_iommu_init(void);
extern int dmar_disabled;
#else
static inline void detect_intel_iommu(void)
{
return;
}
static inline int intel_iommu_init(void)
{
#ifdef CONFIG_INTR_REMAP
return dmar_dev_scope_init();
#else
return -ENODEV;
#endif
}
#endif /* !CONFIG_DMAR */
#endif /* __DMAR_H__ */

41
include/linux/dmi.h
View file

@ -2,29 +2,9 @@
#define __DMI_H__
#include <linux/list.h>
#include <linux/mod_devicetable.h>
enum dmi_field {
DMI_NONE,
DMI_BIOS_VENDOR,
DMI_BIOS_VERSION,
DMI_BIOS_DATE,
DMI_SYS_VENDOR,
DMI_PRODUCT_NAME,
DMI_PRODUCT_VERSION,
DMI_PRODUCT_SERIAL,
DMI_PRODUCT_UUID,
DMI_BOARD_VENDOR,
DMI_BOARD_NAME,
DMI_BOARD_VERSION,
DMI_BOARD_SERIAL,
DMI_BOARD_ASSET_TAG,
DMI_CHASSIS_VENDOR,
DMI_CHASSIS_TYPE,
DMI_CHASSIS_VERSION,
DMI_CHASSIS_SERIAL,
DMI_CHASSIS_ASSET_TAG,
DMI_STRING_MAX,
};
/* enum dmi_field is in mod_devicetable.h */
enum dmi_device_type {
DMI_DEV_TYPE_ANY = 0,
@ -48,23 +28,6 @@ struct dmi_header {
u16 handle;
};
/*
* DMI callbacks for problem boards
*/
struct dmi_strmatch {
u8 slot;
char *substr;
};
struct dmi_system_id {
int (*callback)(const struct dmi_system_id *);
const char *ident;
struct dmi_strmatch matches[4];
void *driver_data;
};
#define DMI_MATCH(a, b) { a, b }
struct dmi_device {
struct list_head list;
int type;

110
include/linux/dvb/frontend.h
View file

@ -62,6 +62,7 @@ typedef enum fe_caps {
FE_CAN_HIERARCHY_AUTO = 0x100000,
FE_CAN_8VSB = 0x200000,
FE_CAN_16VSB = 0x400000,
FE_HAS_EXTENDED_CAPS = 0x800000, // We need more bitspace for newer APIs, indicate this.
FE_NEEDS_BENDING = 0x20000000, // not supported anymore, don't use (frontend requires frequency bending)
FE_CAN_RECOVER = 0x40000000, // frontend can recover from a cable unplug automatically
FE_CAN_MUTE_TS = 0x80000000 // frontend can stop spurious TS data output
@ -147,7 +148,9 @@ typedef enum fe_code_rate {
FEC_6_7,
FEC_7_8,
FEC_8_9,
FEC_AUTO
FEC_AUTO,
FEC_3_5,
FEC_9_10,
} fe_code_rate_t;
@ -160,7 +163,10 @@ typedef enum fe_modulation {
QAM_256,
QAM_AUTO,
VSB_8,
VSB_16
VSB_16,
PSK_8,
APSK_16,
DQPSK,
} fe_modulation_t;
typedef enum fe_transmit_mode {
@ -239,6 +245,106 @@ struct dvb_frontend_event {
struct dvb_frontend_parameters parameters;
};
/* S2API Commands */
#define DTV_UNDEFINED 0
#define DTV_TUNE 1
#define DTV_CLEAR 2
#define DTV_FREQUENCY 3
#define DTV_MODULATION 4
#define DTV_BANDWIDTH_HZ 5
#define DTV_INVERSION 6
#define DTV_DISEQC_MASTER 7
#define DTV_SYMBOL_RATE 8
#define DTV_INNER_FEC 9
#define DTV_VOLTAGE 10
#define DTV_TONE 11
#define DTV_PILOT 12
#define DTV_ROLLOFF 13
#define DTV_DISEQC_SLAVE_REPLY 14
/* Basic enumeration set for querying unlimited capabilities */
#define DTV_FE_CAPABILITY_COUNT 15
#define DTV_FE_CAPABILITY 16
#define DTV_DELIVERY_SYSTEM 17
#define DTV_API_VERSION 35
#define DTV_API_VERSION 35
#define DTV_CODE_RATE_HP 36
#define DTV_CODE_RATE_LP 37
#define DTV_GUARD_INTERVAL 38
#define DTV_TRANSMISSION_MODE 39
#define DTV_HIERARCHY 40
#define DTV_MAX_COMMAND DTV_HIERARCHY
typedef enum fe_pilot {
PILOT_ON,
PILOT_OFF,
PILOT_AUTO,
} fe_pilot_t;
typedef enum fe_rolloff {
ROLLOFF_35, /* Implied value in DVB-S, default for DVB-S2 */
ROLLOFF_20,
ROLLOFF_25,
ROLLOFF_AUTO,
} fe_rolloff_t;
typedef enum fe_delivery_system {
SYS_UNDEFINED,
SYS_DVBC_ANNEX_AC,
SYS_DVBC_ANNEX_B,
SYS_DVBT,
SYS_DVBS,
SYS_DVBS2,
SYS_DVBH,
SYS_ISDBT,
SYS_ISDBS,
SYS_ISDBC,
SYS_ATSC,
SYS_ATSCMH,
SYS_DMBTH,
SYS_CMMB,
SYS_DAB,
} fe_delivery_system_t;
struct dtv_cmds_h {
char *name; /* A display name for debugging purposes */
__u32 cmd; /* A unique ID */
/* Flags */
__u32 set:1; /* Either a set or get property */
__u32 buffer:1; /* Does this property use the buffer? */
__u32 reserved:30; /* Align */
};
struct dtv_property {
__u32 cmd;
__u32 reserved[3];
union {
__u32 data;
struct {
__u8 data[32];
__u32 len;
__u32 reserved1[3];
void *reserved2;
} buffer;
} u;
int result;
} __attribute__ ((packed));
/* num of properties cannot exceed DTV_IOCTL_MAX_MSGS per ioctl */
#define DTV_IOCTL_MAX_MSGS 64
struct dtv_properties {
__u32 num;
struct dtv_property *props;
};
#define FE_SET_PROPERTY _IOW('o', 82, struct dtv_properties)
#define FE_GET_PROPERTY _IOR('o', 83, struct dtv_properties)
/**
* When set, this flag will disable any zigzagging or other "normal" tuning

4
include/linux/dvb/version.h
View file

@ -23,7 +23,7 @@
#ifndef _DVBVERSION_H_
#define _DVBVERSION_H_
#define DVB_API_VERSION 3
#define DVB_API_VERSION_MINOR 2
#define DVB_API_VERSION 5
#define DVB_API_VERSION_MINOR 0
#endif /*_DVBVERSION_H_*/

9
include/linux/elevator.h
View file

@ -112,6 +112,7 @@ extern struct request *elv_latter_request(struct request_queue *, struct request
extern int elv_register_queue(struct request_queue *q);
extern void elv_unregister_queue(struct request_queue *q);
extern int elv_may_queue(struct request_queue *, int);
extern void elv_abort_queue(struct request_queue *);
extern void elv_completed_request(struct request_queue *, struct request *);
extern int elv_set_request(struct request_queue *, struct request *, gfp_t);
extern void elv_put_request(struct request_queue *, struct request *);
@ -173,15 +174,15 @@ enum {
#define rb_entry_rq(node) rb_entry((node), struct request, rb_node)
/*
* Hack to reuse the donelist list_head as the fifo time holder while
* Hack to reuse the csd.list list_head as the fifo time holder while
* the request is in the io scheduler. Saves an unsigned long in rq.
*/
#define rq_fifo_time(rq) ((unsigned long) (rq)->donelist.next)
#define rq_set_fifo_time(rq,exp) ((rq)->donelist.next = (void *) (exp))
#define rq_fifo_time(rq) ((unsigned long) (rq)->csd.list.next)
#define rq_set_fifo_time(rq,exp) ((rq)->csd.list.next = (void *) (exp))
#define rq_entry_fifo(ptr) list_entry((ptr), struct request, queuelist)
#define rq_fifo_clear(rq) do { \
list_del_init(&(rq)->queuelist); \
INIT_LIST_HEAD(&(rq)->donelist); \
INIT_LIST_HEAD(&(rq)->csd.list); \
} while (0)
/*

1
include/linux/elf.h
View file

@ -360,6 +360,7 @@ typedef struct elf64_shdr {
#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */
#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */
/* Note header in a PT_NOTE section */

2
include/linux/ext3_fs.h
View file

@ -837,6 +837,8 @@ extern void ext3_truncate (struct inode *);
extern void ext3_set_inode_flags(struct inode *);
extern void ext3_get_inode_flags(struct ext3_inode_info *);
extern void ext3_set_aops(struct inode *inode);
extern int ext3_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
u64 start, u64 len);
/* ioctl.c */
extern int ext3_ioctl (struct inode *, struct file *, unsigned int,

8
include/linux/fd.h
View file

@ -15,10 +15,16 @@ struct floppy_struct {
sect, /* sectors per track */
head, /* nr of heads */
track, /* nr of tracks */
stretch; /* !=0 means double track steps */
stretch; /* bit 0 !=0 means double track steps */
/* bit 1 != 0 means swap sides */
/* bits 2..9 give the first sector */
/* number (the LSB is flipped) */
#define FD_STRETCH 1
#define FD_SWAPSIDES 2
#define FD_ZEROBASED 4
#define FD_SECTBASEMASK 0x3FC
#define FD_MKSECTBASE(s) (((s) ^ 1) << 2)
#define FD_SECTBASE(floppy) ((((floppy)->stretch & FD_SECTBASEMASK) >> 2) ^ 1)
unsigned char gap, /* gap1 size */

64
include/linux/fiemap.h Normal file
View file

@ -0,0 +1,64 @@
/*
* FS_IOC_FIEMAP ioctl infrastructure.
*
* Some portions copyright (C) 2007 Cluster File Systems, Inc
*
* Authors: Mark Fasheh <mfasheh@suse.com>
* Kalpak Shah <kalpak.shah@sun.com>
* Andreas Dilger <adilger@sun.com>
*/
#ifndef _LINUX_FIEMAP_H
#define _LINUX_FIEMAP_H
struct fiemap_extent {
__u64 fe_logical; /* logical offset in bytes for the start of
* the extent from the beginning of the file */
__u64 fe_physical; /* physical offset in bytes for the start
* of the extent from the beginning of the disk */
__u64 fe_length; /* length in bytes for this extent */
__u64 fe_reserved64[2];
__u32 fe_flags; /* FIEMAP_EXTENT_* flags for this extent */
__u32 fe_reserved[3];
};
struct fiemap {
__u64 fm_start; /* logical offset (inclusive) at
* which to start mapping (in) */
__u64 fm_length; /* logical length of mapping which
* userspace wants (in) */
__u32 fm_flags; /* FIEMAP_FLAG_* flags for request (in/out) */
__u32 fm_mapped_extents;/* number of extents that were mapped (out) */
__u32 fm_extent_count; /* size of fm_extents array (in) */
__u32 fm_reserved;
struct fiemap_extent fm_extents[0]; /* array of mapped extents (out) */
};
#define FIEMAP_MAX_OFFSET (~0ULL)
#define FIEMAP_FLAG_SYNC 0x00000001 /* sync file data before map */
#define FIEMAP_FLAG_XATTR 0x00000002 /* map extended attribute tree */
#define FIEMAP_FLAGS_COMPAT (FIEMAP_FLAG_SYNC | FIEMAP_FLAG_XATTR)
#define FIEMAP_EXTENT_LAST 0x00000001 /* Last extent in file. */
#define FIEMAP_EXTENT_UNKNOWN 0x00000002 /* Data location unknown. */
#define FIEMAP_EXTENT_DELALLOC 0x00000004 /* Location still pending.
* Sets EXTENT_UNKNOWN. */
#define FIEMAP_EXTENT_ENCODED 0x00000008 /* Data can not be read
* while fs is unmounted */
#define FIEMAP_EXTENT_DATA_ENCRYPTED 0x00000080 /* Data is encrypted by fs.
* Sets EXTENT_NO_BYPASS. */
#define FIEMAP_EXTENT_NOT_ALIGNED 0x00000100 /* Extent offsets may not be
* block aligned. */
#define FIEMAP_EXTENT_DATA_INLINE 0x00000200 /* Data mixed with metadata.
* Sets EXTENT_NOT_ALIGNED.*/
#define FIEMAP_EXTENT_DATA_TAIL 0x00000400 /* Multiple files in block.
* Sets EXTENT_NOT_ALIGNED.*/
#define FIEMAP_EXTENT_UNWRITTEN 0x00000800 /* Space allocated, but
* no data (i.e. zero). */
#define FIEMAP_EXTENT_MERGED 0x00001000 /* File does not natively
* support extents. Result
* merged for efficiency. */
#endif /* _LINUX_FIEMAP_H */

95
include/linux/fs.h
View file

@ -86,7 +86,9 @@ extern int dir_notify_enable;
#define READ_META (READ | (1 << BIO_RW_META))
#define WRITE_SYNC (WRITE | (1 << BIO_RW_SYNC))
#define SWRITE_SYNC (SWRITE | (1 << BIO_RW_SYNC))
#define WRITE_BARRIER ((1 << BIO_RW) | (1 << BIO_RW_BARRIER))
#define WRITE_BARRIER (WRITE | (1 << BIO_RW_BARRIER))
#define DISCARD_NOBARRIER (1 << BIO_RW_DISCARD)
#define DISCARD_BARRIER ((1 << BIO_RW_DISCARD) | (1 << BIO_RW_BARRIER))
#define SEL_IN 1
#define SEL_OUT 2
@ -222,6 +224,7 @@ extern int dir_notify_enable;
#define BLKTRACESTART _IO(0x12,116)
#define BLKTRACESTOP _IO(0x12,117)
#define BLKTRACETEARDOWN _IO(0x12,118)
#define BLKDISCARD _IO(0x12,119)
#define BMAP_IOCTL 1 /* obsolete - kept for compatibility */
#define FIBMAP _IO(0x00,1) /* bmap access */
@ -231,6 +234,7 @@ extern int dir_notify_enable;
#define FS_IOC_SETFLAGS _IOW('f', 2, long)
#define FS_IOC_GETVERSION _IOR('v', 1, long)
#define FS_IOC_SETVERSION _IOW('v', 2, long)
#define FS_IOC_FIEMAP _IOWR('f', 11, struct fiemap)
#define FS_IOC32_GETFLAGS _IOR('f', 1, int)
#define FS_IOC32_SETFLAGS _IOW('f', 2, int)
#define FS_IOC32_GETVERSION _IOR('v', 1, int)
@ -291,6 +295,7 @@ extern int dir_notify_enable;
#include <linux/mutex.h>
#include <linux/capability.h>
#include <linux/semaphore.h>
#include <linux/fiemap.h>
#include <asm/atomic.h>
#include <asm/byteorder.h>
@ -942,6 +947,14 @@ struct lock_manager_operations {
int (*fl_change)(struct file_lock **, int);
};
struct lock_manager {
struct list_head list;
};
void locks_start_grace(struct lock_manager *);
void locks_end_grace(struct lock_manager *);
int locks_in_grace(void);
/* that will die - we need it for nfs_lock_info */
#include <linux/nfs_fs_i.h>
@ -983,6 +996,13 @@ struct file_lock {
#include <linux/fcntl.h>
extern void send_sigio(struct fown_struct *fown, int fd, int band);
/* fs/sync.c */
extern int do_sync_mapping_range(struct address_space *mapping, loff_t offset,
loff_t endbyte, unsigned int flags);
#ifdef CONFIG_FILE_LOCKING
extern int fcntl_getlk(struct file *, struct flock __user *);
extern int fcntl_setlk(unsigned int, struct file *, unsigned int,
struct flock __user *);
@ -993,14 +1013,9 @@ extern int fcntl_setlk64(unsigned int, struct file *, unsigned int,
struct flock64 __user *);
#endif
extern void send_sigio(struct fown_struct *fown, int fd, int band);
extern int fcntl_setlease(unsigned int fd, struct file *filp, long arg);
extern int fcntl_getlease(struct file *filp);
/* fs/sync.c */
extern int do_sync_mapping_range(struct address_space *mapping, loff_t offset,
loff_t endbyte, unsigned int flags);
/* fs/locks.c */
extern void locks_init_lock(struct file_lock *);
extern void locks_copy_lock(struct file_lock *, struct file_lock *);
@ -1023,6 +1038,37 @@ extern int lease_modify(struct file_lock **, int);
extern int lock_may_read(struct inode *, loff_t start, unsigned long count);
extern int lock_may_write(struct inode *, loff_t start, unsigned long count);
extern struct seq_operations locks_seq_operations;
#else /* !CONFIG_FILE_LOCKING */
#define fcntl_getlk(a, b) ({ -EINVAL; })
#define fcntl_setlk(a, b, c, d) ({ -EACCES; })
#if BITS_PER_LONG == 32
#define fcntl_getlk64(a, b) ({ -EINVAL; })
#define fcntl_setlk64(a, b, c, d) ({ -EACCES; })
#endif
#define fcntl_setlease(a, b, c) ({ 0; })
#define fcntl_getlease(a) ({ 0; })
#define locks_init_lock(a) ({ })
#define __locks_copy_lock(a, b) ({ })
#define locks_copy_lock(a, b) ({ })
#define locks_remove_posix(a, b) ({ })
#define locks_remove_flock(a) ({ })
#define posix_test_lock(a, b) ({ 0; })
#define posix_lock_file(a, b, c) ({ -ENOLCK; })
#define posix_lock_file_wait(a, b) ({ -ENOLCK; })
#define posix_unblock_lock(a, b) (-ENOENT)
#define vfs_test_lock(a, b) ({ 0; })
#define vfs_lock_file(a, b, c, d) (-ENOLCK)
#define vfs_cancel_lock(a, b) ({ 0; })
#define flock_lock_file_wait(a, b) ({ -ENOLCK; })
#define __break_lease(a, b) ({ 0; })
#define lease_get_mtime(a, b) ({ })
#define generic_setlease(a, b, c) ({ -EINVAL; })
#define vfs_setlease(a, b, c) ({ -EINVAL; })
#define lease_modify(a, b) ({ -EINVAL; })
#define lock_may_read(a, b, c) ({ 1; })
#define lock_may_write(a, b, c) ({ 1; })
#endif /* !CONFIG_FILE_LOCKING */
struct fasync_struct {
int magic;
@ -1178,6 +1224,20 @@ extern void dentry_unhash(struct dentry *dentry);
*/
extern int file_permission(struct file *, int);
/*
* VFS FS_IOC_FIEMAP helper definitions.
*/
struct fiemap_extent_info {
unsigned int fi_flags; /* Flags as passed from user */
unsigned int fi_extents_mapped; /* Number of mapped extents */
unsigned int fi_extents_max; /* Size of fiemap_extent array */
struct fiemap_extent *fi_extents_start; /* Start of fiemap_extent
* array */
};
int fiemap_fill_next_extent(struct fiemap_extent_info *info, u64 logical,
u64 phys, u64 len, u32 flags);
int fiemap_check_flags(struct fiemap_extent_info *fieinfo, u32 fs_flags);
/*
* File types
*
@ -1287,6 +1347,8 @@ struct inode_operations {
void (*truncate_range)(struct inode *, loff_t, loff_t);
long (*fallocate)(struct inode *inode, int mode, loff_t offset,
loff_t len);
int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 start,
u64 len);
};
struct seq_file;
@ -1554,9 +1616,12 @@ extern int vfs_statfs(struct dentry *, struct kstatfs *);
/* /sys/fs */
extern struct kobject *fs_kobj;
extern int rw_verify_area(int, struct file *, loff_t *, size_t);
#define FLOCK_VERIFY_READ 1
#define FLOCK_VERIFY_WRITE 2
#ifdef CONFIG_FILE_LOCKING
extern int locks_mandatory_locked(struct inode *);
extern int locks_mandatory_area(int, struct inode *, struct file *, loff_t, size_t);
@ -1587,8 +1652,6 @@ static inline int locks_verify_locked(struct inode *inode)
return 0;
}
extern int rw_verify_area(int, struct file *, loff_t *, size_t);
static inline int locks_verify_truncate(struct inode *inode,
struct file *filp,
loff_t size)
@ -1609,6 +1672,15 @@ static inline int break_lease(struct inode *inode, unsigned int mode)
return __break_lease(inode, mode);
return 0;
}
#else /* !CONFIG_FILE_LOCKING */
#define locks_mandatory_locked(a) ({ 0; })
#define locks_mandatory_area(a, b, c, d, e) ({ 0; })
#define __mandatory_lock(a) ({ 0; })
#define mandatory_lock(a) ({ 0; })
#define locks_verify_locked(a) ({ 0; })
#define locks_verify_truncate(a, b, c) ({ 0; })
#define break_lease(a, b) ({ 0; })
#endif /* CONFIG_FILE_LOCKING */
/* fs/open.c */
@ -1682,6 +1754,7 @@ extern void chrdev_show(struct seq_file *,off_t);
/* fs/block_dev.c */
#define BDEVNAME_SIZE 32 /* Largest string for a blockdev identifier */
#define BDEVT_SIZE 10 /* Largest string for MAJ:MIN for blkdev */
#ifdef CONFIG_BLOCK
#define BLKDEV_MAJOR_HASH_SIZE 255
@ -1718,6 +1791,9 @@ extern int fs_may_remount_ro(struct super_block *);
*/
#define bio_data_dir(bio) ((bio)->bi_rw & 1)
extern void check_disk_size_change(struct gendisk *disk,
struct block_device *bdev);
extern int revalidate_disk(struct gendisk *);
extern int check_disk_change(struct block_device *);
extern int __invalidate_device(struct block_device *);
extern int invalidate_partition(struct gendisk *, int);
@ -1980,6 +2056,9 @@ extern int vfs_fstat(unsigned int, struct kstat *);
extern int do_vfs_ioctl(struct file *filp, unsigned int fd, unsigned int cmd,
unsigned long arg);
extern int generic_block_fiemap(struct inode *inode,
struct fiemap_extent_info *fieinfo, u64 start,
u64 len, get_block_t *get_block);
extern void get_filesystem(struct file_system_type *fs);
extern void put_filesystem(struct file_system_type *fs);

371
include/linux/genhd.h
View file

@ -11,12 +11,15 @@
#include <linux/types.h>
#include <linux/kdev_t.h>
#include <linux/rcupdate.h>
#ifdef CONFIG_BLOCK
#define kobj_to_dev(k) container_of(k, struct device, kobj)
#define dev_to_disk(device) container_of(device, struct gendisk, dev)
#define dev_to_part(device) container_of(device, struct hd_struct, dev)
#define kobj_to_dev(k) container_of((k), struct device, kobj)
#define dev_to_disk(device) container_of((device), struct gendisk, part0.__dev)
#define dev_to_part(device) container_of((device), struct hd_struct, __dev)
#define disk_to_dev(disk) (&(disk)->part0.__dev)
#define part_to_dev(part) (&((part)->__dev))
extern struct device_type part_type;
extern struct kobject *block_depr;
@ -55,6 +58,9 @@ enum {
UNIXWARE_PARTITION = 0x63, /* Same as GNU_HURD and SCO Unix */
};
#define DISK_MAX_PARTS 256
#define DISK_NAME_LEN 32
#include <linux/major.h>
#include <linux/device.h>
#include <linux/smp.h>
@ -87,7 +93,7 @@ struct disk_stats {
struct hd_struct {
sector_t start_sect;
sector_t nr_sects;
struct device dev;
struct device __dev;
struct kobject *holder_dir;
int policy, partno;
#ifdef CONFIG_FAIL_MAKE_REQUEST
@ -100,6 +106,7 @@ struct hd_struct {
#else
struct disk_stats dkstats;
#endif
struct rcu_head rcu_head;
};
#define GENHD_FL_REMOVABLE 1
@ -108,100 +115,148 @@ struct hd_struct {
#define GENHD_FL_CD 8
#define GENHD_FL_UP 16
#define GENHD_FL_SUPPRESS_PARTITION_INFO 32
#define GENHD_FL_FAIL 64
#define GENHD_FL_EXT_DEVT 64 /* allow extended devt */
#define BLK_SCSI_MAX_CMDS (256)
#define BLK_SCSI_CMD_PER_LONG (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
struct blk_scsi_cmd_filter {
unsigned long read_ok[BLK_SCSI_CMD_PER_LONG];
unsigned long write_ok[BLK_SCSI_CMD_PER_LONG];
struct kobject kobj;
};
struct disk_part_tbl {
struct rcu_head rcu_head;
int len;
struct hd_struct *part[];
};
struct gendisk {
/* major, first_minor and minors are input parameters only,
* don't use directly. Use disk_devt() and disk_max_parts().
*/
int major; /* major number of driver */
int first_minor;
int minors; /* maximum number of minors, =1 for
* disks that can't be partitioned. */
char disk_name[32]; /* name of major driver */
struct hd_struct **part; /* [indexed by minor] */
char disk_name[DISK_NAME_LEN]; /* name of major driver */
/* Array of pointers to partitions indexed by partno.
* Protected with matching bdev lock but stat and other
* non-critical accesses use RCU. Always access through
* helpers.
*/
struct disk_part_tbl *part_tbl;
struct hd_struct part0;
struct block_device_operations *fops;
struct request_queue *queue;
void *private_data;
sector_t capacity;
int flags;
struct device *driverfs_dev; // FIXME: remove
struct device dev;
struct kobject *holder_dir;
struct kobject *slave_dir;
struct timer_rand_state *random;
int policy;
atomic_t sync_io; /* RAID */
unsigned long stamp;
int in_flight;
#ifdef CONFIG_SMP
struct disk_stats *dkstats;
#else
struct disk_stats dkstats;
#endif
struct work_struct async_notify;
#ifdef CONFIG_BLK_DEV_INTEGRITY
struct blk_integrity *integrity;
#endif
int node_id;
};
/*
* Macros to operate on percpu disk statistics:
*
* The __ variants should only be called in critical sections. The full
* variants disable/enable preemption.
*/
static inline struct hd_struct *get_part(struct gendisk *gendiskp,
sector_t sector)
static inline struct gendisk *part_to_disk(struct hd_struct *part)
{
struct hd_struct *part;
int i;
for (i = 0; i < gendiskp->minors - 1; i++) {
part = gendiskp->part[i];
if (part && part->start_sect <= sector
&& sector < part->start_sect + part->nr_sects)
return part;
if (likely(part)) {
if (part->partno)
return dev_to_disk(part_to_dev(part)->parent);
else
return dev_to_disk(part_to_dev(part));
}
return NULL;
}
static inline int disk_max_parts(struct gendisk *disk)
{
if (disk->flags & GENHD_FL_EXT_DEVT)
return DISK_MAX_PARTS;
return disk->minors;
}
static inline bool disk_partitionable(struct gendisk *disk)
{
return disk_max_parts(disk) > 1;
}
static inline dev_t disk_devt(struct gendisk *disk)
{
return disk_to_dev(disk)->devt;
}
static inline dev_t part_devt(struct hd_struct *part)
{
return part_to_dev(part)->devt;
}
extern struct hd_struct *disk_get_part(struct gendisk *disk, int partno);
static inline void disk_put_part(struct hd_struct *part)
{
if (likely(part))
put_device(part_to_dev(part));
}
/*
* Smarter partition iterator without context limits.
*/
#define DISK_PITER_REVERSE (1 << 0) /* iterate in the reverse direction */
#define DISK_PITER_INCL_EMPTY (1 << 1) /* include 0-sized parts */
#define DISK_PITER_INCL_PART0 (1 << 2) /* include partition 0 */
struct disk_part_iter {
struct gendisk *disk;
struct hd_struct *part;
int idx;
unsigned int flags;
};
extern void disk_part_iter_init(struct disk_part_iter *piter,
struct gendisk *disk, unsigned int flags);
extern struct hd_struct *disk_part_iter_next(struct disk_part_iter *piter);
extern void disk_part_iter_exit(struct disk_part_iter *piter);
extern struct hd_struct *disk_map_sector_rcu(struct gendisk *disk,
sector_t sector);
/*
* Macros to operate on percpu disk statistics:
*
* {disk|part|all}_stat_{add|sub|inc|dec}() modify the stat counters
* and should be called between disk_stat_lock() and
* disk_stat_unlock().
*
* part_stat_read() can be called at any time.
*
* part_stat_{add|set_all}() and {init|free}_part_stats are for
* internal use only.
*/
#ifdef CONFIG_SMP
#define __disk_stat_add(gendiskp, field, addnd) \
(per_cpu_ptr(gendiskp->dkstats, smp_processor_id())->field += addnd)
#define part_stat_lock() ({ rcu_read_lock(); get_cpu(); })
#define part_stat_unlock() do { put_cpu(); rcu_read_unlock(); } while (0)
#define disk_stat_read(gendiskp, field) \
({ \
typeof(gendiskp->dkstats->field) res = 0; \
int i; \
for_each_possible_cpu(i) \
res += per_cpu_ptr(gendiskp->dkstats, i)->field; \
res; \
})
static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) {
int i;
for_each_possible_cpu(i)
memset(per_cpu_ptr(gendiskp->dkstats, i), value,
sizeof(struct disk_stats));
}
#define __part_stat_add(part, field, addnd) \
(per_cpu_ptr(part->dkstats, smp_processor_id())->field += addnd)
#define __all_stat_add(gendiskp, part, field, addnd, sector) \
({ \
if (part) \
__part_stat_add(part, field, addnd); \
__disk_stat_add(gendiskp, field, addnd); \
})
#define __part_stat_add(cpu, part, field, addnd) \
(per_cpu_ptr((part)->dkstats, (cpu))->field += (addnd))
#define part_stat_read(part, field) \
({ \
typeof(part->dkstats->field) res = 0; \
typeof((part)->dkstats->field) res = 0; \
int i; \
for_each_possible_cpu(i) \
res += per_cpu_ptr(part->dkstats, i)->field; \
res += per_cpu_ptr((part)->dkstats, i)->field; \
res; \
})
@ -213,108 +268,6 @@ static inline void part_stat_set_all(struct hd_struct *part, int value)
memset(per_cpu_ptr(part->dkstats, i), value,
sizeof(struct disk_stats));
}
#else /* !CONFIG_SMP */
#define __disk_stat_add(gendiskp, field, addnd) \
(gendiskp->dkstats.field += addnd)
#define disk_stat_read(gendiskp, field) (gendiskp->dkstats.field)
static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)
{
memset(&gendiskp->dkstats, value, sizeof (struct disk_stats));
}
#define __part_stat_add(part, field, addnd) \
(part->dkstats.field += addnd)
#define __all_stat_add(gendiskp, part, field, addnd, sector) \
({ \
if (part) \
part->dkstats.field += addnd; \
__disk_stat_add(gendiskp, field, addnd); \
})
#define part_stat_read(part, field) (part->dkstats.field)
static inline void part_stat_set_all(struct hd_struct *part, int value)
{
memset(&part->dkstats, value, sizeof(struct disk_stats));
}
#endif /* CONFIG_SMP */
#define disk_stat_add(gendiskp, field, addnd) \
do { \
preempt_disable(); \
__disk_stat_add(gendiskp, field, addnd); \
preempt_enable(); \
} while (0)
#define __disk_stat_dec(gendiskp, field) __disk_stat_add(gendiskp, field, -1)
#define disk_stat_dec(gendiskp, field) disk_stat_add(gendiskp, field, -1)
#define __disk_stat_inc(gendiskp, field) __disk_stat_add(gendiskp, field, 1)
#define disk_stat_inc(gendiskp, field) disk_stat_add(gendiskp, field, 1)
#define __disk_stat_sub(gendiskp, field, subnd) \
__disk_stat_add(gendiskp, field, -subnd)
#define disk_stat_sub(gendiskp, field, subnd) \
disk_stat_add(gendiskp, field, -subnd)
#define part_stat_add(gendiskp, field, addnd) \
do { \
preempt_disable(); \
__part_stat_add(gendiskp, field, addnd);\
preempt_enable(); \
} while (0)
#define __part_stat_dec(gendiskp, field) __part_stat_add(gendiskp, field, -1)
#define part_stat_dec(gendiskp, field) part_stat_add(gendiskp, field, -1)
#define __part_stat_inc(gendiskp, field) __part_stat_add(gendiskp, field, 1)
#define part_stat_inc(gendiskp, field) part_stat_add(gendiskp, field, 1)
#define __part_stat_sub(gendiskp, field, subnd) \
__part_stat_add(gendiskp, field, -subnd)
#define part_stat_sub(gendiskp, field, subnd) \
part_stat_add(gendiskp, field, -subnd)
#define all_stat_add(gendiskp, part, field, addnd, sector) \
do { \
preempt_disable(); \
__all_stat_add(gendiskp, part, field, addnd, sector); \
preempt_enable(); \
} while (0)
#define __all_stat_dec(gendiskp, field, sector) \
__all_stat_add(gendiskp, field, -1, sector)
#define all_stat_dec(gendiskp, field, sector) \
all_stat_add(gendiskp, field, -1, sector)
#define __all_stat_inc(gendiskp, part, field, sector) \
__all_stat_add(gendiskp, part, field, 1, sector)
#define all_stat_inc(gendiskp, part, field, sector) \
all_stat_add(gendiskp, part, field, 1, sector)
#define __all_stat_sub(gendiskp, part, field, subnd, sector) \
__all_stat_add(gendiskp, part, field, -subnd, sector)
#define all_stat_sub(gendiskp, part, field, subnd, sector) \
all_stat_add(gendiskp, part, field, -subnd, sector)
/* Inlines to alloc and free disk stats in struct gendisk */
#ifdef CONFIG_SMP
static inline int init_disk_stats(struct gendisk *disk)
{
disk->dkstats = alloc_percpu(struct disk_stats);
if (!disk->dkstats)
return 0;
return 1;
}
static inline void free_disk_stats(struct gendisk *disk)
{
free_percpu(disk->dkstats);
}
static inline int init_part_stats(struct hd_struct *part)
{
@ -329,14 +282,18 @@ static inline void free_part_stats(struct hd_struct *part)
free_percpu(part->dkstats);
}
#else /* CONFIG_SMP */
static inline int init_disk_stats(struct gendisk *disk)
{
return 1;
}
#else /* !CONFIG_SMP */
#define part_stat_lock() ({ rcu_read_lock(); 0; })
#define part_stat_unlock() rcu_read_unlock()
static inline void free_disk_stats(struct gendisk *disk)
#define __part_stat_add(cpu, part, field, addnd) \
((part)->dkstats.field += addnd)
#define part_stat_read(part, field) ((part)->dkstats.field)
static inline void part_stat_set_all(struct hd_struct *part, int value)
{
memset(&part->dkstats, value, sizeof(struct disk_stats));
}
static inline int init_part_stats(struct hd_struct *part)
@ -347,37 +304,71 @@ static inline int init_part_stats(struct hd_struct *part)
static inline void free_part_stats(struct hd_struct *part)
{
}
#endif /* CONFIG_SMP */
#endif /* CONFIG_SMP */
#define part_stat_add(cpu, part, field, addnd) do { \
__part_stat_add((cpu), (part), field, addnd); \
if ((part)->partno) \
__part_stat_add((cpu), &part_to_disk((part))->part0, \
field, addnd); \
} while (0)
#define part_stat_dec(cpu, gendiskp, field) \
part_stat_add(cpu, gendiskp, field, -1)
#define part_stat_inc(cpu, gendiskp, field) \
part_stat_add(cpu, gendiskp, field, 1)
#define part_stat_sub(cpu, gendiskp, field, subnd) \
part_stat_add(cpu, gendiskp, field, -subnd)
static inline void part_inc_in_flight(struct hd_struct *part)
{
part->in_flight++;
if (part->partno)
part_to_disk(part)->part0.in_flight++;
}
static inline void part_dec_in_flight(struct hd_struct *part)
{
part->in_flight--;
if (part->partno)
part_to_disk(part)->part0.in_flight--;
}
/* drivers/block/ll_rw_blk.c */
extern void disk_round_stats(struct gendisk *disk);
extern void part_round_stats(struct hd_struct *part);
extern void part_round_stats(int cpu, struct hd_struct *part);
/* drivers/block/genhd.c */
extern int get_blkdev_list(char *, int);
extern void add_disk(struct gendisk *disk);
extern void del_gendisk(struct gendisk *gp);
extern void unlink_gendisk(struct gendisk *gp);
extern struct gendisk *get_gendisk(dev_t dev, int *part);
extern struct gendisk *get_gendisk(dev_t dev, int *partno);
extern struct block_device *bdget_disk(struct gendisk *disk, int partno);
extern void set_device_ro(struct block_device *bdev, int flag);
extern void set_disk_ro(struct gendisk *disk, int flag);
static inline int get_disk_ro(struct gendisk *disk)
{
return disk->part0.policy;
}
/* drivers/char/random.c */
extern void add_disk_randomness(struct gendisk *disk);
extern void rand_initialize_disk(struct gendisk *disk);
static inline sector_t get_start_sect(struct block_device *bdev)
{
return bdev->bd_contains == bdev ? 0 : bdev->bd_part->start_sect;
return bdev->bd_part->start_sect;
}
static inline sector_t get_capacity(struct gendisk *disk)
{
return disk->capacity;
return disk->part0.nr_sects;
}
static inline void set_capacity(struct gendisk *disk, sector_t size)
{
disk->capacity = size;
disk->part0.nr_sects = size;
}
#ifdef CONFIG_SOLARIS_X86_PARTITION
@ -527,9 +518,12 @@ struct unixware_disklabel {
#define ADDPART_FLAG_RAID 1
#define ADDPART_FLAG_WHOLEDISK 2
extern dev_t blk_lookup_devt(const char *name, int part);
extern char *disk_name (struct gendisk *hd, int part, char *buf);
extern int blk_alloc_devt(struct hd_struct *part, dev_t *devt);
extern void blk_free_devt(dev_t devt);
extern dev_t blk_lookup_devt(const char *name, int partno);
extern char *disk_name (struct gendisk *hd, int partno, char *buf);
extern int disk_expand_part_tbl(struct gendisk *disk, int target);
extern int rescan_partitions(struct gendisk *disk, struct block_device *bdev);
extern int __must_check add_partition(struct gendisk *, int, sector_t, sector_t, int);
extern void delete_partition(struct gendisk *, int);
@ -546,16 +540,23 @@ extern void blk_register_region(dev_t devt, unsigned long range,
void *data);
extern void blk_unregister_region(dev_t devt, unsigned long range);
static inline struct block_device *bdget_disk(struct gendisk *disk, int index)
{
return bdget(MKDEV(disk->major, disk->first_minor) + index);
}
extern ssize_t part_size_show(struct device *dev,
struct device_attribute *attr, char *buf);
extern ssize_t part_stat_show(struct device *dev,
struct device_attribute *attr, char *buf);
#ifdef CONFIG_FAIL_MAKE_REQUEST
extern ssize_t part_fail_show(struct device *dev,
struct device_attribute *attr, char *buf);
extern ssize_t part_fail_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count);
#endif /* CONFIG_FAIL_MAKE_REQUEST */
#else /* CONFIG_BLOCK */
static inline void printk_all_partitions(void) { }
static inline dev_t blk_lookup_devt(const char *name, int part)
static inline dev_t blk_lookup_devt(const char *name, int partno)
{
dev_t devt = MKDEV(0, 0);
return devt;

6
include/linux/gfs2_ondisk.h
View file

@ -118,7 +118,11 @@ struct gfs2_sb {
char sb_lockproto[GFS2_LOCKNAME_LEN];
char sb_locktable[GFS2_LOCKNAME_LEN];
/* In gfs1, quota and license dinodes followed */
struct gfs2_inum __pad3; /* Was quota inode in gfs1 */
struct gfs2_inum __pad4; /* Was licence inode in gfs1 */
#define GFS2_HAS_UUID 1
__u8 sb_uuid[16]; /* The UUID, maybe 0 for backwards compat */
};
/*

14
include/linux/hpet.h
View file

@ -37,6 +37,7 @@ struct hpet {
#define hpet_compare _u1._hpet_compare
#define HPET_MAX_TIMERS (32)
#define HPET_MAX_IRQ (32)
/*
* HPET general capabilities register
@ -64,7 +65,7 @@ struct hpet {
*/
#define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL)
#define Tn_INI_ROUTE_CAP_SHIFT (32UL)
#define Tn_INT_ROUTE_CAP_SHIFT (32UL)
#define Tn_FSB_INT_DELCAP_MASK (0x8000UL)
#define Tn_FSB_INT_DELCAP_SHIFT (15)
#define Tn_FSB_EN_CNF_MASK (0x4000UL)
@ -91,23 +92,14 @@ struct hpet {
* exported interfaces
*/
struct hpet_task {
void (*ht_func) (void *);
void *ht_data;
void *ht_opaque;
};
struct hpet_data {
unsigned long hd_phys_address;
void __iomem *hd_address;
unsigned short hd_nirqs;
unsigned short hd_flags;
unsigned int hd_state; /* timer allocated */
unsigned int hd_irq[HPET_MAX_TIMERS];
};
#define HPET_DATA_PLATFORM 0x0001 /* platform call to hpet_alloc */
static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
{
hd->hd_state |= (1 << timer);
@ -125,7 +117,7 @@ struct hpet_info {
unsigned short hi_timer;
};
#define HPET_INFO_PERIODIC 0x0001 /* timer is periodic */
#define HPET_INFO_PERIODIC 0x0010 /* periodic-capable comparator */
#define HPET_IE_ON _IO('h', 0x01) /* interrupt on */
#define HPET_IE_OFF _IO('h', 0x02) /* interrupt off */

18
include/linux/hrtimer.h
View file

@ -47,14 +47,22 @@ enum hrtimer_restart {
* HRTIMER_CB_IRQSAFE: Callback may run in hardirq context
* HRTIMER_CB_IRQSAFE_NO_RESTART: Callback may run in hardirq context and
* does not restart the timer
* HRTIMER_CB_IRQSAFE_NO_SOFTIRQ: Callback must run in hardirq context
* Special mode for tick emultation
* HRTIMER_CB_IRQSAFE_PERCPU: Callback must run in hardirq context
* Special mode for tick emulation and
* scheduler timer. Such timers are per
* cpu and not allowed to be migrated on
* cpu unplug.
* HRTIMER_CB_IRQSAFE_UNLOCKED: Callback should run in hardirq context
* with timer->base lock unlocked
* used for timers which call wakeup to
* avoid lock order problems with rq->lock
*/
enum hrtimer_cb_mode {
HRTIMER_CB_SOFTIRQ,
HRTIMER_CB_IRQSAFE,
HRTIMER_CB_IRQSAFE_NO_RESTART,
HRTIMER_CB_IRQSAFE_NO_SOFTIRQ,
HRTIMER_CB_IRQSAFE_PERCPU,
HRTIMER_CB_IRQSAFE_UNLOCKED,
};
/*
@ -67,9 +75,10 @@ enum hrtimer_cb_mode {
* 0x02 callback function running
* 0x04 callback pending (high resolution mode)
*
* Special case:
* Special cases:
* 0x03 callback function running and enqueued
* (was requeued on another CPU)
* 0x09 timer was migrated on CPU hotunplug
* The "callback function running and enqueued" status is only possible on
* SMP. It happens for example when a posix timer expired and the callback
* queued a signal. Between dropping the lock which protects the posix timer
@ -87,6 +96,7 @@ enum hrtimer_cb_mode {
#define HRTIMER_STATE_ENQUEUED 0x01
#define HRTIMER_STATE_CALLBACK 0x02
#define HRTIMER_STATE_PENDING 0x04
#define HRTIMER_STATE_MIGRATE 0x08
/**
* struct hrtimer - the basic hrtimer structure

1
include/linux/i2c-id.h
View file

@ -41,7 +41,6 @@
#define I2C_DRIVERID_SAA7110 22 /* video decoder */
#define I2C_DRIVERID_SAA5249 24 /* SAA5249 and compatibles */
#define I2C_DRIVERID_PCF8583 25 /* real time clock */
#define I2C_DRIVERID_SAB3036 26 /* SAB3036 tuner */
#define I2C_DRIVERID_TDA7432 27 /* Stereo sound processor */
#define I2C_DRIVERID_TVMIXER 28 /* Mixer driver for tv cards */
#define I2C_DRIVERID_TVAUDIO 29 /* Generic TV sound driver */

1629
include/linux/ide.h
View file

File diff suppressed because it is too large Load diff

36
include/linux/ieee80211.h
View file

@ -471,6 +471,11 @@ struct ieee80211s_hdr {
u8 eaddr3[6];
} __attribute__ ((packed));
/* Mesh flags */
#define MESH_FLAGS_AE_A4 0x1
#define MESH_FLAGS_AE_A5_A6 0x2
#define MESH_FLAGS_PS_DEEP 0x4
/**
* struct ieee80211_quiet_ie
*
@ -643,6 +648,9 @@ struct ieee80211_mgmt {
} u;
} __attribute__ ((packed));
/* mgmt header + 1 byte category code */
#define IEEE80211_MIN_ACTION_SIZE offsetof(struct ieee80211_mgmt, u.action.u)
/* Control frames */
struct ieee80211_rts {
@ -708,12 +716,13 @@ struct ieee80211_ht_addt_info {
/* 802.11n HT capabilities masks */
#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002
#define IEEE80211_HT_CAP_MIMO_PS 0x000C
#define IEEE80211_HT_CAP_SM_PS 0x000C
#define IEEE80211_HT_CAP_GRN_FLD 0x0010
#define IEEE80211_HT_CAP_SGI_20 0x0020
#define IEEE80211_HT_CAP_SGI_40 0x0040
#define IEEE80211_HT_CAP_DELAY_BA 0x0400
#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800
#define IEEE80211_HT_CAP_DSSSCCK40 0x1000
/* 802.11n HT capability AMPDU settings */
#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03
#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C
@ -736,11 +745,26 @@ struct ieee80211_ht_addt_info {
#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004
#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010
/* MIMO Power Save Modes */
#define WLAN_HT_CAP_MIMO_PS_STATIC 0
#define WLAN_HT_CAP_MIMO_PS_DYNAMIC 1
#define WLAN_HT_CAP_MIMO_PS_INVALID 2
#define WLAN_HT_CAP_MIMO_PS_DISABLED 3
/* block-ack parameters */
#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C
#define IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0
#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000
#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800
/*
* A-PMDU buffer sizes
* According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
*/
#define IEEE80211_MIN_AMPDU_BUF 0x8
#define IEEE80211_MAX_AMPDU_BUF 0x40
/* Spatial Multiplexing Power Save Modes */
#define WLAN_HT_CAP_SM_PS_STATIC 0
#define WLAN_HT_CAP_SM_PS_DYNAMIC 1
#define WLAN_HT_CAP_SM_PS_INVALID 2
#define WLAN_HT_CAP_SM_PS_DISABLED 3
/* Authentication algorithms */
#define WLAN_AUTH_OPEN 0

1
include/linux/if.h
View file

@ -24,6 +24,7 @@
#include <linux/compiler.h> /* for "__user" et al */
#define IFNAMSIZ 16
#define IFALIASZ 256
#include <linux/hdlc/ioctl.h>
/* Standard interface flags (netdevice->flags). */

8
include/linux/if_ether.h
View file

@ -9,7 +9,7 @@
*
* Author: Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
* Donald Becker, <becker@super.org>
* Alan Cox, <alan@redhat.com>
* Alan Cox, <alan@lxorguk.ukuu.org.uk>
* Steve Whitehouse, <gw7rrm@eeshack3.swan.ac.uk>
*
* This program is free software; you can redistribute it and/or
@ -56,6 +56,7 @@
#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */
#define ETH_P_CUST 0x6006 /* DEC Customer use */
#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */
#define ETH_P_TEB 0x6558 /* Trans Ether Bridging */
#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */
#define ETH_P_ATALK 0x809B /* Appletalk DDP */
#define ETH_P_AARP 0x80F3 /* Appletalk AARP */
@ -74,8 +75,10 @@
#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport
* over Ethernet
*/
#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
#define ETH_P_AOE 0x88A2 /* ATA over Ethernet */
#define ETH_P_TIPC 0x88CA /* TIPC */
#define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
/*
* Non DIX types. Won't clash for 1500 types.
@ -99,6 +102,9 @@
#define ETH_P_ECONET 0x0018 /* Acorn Econet */
#define ETH_P_HDLC 0x0019 /* HDLC frames */
#define ETH_P_ARCNET 0x001A /* 1A for ArcNet :-) */
#define ETH_P_DSA 0x001B /* Distributed Switch Arch. */
#define ETH_P_TRAILER 0x001C /* Trailer switch tagging */
#define ETH_P_PHONET 0x00F5 /* Nokia Phonet frames */
/*
* This is an Ethernet frame header.

2
include/linux/if_fddi.h
View file

@ -12,7 +12,7 @@
* if_fddi.h is based on previous if_ether.h and if_tr.h work by
* Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
* Donald Becker, <becker@super.org>
* Alan Cox, <alan@redhat.com>
* Alan Cox, <alan@lxorguk.ukuu.org.uk>
* Steve Whitehouse, <gw7rrm@eeshack3.swan.ac.uk>
* Peter De Schrijver, <stud11@cc4.kuleuven.ac.be>
*

2
include/linux/if_hippi.h
View file

@ -9,7 +9,7 @@
*
* Author: Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
* Donald Becker, <becker@super.org>
* Alan Cox, <alan@redhat.com>
* Alan Cox, <alan@lxorguk.ukuu.org.uk>
* Steve Whitehouse, <gw7rrm@eeshack3.swan.ac.uk>
* Jes Sorensen, <Jes.Sorensen@cern.ch>
*

1
include/linux/if_link.h
View file

@ -79,6 +79,7 @@ enum
IFLA_LINKINFO,
#define IFLA_LINKINFO IFLA_LINKINFO
IFLA_NET_NS_PID,
IFLA_IFALIAS,
__IFLA_MAX
};

19
include/linux/if_phonet.h Normal file
View file

@ -0,0 +1,19 @@
/*
* File: if_phonet.h
*
* Phonet interface kernel definitions
*
* Copyright (C) 2008 Nokia Corporation. All rights reserved.
*/
#ifndef LINUX_IF_PHONET_H
#define LINUX_IF_PHONET_H
#define PHONET_MIN_MTU 6 /* pn_length = 0 */
#define PHONET_MAX_MTU 65541 /* pn_length = 0xffff */
#define PHONET_DEV_MTU PHONET_MAX_MTU
#ifdef __KERNEL__
extern struct header_ops phonet_header_ops;
#endif
#endif

19
include/linux/if_tunnel.h
View file

@ -2,6 +2,7 @@
#define _IF_TUNNEL_H_
#include <linux/types.h>
#include <linux/ip.h>
#define SIOCGETTUNNEL (SIOCDEVPRIVATE + 0)
#define SIOCADDTUNNEL (SIOCDEVPRIVATE + 1)
@ -47,4 +48,22 @@ struct ip_tunnel_prl {
/* PRL flags */
#define PRL_DEFAULT 0x0001
enum
{
IFLA_GRE_UNSPEC,
IFLA_GRE_LINK,
IFLA_GRE_IFLAGS,
IFLA_GRE_OFLAGS,
IFLA_GRE_IKEY,
IFLA_GRE_OKEY,
IFLA_GRE_LOCAL,
IFLA_GRE_REMOTE,
IFLA_GRE_TTL,
IFLA_GRE_TOS,
IFLA_GRE_PMTUDISC,
__IFLA_GRE_MAX,
};
#define IFLA_GRE_MAX (__IFLA_GRE_MAX - 1)
#endif /* _IF_TUNNEL_H_ */

2
include/linux/igmp.h
View file

@ -2,7 +2,7 @@
* Linux NET3: Internet Group Management Protocol [IGMP]
*
* Authors:
* Alan Cox <Alan.Cox@linux.org>
* Alan Cox <alan@lxorguk.ukuu.org.uk>
*
* Extended to talk the BSD extended IGMP protocol of mrouted 3.6
*

1
include/linux/in.h
View file

@ -75,6 +75,7 @@ struct in_addr {
#define IP_IPSEC_POLICY 16
#define IP_XFRM_POLICY 17
#define IP_PASSSEC 18
#define IP_TRANSPARENT 19
/* BSD compatibility */
#define IP_RECVRETOPTS IP_RETOPTS

1
include/linux/inetdevice.h
View file

@ -25,6 +25,7 @@ struct in_device
struct in_ifaddr *ifa_list; /* IP ifaddr chain */
rwlock_t mc_list_lock;
struct ip_mc_list *mc_list; /* IP multicast filter chain */
int mc_count; /* Number of installed mcasts */
spinlock_t mc_tomb_lock;
struct ip_mc_list *mc_tomb;
unsigned long mr_v1_seen;

16
include/linux/iommu-helper.h
View file

@ -1,6 +1,20 @@
#ifndef _LINUX_IOMMU_HELPER_H
#define _LINUX_IOMMU_HELPER_H
static inline unsigned long iommu_device_max_index(unsigned long size,
unsigned long offset,
u64 dma_mask)
{
if (size + offset > dma_mask)
return dma_mask - offset + 1;
else
return size;
}
extern int iommu_is_span_boundary(unsigned int index, unsigned int nr,
unsigned long shift,
unsigned long boundary_size);
extern void iommu_area_reserve(unsigned long *map, unsigned long i, int len);
extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
unsigned long start, unsigned int nr,
unsigned long shift,
@ -8,3 +22,5 @@ extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
unsigned long align_mask);
extern void iommu_area_free(unsigned long *map, unsigned long start,
unsigned int nr);
#endif

7
include/linux/ioport.h
View file

@ -108,6 +108,9 @@ extern struct resource iomem_resource;
extern int request_resource(struct resource *root, struct resource *new);
extern int release_resource(struct resource *new);
extern void reserve_region_with_split(struct resource *root,
resource_size_t start, resource_size_t end,
const char *name);
extern int insert_resource(struct resource *parent, struct resource *new);
extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new);
extern int allocate_resource(struct resource *root, struct resource *new,
@ -159,9 +162,9 @@ extern struct resource * __devm_request_region(struct device *dev,
struct resource *parent, resource_size_t start,
resource_size_t n, const char *name);
#define devm_release_region(start,n) \
#define devm_release_region(dev, start, n) \
__devm_release_region(dev, &ioport_resource, (start), (n))
#define devm_release_mem_region(start,n) \
#define devm_release_mem_region(dev, start, n) \
__devm_release_region(dev, &iomem_resource, (start), (n))
extern void __devm_release_region(struct device *dev, struct resource *parent,

160
include/linux/ip_vs.h
View file

@ -242,4 +242,164 @@ struct ip_vs_daemon_user {
int syncid;
};
/*
*
* IPVS Generic Netlink interface definitions
*
*/
/* Generic Netlink family info */
#define IPVS_GENL_NAME "IPVS"
#define IPVS_GENL_VERSION 0x1
struct ip_vs_flags {
__be32 flags;
__be32 mask;
};
/* Generic Netlink command attributes */
enum {
IPVS_CMD_UNSPEC = 0,
IPVS_CMD_NEW_SERVICE, /* add service */
IPVS_CMD_SET_SERVICE, /* modify service */
IPVS_CMD_DEL_SERVICE, /* delete service */
IPVS_CMD_GET_SERVICE, /* get service info */
IPVS_CMD_NEW_DEST, /* add destination */
IPVS_CMD_SET_DEST, /* modify destination */
IPVS_CMD_DEL_DEST, /* delete destination */
IPVS_CMD_GET_DEST, /* get destination info */
IPVS_CMD_NEW_DAEMON, /* start sync daemon */
IPVS_CMD_DEL_DAEMON, /* stop sync daemon */
IPVS_CMD_GET_DAEMON, /* get sync daemon status */
IPVS_CMD_SET_CONFIG, /* set config settings */
IPVS_CMD_GET_CONFIG, /* get config settings */
IPVS_CMD_SET_INFO, /* only used in GET_INFO reply */
IPVS_CMD_GET_INFO, /* get general IPVS info */
IPVS_CMD_ZERO, /* zero all counters and stats */
IPVS_CMD_FLUSH, /* flush services and dests */
__IPVS_CMD_MAX,
};
#define IPVS_CMD_MAX (__IPVS_CMD_MAX - 1)
/* Attributes used in the first level of commands */
enum {
IPVS_CMD_ATTR_UNSPEC = 0,
IPVS_CMD_ATTR_SERVICE, /* nested service attribute */
IPVS_CMD_ATTR_DEST, /* nested destination attribute */
IPVS_CMD_ATTR_DAEMON, /* nested sync daemon attribute */
IPVS_CMD_ATTR_TIMEOUT_TCP, /* TCP connection timeout */
IPVS_CMD_ATTR_TIMEOUT_TCP_FIN, /* TCP FIN wait timeout */
IPVS_CMD_ATTR_TIMEOUT_UDP, /* UDP timeout */
__IPVS_CMD_ATTR_MAX,
};
#define IPVS_CMD_ATTR_MAX (__IPVS_SVC_ATTR_MAX - 1)
/*
* Attributes used to describe a service
*
* Used inside nested attribute IPVS_CMD_ATTR_SERVICE
*/
enum {
IPVS_SVC_ATTR_UNSPEC = 0,
IPVS_SVC_ATTR_AF, /* address family */
IPVS_SVC_ATTR_PROTOCOL, /* virtual service protocol */
IPVS_SVC_ATTR_ADDR, /* virtual service address */
IPVS_SVC_ATTR_PORT, /* virtual service port */
IPVS_SVC_ATTR_FWMARK, /* firewall mark of service */
IPVS_SVC_ATTR_SCHED_NAME, /* name of scheduler */
IPVS_SVC_ATTR_FLAGS, /* virtual service flags */
IPVS_SVC_ATTR_TIMEOUT, /* persistent timeout */
IPVS_SVC_ATTR_NETMASK, /* persistent netmask */
IPVS_SVC_ATTR_STATS, /* nested attribute for service stats */
__IPVS_SVC_ATTR_MAX,
};
#define IPVS_SVC_ATTR_MAX (__IPVS_SVC_ATTR_MAX - 1)
/*
* Attributes used to describe a destination (real server)
*
* Used inside nested attribute IPVS_CMD_ATTR_DEST
*/
enum {
IPVS_DEST_ATTR_UNSPEC = 0,
IPVS_DEST_ATTR_ADDR, /* real server address */
IPVS_DEST_ATTR_PORT, /* real server port */
IPVS_DEST_ATTR_FWD_METHOD, /* forwarding method */
IPVS_DEST_ATTR_WEIGHT, /* destination weight */
IPVS_DEST_ATTR_U_THRESH, /* upper threshold */
IPVS_DEST_ATTR_L_THRESH, /* lower threshold */
IPVS_DEST_ATTR_ACTIVE_CONNS, /* active connections */
IPVS_DEST_ATTR_INACT_CONNS, /* inactive connections */
IPVS_DEST_ATTR_PERSIST_CONNS, /* persistent connections */
IPVS_DEST_ATTR_STATS, /* nested attribute for dest stats */
__IPVS_DEST_ATTR_MAX,
};
#define IPVS_DEST_ATTR_MAX (__IPVS_DEST_ATTR_MAX - 1)
/*
* Attributes describing a sync daemon
*
* Used inside nested attribute IPVS_CMD_ATTR_DAEMON
*/
enum {
IPVS_DAEMON_ATTR_UNSPEC = 0,
IPVS_DAEMON_ATTR_STATE, /* sync daemon state (master/backup) */
IPVS_DAEMON_ATTR_MCAST_IFN, /* multicast interface name */
IPVS_DAEMON_ATTR_SYNC_ID, /* SyncID we belong to */
__IPVS_DAEMON_ATTR_MAX,
};
#define IPVS_DAEMON_ATTR_MAX (__IPVS_DAEMON_ATTR_MAX - 1)
/*
* Attributes used to describe service or destination entry statistics
*
* Used inside nested attributes IPVS_SVC_ATTR_STATS and IPVS_DEST_ATTR_STATS
*/
enum {
IPVS_STATS_ATTR_UNSPEC = 0,
IPVS_STATS_ATTR_CONNS, /* connections scheduled */
IPVS_STATS_ATTR_INPKTS, /* incoming packets */
IPVS_STATS_ATTR_OUTPKTS, /* outgoing packets */
IPVS_STATS_ATTR_INBYTES, /* incoming bytes */
IPVS_STATS_ATTR_OUTBYTES, /* outgoing bytes */
IPVS_STATS_ATTR_CPS, /* current connection rate */
IPVS_STATS_ATTR_INPPS, /* current in packet rate */
IPVS_STATS_ATTR_OUTPPS, /* current out packet rate */
IPVS_STATS_ATTR_INBPS, /* current in byte rate */
IPVS_STATS_ATTR_OUTBPS, /* current out byte rate */
__IPVS_STATS_ATTR_MAX,
};
#define IPVS_STATS_ATTR_MAX (__IPVS_STATS_ATTR_MAX - 1)
/* Attributes used in response to IPVS_CMD_GET_INFO command */
enum {
IPVS_INFO_ATTR_UNSPEC = 0,
IPVS_INFO_ATTR_VERSION, /* IPVS version number */
IPVS_INFO_ATTR_CONN_TAB_SIZE, /* size of connection hash table */
__IPVS_INFO_ATTR_MAX,
};
#define IPVS_INFO_ATTR_MAX (__IPVS_INFO_ATTR_MAX - 1)
#endif /* _IP_VS_H */

1
include/linux/irq.h
View file

@ -62,6 +62,7 @@ typedef void (*irq_flow_handler_t)(unsigned int irq,
#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
#ifdef CONFIG_IRQ_PER_CPU
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)

2
include/linux/isdn_ppp.h
View file

@ -157,7 +157,7 @@ typedef struct {
typedef struct {
int mp_mrru; /* unused */
struct sk_buff * frags; /* fragments sl list -- use skb->next */
struct sk_buff_head frags; /* fragments sl list */
long frames; /* number of frames in the frame list */
unsigned int seq; /* last processed packet seq #: any packets
* with smaller seq # will be dropped

1
include/linux/ivtv.h
View file

@ -23,6 +23,7 @@
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/videodev2.h>
/* ivtv knows several distinct output modes: MPEG streaming,
YUV streaming, YUV updates through user DMA and the passthrough

8
include/linux/jbd2.h
View file

@ -850,7 +850,8 @@ struct journal_s
*/
struct block_device *j_dev;
int j_blocksize;
unsigned long long j_blk_offset;
unsigned long long j_blk_offset;
char j_devname[BDEVNAME_SIZE+24];
/*
* Device which holds the client fs. For internal journal this will be
@ -966,6 +967,9 @@ struct journal_s
#define JBD2_FLUSHED 0x008 /* The journal superblock has been flushed */
#define JBD2_LOADED 0x010 /* The journal superblock has been loaded */
#define JBD2_BARRIER 0x020 /* Use IDE barriers */
#define JBD2_ABORT_ON_SYNCDATA_ERR 0x040 /* Abort the journal on file
* data write error in ordered
* mode */
/*
* Function declarations for the journaling transaction and buffer
@ -1059,7 +1063,7 @@ extern void jbd2_journal_clear_features
(journal_t *, unsigned long, unsigned long, unsigned long);
extern int jbd2_journal_create (journal_t *);
extern int jbd2_journal_load (journal_t *journal);
extern void jbd2_journal_destroy (journal_t *);
extern int jbd2_journal_destroy (journal_t *);
extern int jbd2_journal_recover (journal_t *journal);
extern int jbd2_journal_wipe (journal_t *, int);
extern int jbd2_journal_skip_recovery (journal_t *);

2
include/linux/kernel.h
View file

@ -182,7 +182,7 @@ extern int vsscanf(const char *, const char *, va_list)
extern int get_option(char **str, int *pint);
extern char *get_options(const char *str, int nints, int *ints);
extern unsigned long long memparse(char *ptr, char **retptr);
extern unsigned long long memparse(const char *ptr, char **retptr);
extern int core_kernel_text(unsigned long addr);
extern int __kernel_text_address(unsigned long addr);

1
include/linux/key.h
View file

@ -299,6 +299,7 @@ extern void key_init(void);
#define key_validate(k) 0
#define key_serial(k) 0
#define key_get(k) ({ NULL; })
#define key_revoke(k) do { } while(0)
#define key_put(k) do { } while(0)
#define key_ref_put(k) do { } while(0)
#define make_key_ref(k, p) ({ NULL; })

3
include/linux/klist.h
View file

@ -38,7 +38,7 @@ extern void klist_init(struct klist *k, void (*get)(struct klist_node *),
void (*put)(struct klist_node *));
struct klist_node {
struct klist *n_klist;
void *n_klist; /* never access directly */
struct list_head n_node;
struct kref n_ref;
struct completion n_removed;
@ -57,7 +57,6 @@ extern int klist_node_attached(struct klist_node *n);
struct klist_iter {
struct klist *i_klist;
struct list_head *i_head;
struct klist_node *i_cur;
};

3
include/linux/lcd.h
View file

@ -11,6 +11,7 @@
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/fb.h>
/* Notes on locking:
*
@ -45,6 +46,8 @@ struct lcd_ops {
int (*get_contrast)(struct lcd_device *);
/* Set LCD panel contrast */
int (*set_contrast)(struct lcd_device *, int contrast);
/* Set LCD panel mode (resolutions ...) */
int (*set_mode)(struct lcd_device *, struct fb_videomode *);
/* Check if given framebuffer device is the one LCD is bound to;
return 0 if not, !=0 if it is. If NULL, lcd always matches the fb. */
int (*check_fb)(struct lcd_device *, struct fb_info *);

66
include/linux/libata.h
View file

@ -146,6 +146,7 @@ enum {
ATA_DFLAG_SPUNDOWN = (1 << 14), /* XXX: for spindown_compat */
ATA_DFLAG_SLEEPING = (1 << 15), /* device is sleeping */
ATA_DFLAG_DUBIOUS_XFER = (1 << 16), /* data transfer not verified */
ATA_DFLAG_NO_UNLOAD = (1 << 17), /* device doesn't support unload */
ATA_DFLAG_INIT_MASK = (1 << 24) - 1,
ATA_DFLAG_DETACH = (1 << 24),
@ -244,6 +245,7 @@ enum {
ATA_TMOUT_BOOT = 30000, /* heuristic */
ATA_TMOUT_BOOT_QUICK = 7000, /* heuristic */
ATA_TMOUT_INTERNAL_QUICK = 5000,
ATA_TMOUT_MAX_PARK = 30000,
/* FIXME: GoVault needs 2s but we can't afford that without
* parallel probing. 800ms is enough for iVDR disk
@ -319,8 +321,11 @@ enum {
ATA_EH_RESET = ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
ATA_EH_ENABLE_LINK = (1 << 3),
ATA_EH_LPM = (1 << 4), /* link power management action */
ATA_EH_PARK = (1 << 5), /* unload heads and stop I/O */
ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE,
ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE | ATA_EH_PARK,
ATA_EH_ALL_ACTIONS = ATA_EH_REVALIDATE | ATA_EH_RESET |
ATA_EH_ENABLE_LINK | ATA_EH_LPM,
/* ata_eh_info->flags */
ATA_EHI_HOTPLUGGED = (1 << 0), /* could have been hotplugged */
@ -452,6 +457,7 @@ enum link_pm {
MEDIUM_POWER,
};
extern struct device_attribute dev_attr_link_power_management_policy;
extern struct device_attribute dev_attr_unload_heads;
extern struct device_attribute dev_attr_em_message_type;
extern struct device_attribute dev_attr_em_message;
extern struct device_attribute dev_attr_sw_activity;
@ -554,8 +560,8 @@ struct ata_ering {
struct ata_device {
struct ata_link *link;
unsigned int devno; /* 0 or 1 */
unsigned long flags; /* ATA_DFLAG_xxx */
unsigned int horkage; /* List of broken features */
unsigned long flags; /* ATA_DFLAG_xxx */
struct scsi_device *sdev; /* attached SCSI device */
#ifdef CONFIG_ATA_ACPI
acpi_handle acpi_handle;
@ -564,6 +570,7 @@ struct ata_device {
/* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */
u64 n_sectors; /* size of device, if ATA */
unsigned int class; /* ATA_DEV_xxx */
unsigned long unpark_deadline;
u8 pio_mode;
u8 dma_mode;
@ -621,6 +628,7 @@ struct ata_eh_context {
[ATA_EH_CMD_TIMEOUT_TABLE_SIZE];
unsigned int classes[ATA_MAX_DEVICES];
unsigned int did_probe_mask;
unsigned int unloaded_mask;
unsigned int saved_ncq_enabled;
u8 saved_xfer_mode[ATA_MAX_DEVICES];
/* timestamp for the last reset attempt or success */
@ -688,7 +696,8 @@ struct ata_port {
unsigned int qc_active;
int nr_active_links; /* #links with active qcs */
struct ata_link link; /* host default link */
struct ata_link link; /* host default link */
struct ata_link *slave_link; /* see ata_slave_link_init() */
int nr_pmp_links; /* nr of available PMP links */
struct ata_link *pmp_link; /* array of PMP links */
@ -709,6 +718,7 @@ struct ata_port {
struct list_head eh_done_q;
wait_queue_head_t eh_wait_q;
int eh_tries;
struct completion park_req_pending;
pm_message_t pm_mesg;
int *pm_result;
@ -772,8 +782,8 @@ struct ata_port_operations {
/*
* Optional features
*/
int (*scr_read)(struct ata_port *ap, unsigned int sc_reg, u32 *val);
int (*scr_write)(struct ata_port *ap, unsigned int sc_reg, u32 val);
int (*scr_read)(struct ata_link *link, unsigned int sc_reg, u32 *val);
int (*scr_write)(struct ata_link *link, unsigned int sc_reg, u32 val);
void (*pmp_attach)(struct ata_port *ap);
void (*pmp_detach)(struct ata_port *ap);
int (*enable_pm)(struct ata_port *ap, enum link_pm policy);
@ -895,6 +905,7 @@ extern void ata_port_disable(struct ata_port *);
extern struct ata_host *ata_host_alloc(struct device *dev, int max_ports);
extern struct ata_host *ata_host_alloc_pinfo(struct device *dev,
const struct ata_port_info * const * ppi, int n_ports);
extern int ata_slave_link_init(struct ata_port *ap);
extern int ata_host_start(struct ata_host *host);
extern int ata_host_register(struct ata_host *host,
struct scsi_host_template *sht);
@ -920,8 +931,8 @@ extern int sata_scr_valid(struct ata_link *link);
extern int sata_scr_read(struct ata_link *link, int reg, u32 *val);
extern int sata_scr_write(struct ata_link *link, int reg, u32 val);
extern int sata_scr_write_flush(struct ata_link *link, int reg, u32 val);
extern int ata_link_online(struct ata_link *link);
extern int ata_link_offline(struct ata_link *link);
extern bool ata_link_online(struct ata_link *link);
extern bool ata_link_offline(struct ata_link *link);
#ifdef CONFIG_PM
extern int ata_host_suspend(struct ata_host *host, pm_message_t mesg);
extern void ata_host_resume(struct ata_host *host);
@ -1098,6 +1109,7 @@ extern void ata_std_error_handler(struct ata_port *ap);
*/
extern const struct ata_port_operations ata_base_port_ops;
extern const struct ata_port_operations sata_port_ops;
extern struct device_attribute *ata_common_sdev_attrs[];
#define ATA_BASE_SHT(drv_name) \
.module = THIS_MODULE, \
@ -1112,7 +1124,8 @@ extern const struct ata_port_operations sata_port_ops;
.proc_name = drv_name, \
.slave_configure = ata_scsi_slave_config, \
.slave_destroy = ata_scsi_slave_destroy, \
.bios_param = ata_std_bios_param
.bios_param = ata_std_bios_param, \
.sdev_attrs = ata_common_sdev_attrs
#define ATA_NCQ_SHT(drv_name) \
ATA_BASE_SHT(drv_name), \
@ -1134,7 +1147,7 @@ static inline bool sata_pmp_attached(struct ata_port *ap)
static inline int ata_is_host_link(const struct ata_link *link)
{
return link == &link->ap->link;
return link == &link->ap->link || link == link->ap->slave_link;
}
#else /* CONFIG_SATA_PMP */
static inline bool sata_pmp_supported(struct ata_port *ap)
@ -1167,7 +1180,7 @@ static inline int sata_srst_pmp(struct ata_link *link)
printk("%sata%u: "fmt, lv, (ap)->print_id , ##args)
#define ata_link_printk(link, lv, fmt, args...) do { \
if (sata_pmp_attached((link)->ap)) \
if (sata_pmp_attached((link)->ap) || (link)->ap->slave_link) \
printk("%sata%u.%02u: "fmt, lv, (link)->ap->print_id, \
(link)->pmp , ##args); \
else \
@ -1265,34 +1278,17 @@ static inline int ata_link_active(struct ata_link *link)
return ata_tag_valid(link->active_tag) || link->sactive;
}
static inline struct ata_link *ata_port_first_link(struct ata_port *ap)
{
if (sata_pmp_attached(ap))
return ap->pmp_link;
return &ap->link;
}
extern struct ata_link *__ata_port_next_link(struct ata_port *ap,
struct ata_link *link,
bool dev_only);
static inline struct ata_link *ata_port_next_link(struct ata_link *link)
{
struct ata_port *ap = link->ap;
if (ata_is_host_link(link)) {
if (!sata_pmp_attached(ap))
return NULL;
return ap->pmp_link;
}
if (++link < ap->nr_pmp_links + ap->pmp_link)
return link;
return NULL;
}
#define __ata_port_for_each_link(lk, ap) \
for ((lk) = &(ap)->link; (lk); (lk) = ata_port_next_link(lk))
#define __ata_port_for_each_link(link, ap) \
for ((link) = __ata_port_next_link((ap), NULL, false); (link); \
(link) = __ata_port_next_link((ap), (link), false))
#define ata_port_for_each_link(link, ap) \
for ((link) = ata_port_first_link(ap); (link); \
(link) = ata_port_next_link(link))
for ((link) = __ata_port_next_link((ap), NULL, true); (link); \
(link) = __ata_port_next_link((ap), (link), true))
#define ata_link_for_each_dev(dev, link) \
for ((dev) = (link)->device; \

11
include/linux/lockd/bind.h
View file

@ -27,7 +27,6 @@ struct nlmsvc_binding {
struct nfs_fh *,
struct file **);
void (*fclose)(struct file *);
unsigned long (*get_grace_period)(void);
};
extern struct nlmsvc_binding * nlmsvc_ops;
@ -53,15 +52,7 @@ extern void nlmclnt_done(struct nlm_host *host);
extern int nlmclnt_proc(struct nlm_host *host, int cmd,
struct file_lock *fl);
extern int lockd_up(int proto);
extern int lockd_up(void);
extern void lockd_down(void);
unsigned long get_nfs_grace_period(void);
#ifdef CONFIG_NFSD_V4
unsigned long get_nfs4_grace_period(void);
#else
static inline unsigned long get_nfs4_grace_period(void) {return 0;}
#endif
#endif /* LINUX_LOCKD_BIND_H */

141
include/linux/lockd/lockd.h
View file

@ -12,6 +12,8 @@
#ifdef __KERNEL__
#include <linux/in.h>
#include <linux/in6.h>
#include <net/ipv6.h>
#include <linux/fs.h>
#include <linux/kref.h>
#include <linux/utsname.h>
@ -38,8 +40,9 @@
*/
struct nlm_host {
struct hlist_node h_hash; /* doubly linked list */
struct sockaddr_in h_addr; /* peer address */
struct sockaddr_in h_saddr; /* our address (optional) */
struct sockaddr_storage h_addr; /* peer address */
size_t h_addrlen;
struct sockaddr_storage h_srcaddr; /* our address (optional) */
struct rpc_clnt * h_rpcclnt; /* RPC client to talk to peer */
char * h_name; /* remote hostname */
u32 h_version; /* interface version */
@ -61,17 +64,55 @@ struct nlm_host {
struct list_head h_granted; /* Locks in GRANTED state */
struct list_head h_reclaim; /* Locks in RECLAIM state */
struct nsm_handle * h_nsmhandle; /* NSM status handle */
char h_addrbuf[48], /* address eyecatchers */
h_srcaddrbuf[48];
};
struct nsm_handle {
struct list_head sm_link;
atomic_t sm_count;
char * sm_name;
struct sockaddr_in sm_addr;
struct sockaddr_storage sm_addr;
size_t sm_addrlen;
unsigned int sm_monitored : 1,
sm_sticky : 1; /* don't unmonitor */
char sm_addrbuf[48]; /* address eyecatcher */
};
/*
* Rigorous type checking on sockaddr type conversions
*/
static inline struct sockaddr_in *nlm_addr_in(const struct nlm_host *host)
{
return (struct sockaddr_in *)&host->h_addr;
}
static inline struct sockaddr *nlm_addr(const struct nlm_host *host)
{
return (struct sockaddr *)&host->h_addr;
}
static inline struct sockaddr_in *nlm_srcaddr_in(const struct nlm_host *host)
{
return (struct sockaddr_in *)&host->h_srcaddr;
}
static inline struct sockaddr *nlm_srcaddr(const struct nlm_host *host)
{
return (struct sockaddr *)&host->h_srcaddr;
}
static inline struct sockaddr_in *nsm_addr_in(const struct nsm_handle *handle)
{
return (struct sockaddr_in *)&handle->sm_addr;
}
static inline struct sockaddr *nsm_addr(const struct nsm_handle *handle)
{
return (struct sockaddr *)&handle->sm_addr;
}
/*
* Map an fl_owner_t into a unique 32-bit "pid"
*/
@ -166,7 +207,8 @@ int nlm_async_reply(struct nlm_rqst *, u32, const struct rpc_call_ops *);
struct nlm_wait * nlmclnt_prepare_block(struct nlm_host *host, struct file_lock *fl);
void nlmclnt_finish_block(struct nlm_wait *block);
int nlmclnt_block(struct nlm_wait *block, struct nlm_rqst *req, long timeout);
__be32 nlmclnt_grant(const struct sockaddr_in *addr, const struct nlm_lock *);
__be32 nlmclnt_grant(const struct sockaddr *addr,
const struct nlm_lock *lock);
void nlmclnt_recovery(struct nlm_host *);
int nlmclnt_reclaim(struct nlm_host *, struct file_lock *);
void nlmclnt_next_cookie(struct nlm_cookie *);
@ -174,12 +216,14 @@ void nlmclnt_next_cookie(struct nlm_cookie *);
/*
* Host cache
*/
struct nlm_host *nlmclnt_lookup_host(const struct sockaddr_in *sin,
int proto, u32 version,
struct nlm_host *nlmclnt_lookup_host(const struct sockaddr *sap,
const size_t salen,
const unsigned short protocol,
const u32 version,
const char *hostname);
struct nlm_host *nlmsvc_lookup_host(const struct svc_rqst *rqstp,
const char *hostname,
unsigned int hostname_len);
struct nlm_host *nlmsvc_lookup_host(struct svc_rqst *, const char *,
unsigned int);
const size_t hostname_len);
struct rpc_clnt * nlm_bind_host(struct nlm_host *);
void nlm_rebind_host(struct nlm_host *);
struct nlm_host * nlm_get_host(struct nlm_host *);
@ -201,7 +245,7 @@ typedef int (*nlm_host_match_fn_t)(void *cur, struct nlm_host *ref);
*/
__be32 nlmsvc_lock(struct svc_rqst *, struct nlm_file *,
struct nlm_host *, struct nlm_lock *, int,
struct nlm_cookie *);
struct nlm_cookie *, int);
__be32 nlmsvc_unlock(struct nlm_file *, struct nlm_lock *);
__be32 nlmsvc_testlock(struct svc_rqst *, struct nlm_file *,
struct nlm_host *, struct nlm_lock *,
@ -233,15 +277,82 @@ static inline struct inode *nlmsvc_file_inode(struct nlm_file *file)
return file->f_file->f_path.dentry->d_inode;
}
/*
* Compare two host addresses (needs modifying for ipv6)
*/
static inline int nlm_cmp_addr(const struct sockaddr_in *sin1,
const struct sockaddr_in *sin2)
static inline int __nlm_privileged_request4(const struct sockaddr *sap)
{
const struct sockaddr_in *sin = (struct sockaddr_in *)sap;
return (sin->sin_addr.s_addr == htonl(INADDR_LOOPBACK)) &&
(ntohs(sin->sin_port) < 1024);
}
#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
static inline int __nlm_privileged_request6(const struct sockaddr *sap)
{
const struct sockaddr_in6 *sin6 = (struct sockaddr_in6 *)sap;
return (ipv6_addr_type(&sin6->sin6_addr) & IPV6_ADDR_LOOPBACK) &&
(ntohs(sin6->sin6_port) < 1024);
}
#else /* defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) */
static inline int __nlm_privileged_request6(const struct sockaddr *sap)
{
return 0;
}
#endif /* defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) */
/*
* Ensure incoming requests are from local privileged callers.
*
* Return TRUE if sender is local and is connecting via a privileged port;
* otherwise return FALSE.
*/
static inline int nlm_privileged_requester(const struct svc_rqst *rqstp)
{
const struct sockaddr *sap = svc_addr(rqstp);
switch (sap->sa_family) {
case AF_INET:
return __nlm_privileged_request4(sap);
case AF_INET6:
return __nlm_privileged_request6(sap);
default:
return 0;
}
}
static inline int __nlm_cmp_addr4(const struct sockaddr *sap1,
const struct sockaddr *sap2)
{
const struct sockaddr_in *sin1 = (const struct sockaddr_in *)sap1;
const struct sockaddr_in *sin2 = (const struct sockaddr_in *)sap2;
return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr;
}
static inline int __nlm_cmp_addr6(const struct sockaddr *sap1,
const struct sockaddr *sap2)
{
const struct sockaddr_in6 *sin1 = (const struct sockaddr_in6 *)sap1;
const struct sockaddr_in6 *sin2 = (const struct sockaddr_in6 *)sap2;
return ipv6_addr_equal(&sin1->sin6_addr, &sin2->sin6_addr);
}
/*
* Compare two host addresses
*
* Return TRUE if the addresses are the same; otherwise FALSE.
*/
static inline int nlm_cmp_addr(const struct sockaddr *sap1,
const struct sockaddr *sap2)
{
if (sap1->sa_family == sap2->sa_family) {
switch (sap1->sa_family) {
case AF_INET:
return __nlm_cmp_addr4(sap1, sap2);
case AF_INET6:
return __nlm_cmp_addr6(sap1, sap2);
}
}
return 0;
}
/*
* Compare two NLM locks.
* When the second lock is of type F_UNLCK, this acts like a wildcard.

2
include/linux/lockd/xdr.h
View file

@ -81,8 +81,6 @@ struct nlm_reboot {
unsigned int len;
u32 state;
__be32 addr;
__be32 vers;
__be32 proto;
};
/*

4
include/linux/magic.h
View file

@ -6,6 +6,10 @@
#define AFS_SUPER_MAGIC 0x5346414F
#define AUTOFS_SUPER_MAGIC 0x0187
#define CODA_SUPER_MAGIC 0x73757245
#define DEBUGFS_MAGIC 0x64626720
#define SYSFS_MAGIC 0x62656572
#define SECURITYFS_MAGIC 0x73636673
#define TMPFS_MAGIC 0x01021994
#define EFS_SUPER_MAGIC 0x414A53
#define EXT2_SUPER_MAGIC 0xEF53
#define EXT3_SUPER_MAGIC 0xEF53

2
include/linux/major.h
View file

@ -170,4 +170,6 @@
#define VIOTAPE_MAJOR 230
#define BLOCK_EXT_MAJOR 259
#endif

97
include/linux/memstick.h
View file

@ -21,30 +21,30 @@
struct ms_status_register {
unsigned char reserved;
unsigned char interrupt;
#define MEMSTICK_INT_CMDNAK 0x0001
#define MEMSTICK_INT_IOREQ 0x0008
#define MEMSTICK_INT_IOBREQ 0x0010
#define MEMSTICK_INT_BREQ 0x0020
#define MEMSTICK_INT_ERR 0x0040
#define MEMSTICK_INT_CED 0x0080
#define MEMSTICK_INT_CMDNAK 0x01
#define MEMSTICK_INT_IOREQ 0x08
#define MEMSTICK_INT_IOBREQ 0x10
#define MEMSTICK_INT_BREQ 0x20
#define MEMSTICK_INT_ERR 0x40
#define MEMSTICK_INT_CED 0x80
unsigned char status0;
#define MEMSTICK_STATUS0_WP 0x0001
#define MEMSTICK_STATUS0_SL 0x0002
#define MEMSTICK_STATUS0_BF 0x0010
#define MEMSTICK_STATUS0_BE 0x0020
#define MEMSTICK_STATUS0_FB0 0x0040
#define MEMSTICK_STATUS0_MB 0x0080
#define MEMSTICK_STATUS0_WP 0x01
#define MEMSTICK_STATUS0_SL 0x02
#define MEMSTICK_STATUS0_BF 0x10
#define MEMSTICK_STATUS0_BE 0x20
#define MEMSTICK_STATUS0_FB0 0x40
#define MEMSTICK_STATUS0_MB 0x80
unsigned char status1;
#define MEMSTICK_STATUS1_UCFG 0x0001
#define MEMSTICK_STATUS1_FGER 0x0002
#define MEMSTICK_STATUS1_UCEX 0x0004
#define MEMSTICK_STATUS1_EXER 0x0008
#define MEMSTICK_STATUS1_UCDT 0x0010
#define MEMSTICK_STATUS1_DTER 0x0020
#define MEMSTICK_STATUS1_FBI 0x0040
#define MEMSTICK_STATUS1_MB 0x0080
#define MEMSTICK_STATUS1_UCFG 0x01
#define MEMSTICK_STATUS1_FGER 0x02
#define MEMSTICK_STATUS1_UCEX 0x04
#define MEMSTICK_STATUS1_EXER 0x08
#define MEMSTICK_STATUS1_UCDT 0x10
#define MEMSTICK_STATUS1_DTER 0x20
#define MEMSTICK_STATUS1_FB1 0x40
#define MEMSTICK_STATUS1_MB 0x80
} __attribute__((packed));
struct ms_id_register {
@ -56,32 +56,32 @@ struct ms_id_register {
struct ms_param_register {
unsigned char system;
#define MEMSTICK_SYS_ATEN 0xc0
#define MEMSTICK_SYS_BAMD 0x80
#define MEMSTICK_SYS_PAM 0x08
#define MEMSTICK_SYS_BAMD 0x80
unsigned char block_address_msb;
unsigned short block_address;
unsigned char cp;
#define MEMSTICK_CP_BLOCK 0x0000
#define MEMSTICK_CP_PAGE 0x0020
#define MEMSTICK_CP_EXTRA 0x0040
#define MEMSTICK_CP_OVERWRITE 0x0080
#define MEMSTICK_CP_BLOCK 0x00
#define MEMSTICK_CP_PAGE 0x20
#define MEMSTICK_CP_EXTRA 0x40
#define MEMSTICK_CP_OVERWRITE 0x80
unsigned char page_address;
} __attribute__((packed));
struct ms_extra_data_register {
unsigned char overwrite_flag;
#define MEMSTICK_OVERWRITE_UPDATA 0x0010
#define MEMSTICK_OVERWRITE_PAGE 0x0060
#define MEMSTICK_OVERWRITE_BLOCK 0x0080
#define MEMSTICK_OVERWRITE_UDST 0x10
#define MEMSTICK_OVERWRITE_PGST1 0x20
#define MEMSTICK_OVERWRITE_PGST0 0x40
#define MEMSTICK_OVERWRITE_BKST 0x80
unsigned char management_flag;
#define MEMSTICK_MANAGEMENT_SYSTEM 0x0004
#define MEMSTICK_MANAGEMENT_TRANS_TABLE 0x0008
#define MEMSTICK_MANAGEMENT_COPY 0x0010
#define MEMSTICK_MANAGEMENT_ACCESS 0x0020
#define MEMSTICK_MANAGEMENT_SYSFLG 0x04
#define MEMSTICK_MANAGEMENT_ATFLG 0x08
#define MEMSTICK_MANAGEMENT_SCMS1 0x10
#define MEMSTICK_MANAGEMENT_SCMS0 0x20
unsigned short logical_address;
} __attribute__((packed));
@ -96,9 +96,9 @@ struct ms_register {
struct mspro_param_register {
unsigned char system;
#define MEMSTICK_SYS_SERIAL 0x80
#define MEMSTICK_SYS_PAR4 0x00
#define MEMSTICK_SYS_PAR8 0x40
#define MEMSTICK_SYS_SERIAL 0x80
unsigned short data_count;
unsigned int data_address;
@ -147,7 +147,7 @@ struct ms_register_addr {
unsigned char w_length;
} __attribute__((packed));
enum {
enum memstick_tpc {
MS_TPC_READ_MG_STATUS = 0x01,
MS_TPC_READ_LONG_DATA = 0x02,
MS_TPC_READ_SHORT_DATA = 0x03,
@ -167,7 +167,7 @@ enum {
MS_TPC_SET_CMD = 0x0e
};
enum {
enum memstick_command {
MS_CMD_BLOCK_END = 0x33,
MS_CMD_RESET = 0x3c,
MS_CMD_BLOCK_WRITE = 0x55,
@ -201,8 +201,6 @@ enum {
/*** Driver structures and functions ***/
#define MEMSTICK_PART_SHIFT 3
enum memstick_param { MEMSTICK_POWER = 1, MEMSTICK_INTERFACE };
#define MEMSTICK_POWER_OFF 0
@ -215,24 +213,27 @@ enum memstick_param { MEMSTICK_POWER = 1, MEMSTICK_INTERFACE };
struct memstick_host;
struct memstick_driver;
struct memstick_device_id {
unsigned char match_flags;
#define MEMSTICK_MATCH_ALL 0x01
unsigned char type;
#define MEMSTICK_TYPE_LEGACY 0xff
#define MEMSTICK_TYPE_DUO 0x00
#define MEMSTICK_TYPE_PRO 0x01
unsigned char category;
#define MEMSTICK_CATEGORY_STORAGE 0xff
#define MEMSTICK_CATEGORY_STORAGE_DUO 0x00
#define MEMSTICK_CATEGORY_IO 0x01
#define MEMSTICK_CATEGORY_IO_PRO 0x10
#define MEMSTICK_CLASS_GENERIC 0xff
#define MEMSTICK_CLASS_GENERIC_DUO 0x00
struct memstick_device_id {
unsigned char match_flags;
unsigned char type;
unsigned char category;
unsigned char class;
#define MEMSTICK_CLASS_FLASH 0xff
#define MEMSTICK_CLASS_DUO 0x00
#define MEMSTICK_CLASS_ROM 0x01
#define MEMSTICK_CLASS_RO 0x02
#define MEMSTICK_CLASS_WP 0x03
};
struct memstick_request {
@ -319,9 +320,9 @@ void memstick_suspend_host(struct memstick_host *host);
void memstick_resume_host(struct memstick_host *host);
void memstick_init_req_sg(struct memstick_request *mrq, unsigned char tpc,
struct scatterlist *sg);
const struct scatterlist *sg);
void memstick_init_req(struct memstick_request *mrq, unsigned char tpc,
void *buf, size_t length);
const void *buf, size_t length);
int memstick_next_req(struct memstick_host *host,
struct memstick_request **mrq);
void memstick_new_req(struct memstick_host *host);

598
include/linux/mfd/wm8350/audio.h Normal file
View file

@ -0,0 +1,598 @@
/*
* audio.h -- Audio Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_AUDIO_H_
#define __LINUX_MFD_WM8350_AUDIO_H_
#include <linux/platform_device.h>
#define WM8350_CLOCK_CONTROL_1 0x28
#define WM8350_CLOCK_CONTROL_2 0x29
#define WM8350_FLL_CONTROL_1 0x2A
#define WM8350_FLL_CONTROL_2 0x2B
#define WM8350_FLL_CONTROL_3 0x2C
#define WM8350_FLL_CONTROL_4 0x2D
#define WM8350_DAC_CONTROL 0x30
#define WM8350_DAC_DIGITAL_VOLUME_L 0x32
#define WM8350_DAC_DIGITAL_VOLUME_R 0x33
#define WM8350_DAC_LR_RATE 0x35
#define WM8350_DAC_CLOCK_CONTROL 0x36
#define WM8350_DAC_MUTE 0x3A
#define WM8350_DAC_MUTE_VOLUME 0x3B
#define WM8350_DAC_SIDE 0x3C
#define WM8350_ADC_CONTROL 0x40
#define WM8350_ADC_DIGITAL_VOLUME_L 0x42
#define WM8350_ADC_DIGITAL_VOLUME_R 0x43
#define WM8350_ADC_DIVIDER 0x44
#define WM8350_ADC_LR_RATE 0x46
#define WM8350_INPUT_CONTROL 0x48
#define WM8350_IN3_INPUT_CONTROL 0x49
#define WM8350_MIC_BIAS_CONTROL 0x4A
#define WM8350_OUTPUT_CONTROL 0x4C
#define WM8350_JACK_DETECT 0x4D
#define WM8350_ANTI_POP_CONTROL 0x4E
#define WM8350_LEFT_INPUT_VOLUME 0x50
#define WM8350_RIGHT_INPUT_VOLUME 0x51
#define WM8350_LEFT_MIXER_CONTROL 0x58
#define WM8350_RIGHT_MIXER_CONTROL 0x59
#define WM8350_OUT3_MIXER_CONTROL 0x5C
#define WM8350_OUT4_MIXER_CONTROL 0x5D
#define WM8350_OUTPUT_LEFT_MIXER_VOLUME 0x60
#define WM8350_OUTPUT_RIGHT_MIXER_VOLUME 0x61
#define WM8350_INPUT_MIXER_VOLUME_L 0x62
#define WM8350_INPUT_MIXER_VOLUME_R 0x63
#define WM8350_INPUT_MIXER_VOLUME 0x64
#define WM8350_LOUT1_VOLUME 0x68
#define WM8350_ROUT1_VOLUME 0x69
#define WM8350_LOUT2_VOLUME 0x6A
#define WM8350_ROUT2_VOLUME 0x6B
#define WM8350_BEEP_VOLUME 0x6F
#define WM8350_AI_FORMATING 0x70
#define WM8350_ADC_DAC_COMP 0x71
#define WM8350_AI_ADC_CONTROL 0x72
#define WM8350_AI_DAC_CONTROL 0x73
#define WM8350_AIF_TEST 0x74
#define WM8350_JACK_PIN_STATUS 0xE7
/* Bit values for R08 (0x08) */
#define WM8350_CODEC_ISEL_1_5 0 /* x1.5 */
#define WM8350_CODEC_ISEL_1_0 1 /* x1.0 */
#define WM8350_CODEC_ISEL_0_75 2 /* x0.75 */
#define WM8350_CODEC_ISEL_0_5 3 /* x0.5 */
#define WM8350_VMID_OFF 0
#define WM8350_VMID_500K 1
#define WM8350_VMID_100K 2
#define WM8350_VMID_10K 3
/*
* R40 (0x28) - Clock Control 1
*/
#define WM8350_TOCLK_RATE 0x4000
#define WM8350_MCLK_SEL 0x0800
#define WM8350_MCLK_DIV_MASK 0x0100
#define WM8350_BCLK_DIV_MASK 0x00F0
#define WM8350_OPCLK_DIV_MASK 0x0007
/*
* R41 (0x29) - Clock Control 2
*/
#define WM8350_LRC_ADC_SEL 0x8000
#define WM8350_MCLK_DIR 0x0001
/*
* R42 (0x2A) - FLL Control 1
*/
#define WM8350_FLL_DITHER_WIDTH_MASK 0x3000
#define WM8350_FLL_DITHER_HP 0x0800
#define WM8350_FLL_OUTDIV_MASK 0x0700
#define WM8350_FLL_RSP_RATE_MASK 0x00F0
#define WM8350_FLL_RATE_MASK 0x0007
/*
* R43 (0x2B) - FLL Control 2
*/
#define WM8350_FLL_RATIO_MASK 0xF800
#define WM8350_FLL_N_MASK 0x03FF
/*
* R44 (0x2C) - FLL Control 3
*/
#define WM8350_FLL_K_MASK 0xFFFF
/*
* R45 (0x2D) - FLL Control 4
*/
#define WM8350_FLL_FRAC 0x0020
#define WM8350_FLL_SLOW_LOCK_REF 0x0010
#define WM8350_FLL_CLK_SRC_MASK 0x0003
/*
* R48 (0x30) - DAC Control
*/
#define WM8350_DAC_MONO 0x2000
#define WM8350_AIF_LRCLKRATE 0x1000
#define WM8350_DEEMP_MASK 0x0030
#define WM8350_DACL_DATINV 0x0002
#define WM8350_DACR_DATINV 0x0001
/*
* R50 (0x32) - DAC Digital Volume L
*/
#define WM8350_DAC_VU 0x0100
#define WM8350_DACL_VOL_MASK 0x00FF
/*
* R51 (0x33) - DAC Digital Volume R
*/
#define WM8350_DAC_VU 0x0100
#define WM8350_DACR_VOL_MASK 0x00FF
/*
* R53 (0x35) - DAC LR Rate
*/
#define WM8350_DACLRC_ENA 0x0800
#define WM8350_DACLRC_RATE_MASK 0x07FF
/*
* R54 (0x36) - DAC Clock Control
*/
#define WM8350_DACCLK_POL 0x0010
#define WM8350_DAC_CLKDIV_MASK 0x0007
/*
* R58 (0x3A) - DAC Mute
*/
#define WM8350_DAC_MUTE_ENA 0x4000
/*
* R59 (0x3B) - DAC Mute Volume
*/
#define WM8350_DAC_MUTEMODE 0x4000
#define WM8350_DAC_MUTERATE 0x2000
#define WM8350_DAC_SB_FILT 0x1000
/*
* R60 (0x3C) - DAC Side
*/
#define WM8350_ADC_TO_DACL_MASK 0x3000
#define WM8350_ADC_TO_DACR_MASK 0x0C00
/*
* R64 (0x40) - ADC Control
*/
#define WM8350_ADC_HPF_CUT_MASK 0x0300
#define WM8350_ADCL_DATINV 0x0002
#define WM8350_ADCR_DATINV 0x0001
/*
* R66 (0x42) - ADC Digital Volume L
*/
#define WM8350_ADC_VU 0x0100
#define WM8350_ADCL_VOL_MASK 0x00FF
/*
* R67 (0x43) - ADC Digital Volume R
*/
#define WM8350_ADC_VU 0x0100
#define WM8350_ADCR_VOL_MASK 0x00FF
/*
* R68 (0x44) - ADC Divider
*/
#define WM8350_ADCL_DAC_SVOL_MASK 0x0F00
#define WM8350_ADCR_DAC_SVOL_MASK 0x00F0
#define WM8350_ADCCLK_POL 0x0008
#define WM8350_ADC_CLKDIV_MASK 0x0007
/*
* R70 (0x46) - ADC LR Rate
*/
#define WM8350_ADCLRC_ENA 0x0800
#define WM8350_ADCLRC_RATE_MASK 0x07FF
/*
* R72 (0x48) - Input Control
*/
#define WM8350_IN2R_ENA 0x0400
#define WM8350_IN1RN_ENA 0x0200
#define WM8350_IN1RP_ENA 0x0100
#define WM8350_IN2L_ENA 0x0004
#define WM8350_IN1LN_ENA 0x0002
#define WM8350_IN1LP_ENA 0x0001
/*
* R73 (0x49) - IN3 Input Control
*/
#define WM8350_IN3R_SHORT 0x4000
#define WM8350_IN3L_SHORT 0x0040
/*
* R74 (0x4A) - Mic Bias Control
*/
#define WM8350_MICBSEL 0x4000
#define WM8350_MCDTHR_MASK 0x001C
#define WM8350_MCDSCTHR_MASK 0x0003
/*
* R76 (0x4C) - Output Control
*/
#define WM8350_OUT4_VROI 0x0800
#define WM8350_OUT3_VROI 0x0400
#define WM8350_OUT2_VROI 0x0200
#define WM8350_OUT1_VROI 0x0100
#define WM8350_OUT2_FB 0x0004
#define WM8350_OUT1_FB 0x0001
/*
* R77 (0x4D) - Jack Detect
*/
#define WM8350_JDL_ENA 0x8000
#define WM8350_JDR_ENA 0x4000
/*
* R78 (0x4E) - Anti Pop Control
*/
#define WM8350_ANTI_POP_MASK 0x0300
#define WM8350_DIS_OP_LN4_MASK 0x00C0
#define WM8350_DIS_OP_LN3_MASK 0x0030
#define WM8350_DIS_OP_OUT2_MASK 0x000C
#define WM8350_DIS_OP_OUT1_MASK 0x0003
/*
* R80 (0x50) - Left Input Volume
*/
#define WM8350_INL_MUTE 0x4000
#define WM8350_INL_ZC 0x2000
#define WM8350_IN_VU 0x0100
#define WM8350_INL_VOL_MASK 0x00FC
/*
* R81 (0x51) - Right Input Volume
*/
#define WM8350_INR_MUTE 0x4000
#define WM8350_INR_ZC 0x2000
#define WM8350_IN_VU 0x0100
#define WM8350_INR_VOL_MASK 0x00FC
/*
* R88 (0x58) - Left Mixer Control
*/
#define WM8350_DACR_TO_MIXOUTL 0x1000
#define WM8350_DACL_TO_MIXOUTL 0x0800
#define WM8350_IN3L_TO_MIXOUTL 0x0004
#define WM8350_INR_TO_MIXOUTL 0x0002
#define WM8350_INL_TO_MIXOUTL 0x0001
/*
* R89 (0x59) - Right Mixer Control
*/
#define WM8350_DACR_TO_MIXOUTR 0x1000
#define WM8350_DACL_TO_MIXOUTR 0x0800
#define WM8350_IN3R_TO_MIXOUTR 0x0008
#define WM8350_INR_TO_MIXOUTR 0x0002
#define WM8350_INL_TO_MIXOUTR 0x0001
/*
* R92 (0x5C) - OUT3 Mixer Control
*/
#define WM8350_DACL_TO_OUT3 0x0800
#define WM8350_MIXINL_TO_OUT3 0x0100
#define WM8350_OUT4_TO_OUT3 0x0008
#define WM8350_MIXOUTL_TO_OUT3 0x0001
/*
* R93 (0x5D) - OUT4 Mixer Control
*/
#define WM8350_DACR_TO_OUT4 0x1000
#define WM8350_DACL_TO_OUT4 0x0800
#define WM8350_OUT4_ATTN 0x0400
#define WM8350_MIXINR_TO_OUT4 0x0200
#define WM8350_OUT3_TO_OUT4 0x0004
#define WM8350_MIXOUTR_TO_OUT4 0x0002
#define WM8350_MIXOUTL_TO_OUT4 0x0001
/*
* R96 (0x60) - Output Left Mixer Volume
*/
#define WM8350_IN3L_MIXOUTL_VOL_MASK 0x0E00
#define WM8350_IN3L_MIXOUTL_VOL_SHIFT 9
#define WM8350_INR_MIXOUTL_VOL_MASK 0x00E0
#define WM8350_INR_MIXOUTL_VOL_SHIFT 5
#define WM8350_INL_MIXOUTL_VOL_MASK 0x000E
#define WM8350_INL_MIXOUTL_VOL_SHIFT 1
/* Bit values for R96 (0x60) */
#define WM8350_IN3L_MIXOUTL_VOL_OFF 0
#define WM8350_IN3L_MIXOUTL_VOL_M12DB 1
#define WM8350_IN3L_MIXOUTL_VOL_M9DB 2
#define WM8350_IN3L_MIXOUTL_VOL_M6DB 3
#define WM8350_IN3L_MIXOUTL_VOL_M3DB 4
#define WM8350_IN3L_MIXOUTL_VOL_0DB 5
#define WM8350_IN3L_MIXOUTL_VOL_3DB 6
#define WM8350_IN3L_MIXOUTL_VOL_6DB 7
#define WM8350_INR_MIXOUTL_VOL_OFF 0
#define WM8350_INR_MIXOUTL_VOL_M12DB 1
#define WM8350_INR_MIXOUTL_VOL_M9DB 2
#define WM8350_INR_MIXOUTL_VOL_M6DB 3
#define WM8350_INR_MIXOUTL_VOL_M3DB 4
#define WM8350_INR_MIXOUTL_VOL_0DB 5
#define WM8350_INR_MIXOUTL_VOL_3DB 6
#define WM8350_INR_MIXOUTL_VOL_6DB 7
#define WM8350_INL_MIXOUTL_VOL_OFF 0
#define WM8350_INL_MIXOUTL_VOL_M12DB 1
#define WM8350_INL_MIXOUTL_VOL_M9DB 2
#define WM8350_INL_MIXOUTL_VOL_M6DB 3
#define WM8350_INL_MIXOUTL_VOL_M3DB 4
#define WM8350_INL_MIXOUTL_VOL_0DB 5
#define WM8350_INL_MIXOUTL_VOL_3DB 6
#define WM8350_INL_MIXOUTL_VOL_6DB 7
/*
* R97 (0x61) - Output Right Mixer Volume
*/
#define WM8350_IN3R_MIXOUTR_VOL_MASK 0xE000
#define WM8350_IN3R_MIXOUTR_VOL_SHIFT 13
#define WM8350_INR_MIXOUTR_VOL_MASK 0x00E0
#define WM8350_INR_MIXOUTR_VOL_SHIFT 5
#define WM8350_INL_MIXOUTR_VOL_MASK 0x000E
#define WM8350_INL_MIXOUTR_VOL_SHIFT 1
/* Bit values for R96 (0x60) */
#define WM8350_IN3R_MIXOUTR_VOL_OFF 0
#define WM8350_IN3R_MIXOUTR_VOL_M12DB 1
#define WM8350_IN3R_MIXOUTR_VOL_M9DB 2
#define WM8350_IN3R_MIXOUTR_VOL_M6DB 3
#define WM8350_IN3R_MIXOUTR_VOL_M3DB 4
#define WM8350_IN3R_MIXOUTR_VOL_0DB 5
#define WM8350_IN3R_MIXOUTR_VOL_3DB 6
#define WM8350_IN3R_MIXOUTR_VOL_6DB 7
#define WM8350_INR_MIXOUTR_VOL_OFF 0
#define WM8350_INR_MIXOUTR_VOL_M12DB 1
#define WM8350_INR_MIXOUTR_VOL_M9DB 2
#define WM8350_INR_MIXOUTR_VOL_M6DB 3
#define WM8350_INR_MIXOUTR_VOL_M3DB 4
#define WM8350_INR_MIXOUTR_VOL_0DB 5
#define WM8350_INR_MIXOUTR_VOL_3DB 6
#define WM8350_INR_MIXOUTR_VOL_6DB 7
#define WM8350_INL_MIXOUTR_VOL_OFF 0
#define WM8350_INL_MIXOUTR_VOL_M12DB 1
#define WM8350_INL_MIXOUTR_VOL_M9DB 2
#define WM8350_INL_MIXOUTR_VOL_M6DB 3
#define WM8350_INL_MIXOUTR_VOL_M3DB 4
#define WM8350_INL_MIXOUTR_VOL_0DB 5
#define WM8350_INL_MIXOUTR_VOL_3DB 6
#define WM8350_INL_MIXOUTR_VOL_6DB 7
/*
* R98 (0x62) - Input Mixer Volume L
*/
#define WM8350_IN3L_MIXINL_VOL_MASK 0x0E00
#define WM8350_IN2L_MIXINL_VOL_MASK 0x000E
#define WM8350_INL_MIXINL_VOL 0x0001
/*
* R99 (0x63) - Input Mixer Volume R
*/
#define WM8350_IN3R_MIXINR_VOL_MASK 0xE000
#define WM8350_IN2R_MIXINR_VOL_MASK 0x00E0
#define WM8350_INR_MIXINR_VOL 0x0001
/*
* R100 (0x64) - Input Mixer Volume
*/
#define WM8350_OUT4_MIXIN_DST 0x8000
#define WM8350_OUT4_MIXIN_VOL_MASK 0x000E
/*
* R104 (0x68) - LOUT1 Volume
*/
#define WM8350_OUT1L_MUTE 0x4000
#define WM8350_OUT1L_ZC 0x2000
#define WM8350_OUT1_VU 0x0100
#define WM8350_OUT1L_VOL_MASK 0x00FC
#define WM8350_OUT1L_VOL_SHIFT 2
/*
* R105 (0x69) - ROUT1 Volume
*/
#define WM8350_OUT1R_MUTE 0x4000
#define WM8350_OUT1R_ZC 0x2000
#define WM8350_OUT1_VU 0x0100
#define WM8350_OUT1R_VOL_MASK 0x00FC
#define WM8350_OUT1R_VOL_SHIFT 2
/*
* R106 (0x6A) - LOUT2 Volume
*/
#define WM8350_OUT2L_MUTE 0x4000
#define WM8350_OUT2L_ZC 0x2000
#define WM8350_OUT2_VU 0x0100
#define WM8350_OUT2L_VOL_MASK 0x00FC
/*
* R107 (0x6B) - ROUT2 Volume
*/
#define WM8350_OUT2R_MUTE 0x4000
#define WM8350_OUT2R_ZC 0x2000
#define WM8350_OUT2R_INV 0x0400
#define WM8350_OUT2R_INV_MUTE 0x0200
#define WM8350_OUT2_VU 0x0100
#define WM8350_OUT2R_VOL_MASK 0x00FC
/*
* R111 (0x6F) - BEEP Volume
*/
#define WM8350_IN3R_OUT2R_VOL_MASK 0x00E0
/*
* R112 (0x70) - AI Formating
*/
#define WM8350_AIF_BCLK_INV 0x8000
#define WM8350_AIF_TRI 0x2000
#define WM8350_AIF_LRCLK_INV 0x1000
#define WM8350_AIF_WL_MASK 0x0C00
#define WM8350_AIF_FMT_MASK 0x0300
/*
* R113 (0x71) - ADC DAC COMP
*/
#define WM8350_DAC_COMP 0x0080
#define WM8350_DAC_COMPMODE 0x0040
#define WM8350_ADC_COMP 0x0020
#define WM8350_ADC_COMPMODE 0x0010
#define WM8350_LOOPBACK 0x0001
/*
* R114 (0x72) - AI ADC Control
*/
#define WM8350_AIFADC_PD 0x0080
#define WM8350_AIFADCL_SRC 0x0040
#define WM8350_AIFADCR_SRC 0x0020
#define WM8350_AIFADC_TDM_CHAN 0x0010
#define WM8350_AIFADC_TDM 0x0008
/*
* R115 (0x73) - AI DAC Control
*/
#define WM8350_BCLK_MSTR 0x4000
#define WM8350_AIFDAC_PD 0x0080
#define WM8350_DACL_SRC 0x0040
#define WM8350_DACR_SRC 0x0020
#define WM8350_AIFDAC_TDM_CHAN 0x0010
#define WM8350_AIFDAC_TDM 0x0008
#define WM8350_DAC_BOOST_MASK 0x0003
/*
* R116 (0x74) - AIF Test
*/
#define WM8350_CODEC_BYP 0x4000
#define WM8350_AIFADC_WR_TST 0x2000
#define WM8350_AIFADC_RD_TST 0x1000
#define WM8350_AIFDAC_WR_TST 0x0800
#define WM8350_AIFDAC_RD_TST 0x0400
#define WM8350_AIFADC_ASYN 0x0020
#define WM8350_AIFDAC_ASYN 0x0010
/*
* R231 (0xE7) - Jack Status
*/
#define WM8350_JACK_R_LVL 0x0400
/*
* WM8350 Platform setup
*/
#define WM8350_S_CURVE_NONE 0x0
#define WM8350_S_CURVE_FAST 0x1
#define WM8350_S_CURVE_MEDIUM 0x2
#define WM8350_S_CURVE_SLOW 0x3
#define WM8350_DISCHARGE_OFF 0x0
#define WM8350_DISCHARGE_FAST 0x1
#define WM8350_DISCHARGE_MEDIUM 0x2
#define WM8350_DISCHARGE_SLOW 0x3
#define WM8350_TIE_OFF_500R 0x0
#define WM8350_TIE_OFF_30K 0x1
/*
* Clock sources & directions
*/
#define WM8350_SYSCLK 0
#define WM8350_MCLK_SEL_PLL_MCLK 0
#define WM8350_MCLK_SEL_PLL_DAC 1
#define WM8350_MCLK_SEL_PLL_ADC 2
#define WM8350_MCLK_SEL_PLL_32K 3
#define WM8350_MCLK_SEL_MCLK 5
#define WM8350_MCLK_DIR_OUT 0
#define WM8350_MCLK_DIR_IN 1
/* clock divider id's */
#define WM8350_ADC_CLKDIV 0
#define WM8350_DAC_CLKDIV 1
#define WM8350_BCLK_CLKDIV 2
#define WM8350_OPCLK_CLKDIV 3
#define WM8350_TO_CLKDIV 4
#define WM8350_SYS_CLKDIV 5
#define WM8350_DACLR_CLKDIV 6
#define WM8350_ADCLR_CLKDIV 7
/* ADC clock dividers */
#define WM8350_ADCDIV_1 0x0
#define WM8350_ADCDIV_1_5 0x1
#define WM8350_ADCDIV_2 0x2
#define WM8350_ADCDIV_3 0x3
#define WM8350_ADCDIV_4 0x4
#define WM8350_ADCDIV_5_5 0x5
#define WM8350_ADCDIV_6 0x6
/* ADC clock dividers */
#define WM8350_DACDIV_1 0x0
#define WM8350_DACDIV_1_5 0x1
#define WM8350_DACDIV_2 0x2
#define WM8350_DACDIV_3 0x3
#define WM8350_DACDIV_4 0x4
#define WM8350_DACDIV_5_5 0x5
#define WM8350_DACDIV_6 0x6
/* BCLK clock dividers */
#define WM8350_BCLK_DIV_1 (0x0 << 4)
#define WM8350_BCLK_DIV_1_5 (0x1 << 4)
#define WM8350_BCLK_DIV_2 (0x2 << 4)
#define WM8350_BCLK_DIV_3 (0x3 << 4)
#define WM8350_BCLK_DIV_4 (0x4 << 4)
#define WM8350_BCLK_DIV_5_5 (0x5 << 4)
#define WM8350_BCLK_DIV_6 (0x6 << 4)
#define WM8350_BCLK_DIV_8 (0x7 << 4)
#define WM8350_BCLK_DIV_11 (0x8 << 4)
#define WM8350_BCLK_DIV_12 (0x9 << 4)
#define WM8350_BCLK_DIV_16 (0xa << 4)
#define WM8350_BCLK_DIV_22 (0xb << 4)
#define WM8350_BCLK_DIV_24 (0xc << 4)
#define WM8350_BCLK_DIV_32 (0xd << 4)
#define WM8350_BCLK_DIV_44 (0xe << 4)
#define WM8350_BCLK_DIV_48 (0xf << 4)
/* Sys (MCLK) clock dividers */
#define WM8350_MCLK_DIV_1 (0x0 << 8)
#define WM8350_MCLK_DIV_2 (0x1 << 8)
/* OP clock dividers */
#define WM8350_OPCLK_DIV_1 0x0
#define WM8350_OPCLK_DIV_2 0x1
#define WM8350_OPCLK_DIV_3 0x2
#define WM8350_OPCLK_DIV_4 0x3
#define WM8350_OPCLK_DIV_5_5 0x4
#define WM8350_OPCLK_DIV_6 0x5
/* DAI ID */
#define WM8350_HIFI_DAI 0
/*
* Audio interrupts.
*/
#define WM8350_IRQ_CODEC_JCK_DET_L 39
#define WM8350_IRQ_CODEC_JCK_DET_R 40
#define WM8350_IRQ_CODEC_MICSCD 41
#define WM8350_IRQ_CODEC_MICD 42
struct wm8350_codec {
struct platform_device *pdev;
};
#endif

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/*
* comparator.h -- Comparator Aux ADC for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_WM8350_COMPARATOR_H_
#define __LINUX_MFD_WM8350_COMPARATOR_H_
/*
* Registers
*/
#define WM8350_DIGITISER_CONTROL_1 0x90
#define WM8350_DIGITISER_CONTROL_2 0x91
#define WM8350_AUX1_READBACK 0x98
#define WM8350_AUX2_READBACK 0x99
#define WM8350_AUX3_READBACK 0x9A
#define WM8350_AUX4_READBACK 0x9B
#define WM8350_CHIP_TEMP_READBACK 0x9F
#define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3
#define WM8350_GENERIC_COMPARATOR_1 0xA4
#define WM8350_GENERIC_COMPARATOR_2 0xA5
#define WM8350_GENERIC_COMPARATOR_3 0xA6
#define WM8350_GENERIC_COMPARATOR_4 0xA7
/*
* R144 (0x90) - Digitiser Control (1)
*/
#define WM8350_AUXADC_CTC 0x4000
#define WM8350_AUXADC_POLL 0x2000
#define WM8350_AUXADC_HIB_MODE 0x1000
#define WM8350_AUXADC_SEL8 0x0080
#define WM8350_AUXADC_SEL7 0x0040
#define WM8350_AUXADC_SEL6 0x0020
#define WM8350_AUXADC_SEL5 0x0010
#define WM8350_AUXADC_SEL4 0x0008
#define WM8350_AUXADC_SEL3 0x0004
#define WM8350_AUXADC_SEL2 0x0002
#define WM8350_AUXADC_SEL1 0x0001
/*
* R145 (0x91) - Digitiser Control (2)
*/
#define WM8350_AUXADC_MASKMODE_MASK 0x3000
#define WM8350_AUXADC_CRATE_MASK 0x0700
#define WM8350_AUXADC_CAL 0x0004
#define WM8350_AUX_RBMODE 0x0002
#define WM8350_AUXADC_WAIT 0x0001
/*
* R152 (0x98) - AUX1 Readback
*/
#define WM8350_AUXADC_SCALE1_MASK 0x6000
#define WM8350_AUXADC_REF1 0x1000
#define WM8350_AUXADC_DATA1_MASK 0x0FFF
/*
* R153 (0x99) - AUX2 Readback
*/
#define WM8350_AUXADC_SCALE2_MASK 0x6000
#define WM8350_AUXADC_REF2 0x1000
#define WM8350_AUXADC_DATA2_MASK 0x0FFF
/*
* R154 (0x9A) - AUX3 Readback
*/
#define WM8350_AUXADC_SCALE3_MASK 0x6000
#define WM8350_AUXADC_REF3 0x1000
#define WM8350_AUXADC_DATA3_MASK 0x0FFF
/*
* R155 (0x9B) - AUX4 Readback
*/
#define WM8350_AUXADC_SCALE4_MASK 0x6000
#define WM8350_AUXADC_REF4 0x1000
#define WM8350_AUXADC_DATA4_MASK 0x0FFF
/*
* R156 (0x9C) - USB Voltage Readback
*/
#define WM8350_AUXADC_DATA_USB_MASK 0x0FFF
/*
* R157 (0x9D) - LINE Voltage Readback
*/
#define WM8350_AUXADC_DATA_LINE_MASK 0x0FFF
/*
* R158 (0x9E) - BATT Voltage Readback
*/
#define WM8350_AUXADC_DATA_BATT_MASK 0x0FFF
/*
* R159 (0x9F) - Chip Temp Readback
*/
#define WM8350_AUXADC_DATA_CHIPTEMP_MASK 0x0FFF
/*
* R163 (0xA3) - Generic Comparator Control
*/
#define WM8350_DCMP4_ENA 0x0008
#define WM8350_DCMP3_ENA 0x0004
#define WM8350_DCMP2_ENA 0x0002
#define WM8350_DCMP1_ENA 0x0001
/*
* R164 (0xA4) - Generic comparator 1
*/
#define WM8350_DCMP1_SRCSEL_MASK 0xE000
#define WM8350_DCMP1_GT 0x1000
#define WM8350_DCMP1_THR_MASK 0x0FFF
/*
* R165 (0xA5) - Generic comparator 2
*/
#define WM8350_DCMP2_SRCSEL_MASK 0xE000
#define WM8350_DCMP2_GT 0x1000
#define WM8350_DCMP2_THR_MASK 0x0FFF
/*
* R166 (0xA6) - Generic comparator 3
*/
#define WM8350_DCMP3_SRCSEL_MASK 0xE000
#define WM8350_DCMP3_GT 0x1000
#define WM8350_DCMP3_THR_MASK 0x0FFF
/*
* R167 (0xA7) - Generic comparator 4
*/
#define WM8350_DCMP4_SRCSEL_MASK 0xE000
#define WM8350_DCMP4_GT 0x1000
#define WM8350_DCMP4_THR_MASK 0x0FFF
/*
* Interrupts.
*/
#define WM8350_IRQ_AUXADC_DATARDY 16
#define WM8350_IRQ_AUXADC_DCOMP4 17
#define WM8350_IRQ_AUXADC_DCOMP3 18
#define WM8350_IRQ_AUXADC_DCOMP2 19
#define WM8350_IRQ_AUXADC_DCOMP1 20
#define WM8350_IRQ_SYS_HYST_COMP_FAIL 21
#define WM8350_IRQ_SYS_CHIP_GT115 22
#define WM8350_IRQ_SYS_CHIP_GT140 23
/*
* USB/2, LINE & BATT = ((VRTC * 2) / 4095)) * 10e6 uV
* Where VRTC = 2.7 V
*/
#define WM8350_AUX_COEFF 1319
#define WM8350_AUXADC_AUX1 0
#define WM8350_AUXADC_AUX2 1
#define WM8350_AUXADC_AUX3 2
#define WM8350_AUXADC_AUX4 3
#define WM8350_AUXADC_USB 4
#define WM8350_AUXADC_LINE 5
#define WM8350_AUXADC_BATT 6
#define WM8350_AUXADC_TEMP 7
#endif

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/*
* core.h -- Core Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_CORE_H_
#define __LINUX_MFD_WM8350_CORE_H_
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/gpio.h>
#include <linux/mfd/wm8350/pmic.h>
#include <linux/mfd/wm8350/rtc.h>
#include <linux/mfd/wm8350/supply.h>
#include <linux/mfd/wm8350/wdt.h>
/*
* Register values.
*/
#define WM8350_RESET_ID 0x00
#define WM8350_ID 0x01
#define WM8350_SYSTEM_CONTROL_1 0x03
#define WM8350_SYSTEM_CONTROL_2 0x04
#define WM8350_SYSTEM_HIBERNATE 0x05
#define WM8350_INTERFACE_CONTROL 0x06
#define WM8350_POWER_MGMT_1 0x08
#define WM8350_POWER_MGMT_2 0x09
#define WM8350_POWER_MGMT_3 0x0A
#define WM8350_POWER_MGMT_4 0x0B
#define WM8350_POWER_MGMT_5 0x0C
#define WM8350_POWER_MGMT_6 0x0D
#define WM8350_POWER_MGMT_7 0x0E
#define WM8350_SYSTEM_INTERRUPTS 0x18
#define WM8350_INT_STATUS_1 0x19
#define WM8350_INT_STATUS_2 0x1A
#define WM8350_POWER_UP_INT_STATUS 0x1B
#define WM8350_UNDER_VOLTAGE_INT_STATUS 0x1C
#define WM8350_OVER_CURRENT_INT_STATUS 0x1D
#define WM8350_GPIO_INT_STATUS 0x1E
#define WM8350_COMPARATOR_INT_STATUS 0x1F
#define WM8350_SYSTEM_INTERRUPTS_MASK 0x20
#define WM8350_INT_STATUS_1_MASK 0x21
#define WM8350_INT_STATUS_2_MASK 0x22
#define WM8350_POWER_UP_INT_STATUS_MASK 0x23
#define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK 0x24
#define WM8350_OVER_CURRENT_INT_STATUS_MASK 0x25
#define WM8350_GPIO_INT_STATUS_MASK 0x26
#define WM8350_COMPARATOR_INT_STATUS_MASK 0x27
#define WM8350_MAX_REGISTER 0xFF
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Reset/ID
*/
#define WM8350_SW_RESET_CHIP_ID_MASK 0xFFFF
/*
* R1 (0x01) - ID
*/
#define WM8350_CHIP_REV_MASK 0x7000
#define WM8350_CONF_STS_MASK 0x0C00
#define WM8350_CUST_ID_MASK 0x00FF
/*
* R3 (0x03) - System Control 1
*/
#define WM8350_CHIP_ON 0x8000
#define WM8350_POWERCYCLE 0x2000
#define WM8350_VCC_FAULT_OV 0x1000
#define WM8350_REG_RSTB_TIME_MASK 0x0C00
#define WM8350_BG_SLEEP 0x0200
#define WM8350_MEM_VALID 0x0020
#define WM8350_CHIP_SET_UP 0x0010
#define WM8350_ON_DEB_T 0x0008
#define WM8350_ON_POL 0x0002
#define WM8350_IRQ_POL 0x0001
/*
* R4 (0x04) - System Control 2
*/
#define WM8350_USB_SUSPEND_8MA 0x8000
#define WM8350_USB_SUSPEND 0x4000
#define WM8350_USB_MSTR 0x2000
#define WM8350_USB_MSTR_SRC 0x1000
#define WM8350_USB_500MA 0x0800
#define WM8350_USB_NOLIM 0x0400
/*
* R5 (0x05) - System Hibernate
*/
#define WM8350_HIBERNATE 0x8000
#define WM8350_WDOG_HIB_MODE 0x0080
#define WM8350_REG_HIB_STARTUP_SEQ 0x0040
#define WM8350_REG_RESET_HIB_MODE 0x0020
#define WM8350_RST_HIB_MODE 0x0010
#define WM8350_IRQ_HIB_MODE 0x0008
#define WM8350_MEMRST_HIB_MODE 0x0004
#define WM8350_PCCOMP_HIB_MODE 0x0002
#define WM8350_TEMPMON_HIB_MODE 0x0001
/*
* R6 (0x06) - Interface Control
*/
#define WM8350_USE_DEV_PINS 0x8000
#define WM8350_USE_DEV_PINS_MASK 0x8000
#define WM8350_USE_DEV_PINS_SHIFT 15
#define WM8350_DEV_ADDR_MASK 0x6000
#define WM8350_DEV_ADDR_SHIFT 13
#define WM8350_CONFIG_DONE 0x1000
#define WM8350_CONFIG_DONE_MASK 0x1000
#define WM8350_CONFIG_DONE_SHIFT 12
#define WM8350_RECONFIG_AT_ON 0x0800
#define WM8350_RECONFIG_AT_ON_MASK 0x0800
#define WM8350_RECONFIG_AT_ON_SHIFT 11
#define WM8350_AUTOINC 0x0200
#define WM8350_AUTOINC_MASK 0x0200
#define WM8350_AUTOINC_SHIFT 9
#define WM8350_ARA 0x0100
#define WM8350_ARA_MASK 0x0100
#define WM8350_ARA_SHIFT 8
#define WM8350_SPI_CFG 0x0008
#define WM8350_SPI_CFG_MASK 0x0008
#define WM8350_SPI_CFG_SHIFT 3
#define WM8350_SPI_4WIRE 0x0004
#define WM8350_SPI_4WIRE_MASK 0x0004
#define WM8350_SPI_4WIRE_SHIFT 2
#define WM8350_SPI_3WIRE 0x0002
#define WM8350_SPI_3WIRE_MASK 0x0002
#define WM8350_SPI_3WIRE_SHIFT 1
/* Bit values for R06 (0x06) */
#define WM8350_USE_DEV_PINS_PRIMARY 0
#define WM8350_USE_DEV_PINS_DEV 1
#define WM8350_DEV_ADDR_34 0
#define WM8350_DEV_ADDR_36 1
#define WM8350_DEV_ADDR_3C 2
#define WM8350_DEV_ADDR_3E 3
#define WM8350_CONFIG_DONE_OFF 0
#define WM8350_CONFIG_DONE_DONE 1
#define WM8350_RECONFIG_AT_ON_OFF 0
#define WM8350_RECONFIG_AT_ON_ON 1
#define WM8350_AUTOINC_OFF 0
#define WM8350_AUTOINC_ON 1
#define WM8350_ARA_OFF 0
#define WM8350_ARA_ON 1
#define WM8350_SPI_CFG_CMOS 0
#define WM8350_SPI_CFG_OD 1
#define WM8350_SPI_4WIRE_3WIRE 0
#define WM8350_SPI_4WIRE_4WIRE 1
#define WM8350_SPI_3WIRE_I2C 0
#define WM8350_SPI_3WIRE_SPI 1
/*
* R8 (0x08) - Power mgmt (1)
*/
#define WM8350_CODEC_ISEL_MASK 0xC000
#define WM8350_VBUFEN 0x2000
#define WM8350_OUTPUT_DRAIN_EN 0x0400
#define WM8350_MIC_DET_ENA 0x0100
#define WM8350_BIASEN 0x0020
#define WM8350_MICBEN 0x0010
#define WM8350_VMIDEN 0x0004
#define WM8350_VMID_MASK 0x0003
#define WM8350_VMID_SHIFT 0
/*
* R9 (0x09) - Power mgmt (2)
*/
#define WM8350_IN3R_ENA 0x0800
#define WM8350_IN3L_ENA 0x0400
#define WM8350_INR_ENA 0x0200
#define WM8350_INL_ENA 0x0100
#define WM8350_MIXINR_ENA 0x0080
#define WM8350_MIXINL_ENA 0x0040
#define WM8350_OUT4_ENA 0x0020
#define WM8350_OUT3_ENA 0x0010
#define WM8350_MIXOUTR_ENA 0x0002
#define WM8350_MIXOUTL_ENA 0x0001
/*
* R10 (0x0A) - Power mgmt (3)
*/
#define WM8350_IN3R_TO_OUT2R 0x0080
#define WM8350_OUT2R_ENA 0x0008
#define WM8350_OUT2L_ENA 0x0004
#define WM8350_OUT1R_ENA 0x0002
#define WM8350_OUT1L_ENA 0x0001
/*
* R11 (0x0B) - Power mgmt (4)
*/
#define WM8350_SYSCLK_ENA 0x4000
#define WM8350_ADC_HPF_ENA 0x2000
#define WM8350_FLL_ENA 0x0800
#define WM8350_FLL_OSC_ENA 0x0400
#define WM8350_TOCLK_ENA 0x0100
#define WM8350_DACR_ENA 0x0020
#define WM8350_DACL_ENA 0x0010
#define WM8350_ADCR_ENA 0x0008
#define WM8350_ADCL_ENA 0x0004
/*
* R12 (0x0C) - Power mgmt (5)
*/
#define WM8350_CODEC_ENA 0x1000
#define WM8350_RTC_TICK_ENA 0x0800
#define WM8350_OSC32K_ENA 0x0400
#define WM8350_CHG_ENA 0x0200
#define WM8350_ACC_DET_ENA 0x0100
#define WM8350_AUXADC_ENA 0x0080
#define WM8350_DCMP4_ENA 0x0008
#define WM8350_DCMP3_ENA 0x0004
#define WM8350_DCMP2_ENA 0x0002
#define WM8350_DCMP1_ENA 0x0001
/*
* R13 (0x0D) - Power mgmt (6)
*/
#define WM8350_LS_ENA 0x8000
#define WM8350_LDO4_ENA 0x0800
#define WM8350_LDO3_ENA 0x0400
#define WM8350_LDO2_ENA 0x0200
#define WM8350_LDO1_ENA 0x0100
#define WM8350_DC6_ENA 0x0020
#define WM8350_DC5_ENA 0x0010
#define WM8350_DC4_ENA 0x0008
#define WM8350_DC3_ENA 0x0004
#define WM8350_DC2_ENA 0x0002
#define WM8350_DC1_ENA 0x0001
/*
* R14 (0x0E) - Power mgmt (7)
*/
#define WM8350_CS2_ENA 0x0002
#define WM8350_CS1_ENA 0x0001
/*
* R24 (0x18) - System Interrupts
*/
#define WM8350_OC_INT 0x2000
#define WM8350_UV_INT 0x1000
#define WM8350_PUTO_INT 0x0800
#define WM8350_CS_INT 0x0200
#define WM8350_EXT_INT 0x0100
#define WM8350_CODEC_INT 0x0080
#define WM8350_GP_INT 0x0040
#define WM8350_AUXADC_INT 0x0020
#define WM8350_RTC_INT 0x0010
#define WM8350_SYS_INT 0x0008
#define WM8350_CHG_INT 0x0004
#define WM8350_USB_INT 0x0002
#define WM8350_WKUP_INT 0x0001
/*
* R25 (0x19) - Interrupt Status 1
*/
#define WM8350_CHG_BAT_HOT_EINT 0x8000
#define WM8350_CHG_BAT_COLD_EINT 0x4000
#define WM8350_CHG_BAT_FAIL_EINT 0x2000
#define WM8350_CHG_TO_EINT 0x1000
#define WM8350_CHG_END_EINT 0x0800
#define WM8350_CHG_START_EINT 0x0400
#define WM8350_CHG_FAST_RDY_EINT 0x0200
#define WM8350_RTC_PER_EINT 0x0080
#define WM8350_RTC_SEC_EINT 0x0040
#define WM8350_RTC_ALM_EINT 0x0020
#define WM8350_CHG_VBATT_LT_3P9_EINT 0x0004
#define WM8350_CHG_VBATT_LT_3P1_EINT 0x0002
#define WM8350_CHG_VBATT_LT_2P85_EINT 0x0001
/*
* R26 (0x1A) - Interrupt Status 2
*/
#define WM8350_CS1_EINT 0x2000
#define WM8350_CS2_EINT 0x1000
#define WM8350_USB_LIMIT_EINT 0x0400
#define WM8350_AUXADC_DATARDY_EINT 0x0100
#define WM8350_AUXADC_DCOMP4_EINT 0x0080
#define WM8350_AUXADC_DCOMP3_EINT 0x0040
#define WM8350_AUXADC_DCOMP2_EINT 0x0020
#define WM8350_AUXADC_DCOMP1_EINT 0x0010
#define WM8350_SYS_HYST_COMP_FAIL_EINT 0x0008
#define WM8350_SYS_CHIP_GT115_EINT 0x0004
#define WM8350_SYS_CHIP_GT140_EINT 0x0002
#define WM8350_SYS_WDOG_TO_EINT 0x0001
/*
* R27 (0x1B) - Power Up Interrupt Status
*/
#define WM8350_PUTO_LDO4_EINT 0x0800
#define WM8350_PUTO_LDO3_EINT 0x0400
#define WM8350_PUTO_LDO2_EINT 0x0200
#define WM8350_PUTO_LDO1_EINT 0x0100
#define WM8350_PUTO_DC6_EINT 0x0020
#define WM8350_PUTO_DC5_EINT 0x0010
#define WM8350_PUTO_DC4_EINT 0x0008
#define WM8350_PUTO_DC3_EINT 0x0004
#define WM8350_PUTO_DC2_EINT 0x0002
#define WM8350_PUTO_DC1_EINT 0x0001
/*
* R28 (0x1C) - Under Voltage Interrupt status
*/
#define WM8350_UV_LDO4_EINT 0x0800
#define WM8350_UV_LDO3_EINT 0x0400
#define WM8350_UV_LDO2_EINT 0x0200
#define WM8350_UV_LDO1_EINT 0x0100
#define WM8350_UV_DC6_EINT 0x0020
#define WM8350_UV_DC5_EINT 0x0010
#define WM8350_UV_DC4_EINT 0x0008
#define WM8350_UV_DC3_EINT 0x0004
#define WM8350_UV_DC2_EINT 0x0002
#define WM8350_UV_DC1_EINT 0x0001
/*
* R29 (0x1D) - Over Current Interrupt status
*/
#define WM8350_OC_LS_EINT 0x8000
/*
* R30 (0x1E) - GPIO Interrupt Status
*/
#define WM8350_GP12_EINT 0x1000
#define WM8350_GP11_EINT 0x0800
#define WM8350_GP10_EINT 0x0400
#define WM8350_GP9_EINT 0x0200
#define WM8350_GP8_EINT 0x0100
#define WM8350_GP7_EINT 0x0080
#define WM8350_GP6_EINT 0x0040
#define WM8350_GP5_EINT 0x0020
#define WM8350_GP4_EINT 0x0010
#define WM8350_GP3_EINT 0x0008
#define WM8350_GP2_EINT 0x0004
#define WM8350_GP1_EINT 0x0002
#define WM8350_GP0_EINT 0x0001
/*
* R31 (0x1F) - Comparator Interrupt Status
*/
#define WM8350_EXT_USB_FB_EINT 0x8000
#define WM8350_EXT_WALL_FB_EINT 0x4000
#define WM8350_EXT_BAT_FB_EINT 0x2000
#define WM8350_CODEC_JCK_DET_L_EINT 0x0800
#define WM8350_CODEC_JCK_DET_R_EINT 0x0400
#define WM8350_CODEC_MICSCD_EINT 0x0200
#define WM8350_CODEC_MICD_EINT 0x0100
#define WM8350_WKUP_OFF_STATE_EINT 0x0040
#define WM8350_WKUP_HIB_STATE_EINT 0x0020
#define WM8350_WKUP_CONV_FAULT_EINT 0x0010
#define WM8350_WKUP_WDOG_RST_EINT 0x0008
#define WM8350_WKUP_GP_PWR_ON_EINT 0x0004
#define WM8350_WKUP_ONKEY_EINT 0x0002
#define WM8350_WKUP_GP_WAKEUP_EINT 0x0001
/*
* R32 (0x20) - System Interrupts Mask
*/
#define WM8350_IM_OC_INT 0x2000
#define WM8350_IM_UV_INT 0x1000
#define WM8350_IM_PUTO_INT 0x0800
#define WM8350_IM_SPARE_INT 0x0400
#define WM8350_IM_CS_INT 0x0200
#define WM8350_IM_EXT_INT 0x0100
#define WM8350_IM_CODEC_INT 0x0080
#define WM8350_IM_GP_INT 0x0040
#define WM8350_IM_AUXADC_INT 0x0020
#define WM8350_IM_RTC_INT 0x0010
#define WM8350_IM_SYS_INT 0x0008
#define WM8350_IM_CHG_INT 0x0004
#define WM8350_IM_USB_INT 0x0002
#define WM8350_IM_WKUP_INT 0x0001
/*
* R33 (0x21) - Interrupt Status 1 Mask
*/
#define WM8350_IM_CHG_BAT_HOT_EINT 0x8000
#define WM8350_IM_CHG_BAT_COLD_EINT 0x4000
#define WM8350_IM_CHG_BAT_FAIL_EINT 0x2000
#define WM8350_IM_CHG_TO_EINT 0x1000
#define WM8350_IM_CHG_END_EINT 0x0800
#define WM8350_IM_CHG_START_EINT 0x0400
#define WM8350_IM_CHG_FAST_RDY_EINT 0x0200
#define WM8350_IM_RTC_PER_EINT 0x0080
#define WM8350_IM_RTC_SEC_EINT 0x0040
#define WM8350_IM_RTC_ALM_EINT 0x0020
#define WM8350_IM_CHG_VBATT_LT_3P9_EINT 0x0004
#define WM8350_IM_CHG_VBATT_LT_3P1_EINT 0x0002
#define WM8350_IM_CHG_VBATT_LT_2P85_EINT 0x0001
/*
* R34 (0x22) - Interrupt Status 2 Mask
*/
#define WM8350_IM_SPARE2_EINT 0x8000
#define WM8350_IM_SPARE1_EINT 0x4000
#define WM8350_IM_CS1_EINT 0x2000
#define WM8350_IM_CS2_EINT 0x1000
#define WM8350_IM_USB_LIMIT_EINT 0x0400
#define WM8350_IM_AUXADC_DATARDY_EINT 0x0100
#define WM8350_IM_AUXADC_DCOMP4_EINT 0x0080
#define WM8350_IM_AUXADC_DCOMP3_EINT 0x0040
#define WM8350_IM_AUXADC_DCOMP2_EINT 0x0020
#define WM8350_IM_AUXADC_DCOMP1_EINT 0x0010
#define WM8350_IM_SYS_HYST_COMP_FAIL_EINT 0x0008
#define WM8350_IM_SYS_CHIP_GT115_EINT 0x0004
#define WM8350_IM_SYS_CHIP_GT140_EINT 0x0002
#define WM8350_IM_SYS_WDOG_TO_EINT 0x0001
/*
* R35 (0x23) - Power Up Interrupt Status Mask
*/
#define WM8350_IM_PUTO_LDO4_EINT 0x0800
#define WM8350_IM_PUTO_LDO3_EINT 0x0400
#define WM8350_IM_PUTO_LDO2_EINT 0x0200
#define WM8350_IM_PUTO_LDO1_EINT 0x0100
#define WM8350_IM_PUTO_DC6_EINT 0x0020
#define WM8350_IM_PUTO_DC5_EINT 0x0010
#define WM8350_IM_PUTO_DC4_EINT 0x0008
#define WM8350_IM_PUTO_DC3_EINT 0x0004
#define WM8350_IM_PUTO_DC2_EINT 0x0002
#define WM8350_IM_PUTO_DC1_EINT 0x0001
/*
* R36 (0x24) - Under Voltage Interrupt status Mask
*/
#define WM8350_IM_UV_LDO4_EINT 0x0800
#define WM8350_IM_UV_LDO3_EINT 0x0400
#define WM8350_IM_UV_LDO2_EINT 0x0200
#define WM8350_IM_UV_LDO1_EINT 0x0100
#define WM8350_IM_UV_DC6_EINT 0x0020
#define WM8350_IM_UV_DC5_EINT 0x0010
#define WM8350_IM_UV_DC4_EINT 0x0008
#define WM8350_IM_UV_DC3_EINT 0x0004
#define WM8350_IM_UV_DC2_EINT 0x0002
#define WM8350_IM_UV_DC1_EINT 0x0001
/*
* R37 (0x25) - Over Current Interrupt status Mask
*/
#define WM8350_IM_OC_LS_EINT 0x8000
/*
* R38 (0x26) - GPIO Interrupt Status Mask
*/
#define WM8350_IM_GP12_EINT 0x1000
#define WM8350_IM_GP11_EINT 0x0800
#define WM8350_IM_GP10_EINT 0x0400
#define WM8350_IM_GP9_EINT 0x0200
#define WM8350_IM_GP8_EINT 0x0100
#define WM8350_IM_GP7_EINT 0x0080
#define WM8350_IM_GP6_EINT 0x0040
#define WM8350_IM_GP5_EINT 0x0020
#define WM8350_IM_GP4_EINT 0x0010
#define WM8350_IM_GP3_EINT 0x0008
#define WM8350_IM_GP2_EINT 0x0004
#define WM8350_IM_GP1_EINT 0x0002
#define WM8350_IM_GP0_EINT 0x0001
/*
* R39 (0x27) - Comparator Interrupt Status Mask
*/
#define WM8350_IM_EXT_USB_FB_EINT 0x8000
#define WM8350_IM_EXT_WALL_FB_EINT 0x4000
#define WM8350_IM_EXT_BAT_FB_EINT 0x2000
#define WM8350_IM_CODEC_JCK_DET_L_EINT 0x0800
#define WM8350_IM_CODEC_JCK_DET_R_EINT 0x0400
#define WM8350_IM_CODEC_MICSCD_EINT 0x0200
#define WM8350_IM_CODEC_MICD_EINT 0x0100
#define WM8350_IM_WKUP_OFF_STATE_EINT 0x0040
#define WM8350_IM_WKUP_HIB_STATE_EINT 0x0020
#define WM8350_IM_WKUP_CONV_FAULT_EINT 0x0010
#define WM8350_IM_WKUP_WDOG_RST_EINT 0x0008
#define WM8350_IM_WKUP_GP_PWR_ON_EINT 0x0004
#define WM8350_IM_WKUP_ONKEY_EINT 0x0002
#define WM8350_IM_WKUP_GP_WAKEUP_EINT 0x0001
/*
* R220 (0xDC) - RAM BIST 1
*/
#define WM8350_READ_STATUS 0x0800
#define WM8350_TSTRAM_CLK 0x0100
#define WM8350_TSTRAM_CLK_ENA 0x0080
#define WM8350_STARTSEQ 0x0040
#define WM8350_READ_SRC 0x0020
#define WM8350_COUNT_DIR 0x0010
#define WM8350_TSTRAM_MODE_MASK 0x000E
#define WM8350_TSTRAM_ENA 0x0001
/*
* R225 (0xE1) - DCDC/LDO status
*/
#define WM8350_LS_STS 0x8000
#define WM8350_LDO4_STS 0x0800
#define WM8350_LDO3_STS 0x0400
#define WM8350_LDO2_STS 0x0200
#define WM8350_LDO1_STS 0x0100
#define WM8350_DC6_STS 0x0020
#define WM8350_DC5_STS 0x0010
#define WM8350_DC4_STS 0x0008
#define WM8350_DC3_STS 0x0004
#define WM8350_DC2_STS 0x0002
#define WM8350_DC1_STS 0x0001
/* WM8350 wake up conditions */
#define WM8350_IRQ_WKUP_OFF_STATE 43
#define WM8350_IRQ_WKUP_HIB_STATE 44
#define WM8350_IRQ_WKUP_CONV_FAULT 45
#define WM8350_IRQ_WKUP_WDOG_RST 46
#define WM8350_IRQ_WKUP_GP_PWR_ON 47
#define WM8350_IRQ_WKUP_ONKEY 48
#define WM8350_IRQ_WKUP_GP_WAKEUP 49
/* wm8350 chip revisions */
#define WM8350_REV_E 0x4
#define WM8350_REV_F 0x5
#define WM8350_REV_G 0x6
#define WM8350_NUM_IRQ 63
struct wm8350_reg_access {
u16 readable; /* Mask of readable bits */
u16 writable; /* Mask of writable bits */
u16 vol; /* Mask of volatile bits */
};
extern const struct wm8350_reg_access wm8350_reg_io_map[];
extern const u16 wm8350_mode0_defaults[];
extern const u16 wm8350_mode1_defaults[];
extern const u16 wm8350_mode2_defaults[];
extern const u16 wm8350_mode3_defaults[];
struct wm8350;
struct wm8350_irq {
void (*handler) (struct wm8350 *, int, void *);
void *data;
};
struct wm8350 {
int rev; /* chip revision */
struct device *dev;
/* device IO */
union {
struct i2c_client *i2c_client;
struct spi_device *spi_device;
};
int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
void *src);
u16 *reg_cache;
/* Interrupt handling */
struct work_struct irq_work;
struct mutex irq_mutex; /* IRQ table mutex */
struct wm8350_irq irq[WM8350_NUM_IRQ];
int chip_irq;
/* Client devices */
struct wm8350_codec codec;
struct wm8350_gpio gpio;
struct wm8350_pmic pmic;
struct wm8350_power power;
struct wm8350_rtc rtc;
struct wm8350_wdt wdt;
};
/**
* Data to be supplied by the platform to initialise the WM8350.
*
* @init: Function called during driver initialisation. Should be
* used by the platform to configure GPIO functions and similar.
*/
struct wm8350_platform_data {
int (*init)(struct wm8350 *wm8350);
};
/*
* WM8350 device initialisation and exit.
*/
int wm8350_device_init(struct wm8350 *wm8350, int irq,
struct wm8350_platform_data *pdata);
void wm8350_device_exit(struct wm8350 *wm8350);
/*
* WM8350 device IO
*/
int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
u16 wm8350_reg_read(struct wm8350 *wm8350, int reg);
int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val);
int wm8350_reg_lock(struct wm8350 *wm8350);
int wm8350_reg_unlock(struct wm8350 *wm8350);
int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest);
int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
/*
* WM8350 internal interrupts
*/
int wm8350_register_irq(struct wm8350 *wm8350, int irq,
void (*handler) (struct wm8350 *, int, void *),
void *data);
int wm8350_free_irq(struct wm8350 *wm8350, int irq);
int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
#endif

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include/linux/mfd/wm8350/gpio.h Normal file
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/*
* gpio.h -- GPIO Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_GPIO_H_
#define __LINUX_MFD_WM8350_GPIO_H_
#include <linux/platform_device.h>
/*
* GPIO Registers.
*/
#define WM8350_GPIO_DEBOUNCE 0x80
#define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
#define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
#define WM8350_GPIO_INT_MODE 0x83
#define WM8350_GPIO_CONTROL 0x85
#define WM8350_GPIO_CONFIGURATION_I_O 0x86
#define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
#define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
#define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
#define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
#define WM8350_GPIO_FUNCTION_SELECT_4 0x8F
/*
* GPIO Functions
*/
#define WM8350_GPIO0_GPIO_IN 0x0
#define WM8350_GPIO0_GPIO_OUT 0x0
#define WM8350_GPIO0_PWR_ON_IN 0x1
#define WM8350_GPIO0_PWR_ON_OUT 0x1
#define WM8350_GPIO0_LDO_EN_IN 0x2
#define WM8350_GPIO0_VRTC_OUT 0x2
#define WM8350_GPIO0_LPWR1_IN 0x3
#define WM8350_GPIO0_POR_B_OUT 0x3
#define WM8350_GPIO1_GPIO_IN 0x0
#define WM8350_GPIO1_GPIO_OUT 0x0
#define WM8350_GPIO1_PWR_ON_IN 0x1
#define WM8350_GPIO1_DO_CONF_OUT 0x1
#define WM8350_GPIO1_LDO_EN_IN 0x2
#define WM8350_GPIO1_RESET_OUT 0x2
#define WM8350_GPIO1_LPWR2_IN 0x3
#define WM8350_GPIO1_MEMRST_OUT 0x3
#define WM8350_GPIO2_GPIO_IN 0x0
#define WM8350_GPIO2_GPIO_OUT 0x0
#define WM8350_GPIO2_PWR_ON_IN 0x1
#define WM8350_GPIO2_PWR_ON_OUT 0x1
#define WM8350_GPIO2_WAKE_UP_IN 0x2
#define WM8350_GPIO2_VRTC_OUT 0x2
#define WM8350_GPIO2_32KHZ_IN 0x3
#define WM8350_GPIO2_32KHZ_OUT 0x3
#define WM8350_GPIO3_GPIO_IN 0x0
#define WM8350_GPIO3_GPIO_OUT 0x0
#define WM8350_GPIO3_PWR_ON_IN 0x1
#define WM8350_GPIO3_P_CLK_OUT 0x1
#define WM8350_GPIO3_LDO_EN_IN 0x2
#define WM8350_GPIO3_VRTC_OUT 0x2
#define WM8350_GPIO3_PWR_OFF_IN 0x3
#define WM8350_GPIO3_32KHZ_OUT 0x3
#define WM8350_GPIO4_GPIO_IN 0x0
#define WM8350_GPIO4_GPIO_OUT 0x0
#define WM8350_GPIO4_MR_IN 0x1
#define WM8350_GPIO4_MEM_RST_OUT 0x1
#define WM8350_GPIO4_FLASH_IN 0x2
#define WM8350_GPIO4_ADA_OUT 0x2
#define WM8350_GPIO4_HIBERNATE_IN 0x3
#define WM8350_GPIO4_FLASH_OUT 0x3
#define WM8350_GPIO4_MICDET_OUT 0x4
#define WM8350_GPIO4_MICSHT_OUT 0x5
#define WM8350_GPIO5_GPIO_IN 0x0
#define WM8350_GPIO5_GPIO_OUT 0x0
#define WM8350_GPIO5_LPWR1_IN 0x1
#define WM8350_GPIO5_P_CLK_OUT 0x1
#define WM8350_GPIO5_ADCLRCLK_IN 0x2
#define WM8350_GPIO5_ADCLRCLK_OUT 0x2
#define WM8350_GPIO5_HIBERNATE_IN 0x3
#define WM8350_GPIO5_32KHZ_OUT 0x3
#define WM8350_GPIO5_MICDET_OUT 0x4
#define WM8350_GPIO5_MICSHT_OUT 0x5
#define WM8350_GPIO5_ADA_OUT 0x6
#define WM8350_GPIO5_OPCLK_OUT 0x7
#define WM8350_GPIO6_GPIO_IN 0x0
#define WM8350_GPIO6_GPIO_OUT 0x0
#define WM8350_GPIO6_LPWR2_IN 0x1
#define WM8350_GPIO6_MEMRST_OUT 0x1
#define WM8350_GPIO6_FLASH_IN 0x2
#define WM8350_GPIO6_ADA_OUT 0x2
#define WM8350_GPIO6_HIBERNATE_IN 0x3
#define WM8350_GPIO6_RTC_OUT 0x3
#define WM8350_GPIO6_MICDET_OUT 0x4
#define WM8350_GPIO6_MICSHT_OUT 0x5
#define WM8350_GPIO6_ADCLRCLKB_OUT 0x6
#define WM8350_GPIO6_SDOUT_OUT 0x7
#define WM8350_GPIO7_GPIO_IN 0x0
#define WM8350_GPIO7_GPIO_OUT 0x0
#define WM8350_GPIO7_LPWR3_IN 0x1
#define WM8350_GPIO7_P_CLK_OUT 0x1
#define WM8350_GPIO7_MASK_IN 0x2
#define WM8350_GPIO7_VCC_FAULT_OUT 0x2
#define WM8350_GPIO7_HIBERNATE_IN 0x3
#define WM8350_GPIO7_BATT_FAULT_OUT 0x3
#define WM8350_GPIO7_MICDET_OUT 0x4
#define WM8350_GPIO7_MICSHT_OUT 0x5
#define WM8350_GPIO7_ADA_OUT 0x6
#define WM8350_GPIO7_CSB_IN 0x7
#define WM8350_GPIO8_GPIO_IN 0x0
#define WM8350_GPIO8_GPIO_OUT 0x0
#define WM8350_GPIO8_MR_IN 0x1
#define WM8350_GPIO8_VCC_FAULT_OUT 0x1
#define WM8350_GPIO8_ADCBCLK_IN 0x2
#define WM8350_GPIO8_ADCBCLK_OUT 0x2
#define WM8350_GPIO8_PWR_OFF_IN 0x3
#define WM8350_GPIO8_BATT_FAULT_OUT 0x3
#define WM8350_GPIO8_ALTSCL_IN 0xf
#define WM8350_GPIO9_GPIO_IN 0x0
#define WM8350_GPIO9_GPIO_OUT 0x0
#define WM8350_GPIO9_HEARTBEAT_IN 0x1
#define WM8350_GPIO9_VCC_FAULT_OUT 0x1
#define WM8350_GPIO9_MASK_IN 0x2
#define WM8350_GPIO9_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO9_PWR_OFF_IN 0x3
#define WM8350_GPIO9_BATT_FAULT_OUT 0x3
#define WM8350_GPIO9_ALTSDA_OUT 0xf
#define WM8350_GPIO10_GPIO_IN 0x0
#define WM8350_GPIO10_GPIO_OUT 0x0
#define WM8350_GPIO10_ISINKC_OUT 0x1
#define WM8350_GPIO10_PWR_OFF_IN 0x2
#define WM8350_GPIO10_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO10_CHD_IND_IN 0x3
#define WM8350_GPIO11_GPIO_IN 0x0
#define WM8350_GPIO11_GPIO_OUT 0x0
#define WM8350_GPIO11_ISINKD_OUT 0x1
#define WM8350_GPIO11_WAKEUP_IN 0x2
#define WM8350_GPIO11_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO11_CHD_IND_IN 0x3
#define WM8350_GPIO12_GPIO_IN 0x0
#define WM8350_GPIO12_GPIO_OUT 0x0
#define WM8350_GPIO12_ISINKE_OUT 0x1
#define WM8350_GPIO12_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO12_LINE_EN_OUT 0x3
#define WM8350_GPIO12_32KHZ_OUT 0x4
#define WM8350_GPIO_DIR_IN 0
#define WM8350_GPIO_DIR_OUT 1
#define WM8350_GPIO_ACTIVE_LOW 0
#define WM8350_GPIO_ACTIVE_HIGH 1
#define WM8350_GPIO_PULL_NONE 0
#define WM8350_GPIO_PULL_UP 1
#define WM8350_GPIO_PULL_DOWN 2
#define WM8350_GPIO_INVERT_OFF 0
#define WM8350_GPIO_INVERT_ON 1
#define WM8350_GPIO_DEBOUNCE_OFF 0
#define WM8350_GPIO_DEBOUNCE_ON 1
/*
* R128 (0x80) - GPIO Debounce
*/
#define WM8350_GP12_DB 0x1000
#define WM8350_GP11_DB 0x0800
#define WM8350_GP10_DB 0x0400
#define WM8350_GP9_DB 0x0200
#define WM8350_GP8_DB 0x0100
#define WM8350_GP7_DB 0x0080
#define WM8350_GP6_DB 0x0040
#define WM8350_GP5_DB 0x0020
#define WM8350_GP4_DB 0x0010
#define WM8350_GP3_DB 0x0008
#define WM8350_GP2_DB 0x0004
#define WM8350_GP1_DB 0x0002
#define WM8350_GP0_DB 0x0001
/*
* R129 (0x81) - GPIO Pin pull up Control
*/
#define WM8350_GP12_PU 0x1000
#define WM8350_GP11_PU 0x0800
#define WM8350_GP10_PU 0x0400
#define WM8350_GP9_PU 0x0200
#define WM8350_GP8_PU 0x0100
#define WM8350_GP7_PU 0x0080
#define WM8350_GP6_PU 0x0040
#define WM8350_GP5_PU 0x0020
#define WM8350_GP4_PU 0x0010
#define WM8350_GP3_PU 0x0008
#define WM8350_GP2_PU 0x0004
#define WM8350_GP1_PU 0x0002
#define WM8350_GP0_PU 0x0001
/*
* R130 (0x82) - GPIO Pull down Control
*/
#define WM8350_GP12_PD 0x1000
#define WM8350_GP11_PD 0x0800
#define WM8350_GP10_PD 0x0400
#define WM8350_GP9_PD 0x0200
#define WM8350_GP8_PD 0x0100
#define WM8350_GP7_PD 0x0080
#define WM8350_GP6_PD 0x0040
#define WM8350_GP5_PD 0x0020
#define WM8350_GP4_PD 0x0010
#define WM8350_GP3_PD 0x0008
#define WM8350_GP2_PD 0x0004
#define WM8350_GP1_PD 0x0002
#define WM8350_GP0_PD 0x0001
/*
* R131 (0x83) - GPIO Interrupt Mode
*/
#define WM8350_GP12_INTMODE 0x1000
#define WM8350_GP11_INTMODE 0x0800
#define WM8350_GP10_INTMODE 0x0400
#define WM8350_GP9_INTMODE 0x0200
#define WM8350_GP8_INTMODE 0x0100
#define WM8350_GP7_INTMODE 0x0080
#define WM8350_GP6_INTMODE 0x0040
#define WM8350_GP5_INTMODE 0x0020
#define WM8350_GP4_INTMODE 0x0010
#define WM8350_GP3_INTMODE 0x0008
#define WM8350_GP2_INTMODE 0x0004
#define WM8350_GP1_INTMODE 0x0002
#define WM8350_GP0_INTMODE 0x0001
/*
* R133 (0x85) - GPIO Control
*/
#define WM8350_GP_DBTIME_MASK 0x00C0
/*
* R134 (0x86) - GPIO Configuration (i/o)
*/
#define WM8350_GP12_DIR 0x1000
#define WM8350_GP11_DIR 0x0800
#define WM8350_GP10_DIR 0x0400
#define WM8350_GP9_DIR 0x0200
#define WM8350_GP8_DIR 0x0100
#define WM8350_GP7_DIR 0x0080
#define WM8350_GP6_DIR 0x0040
#define WM8350_GP5_DIR 0x0020
#define WM8350_GP4_DIR 0x0010
#define WM8350_GP3_DIR 0x0008
#define WM8350_GP2_DIR 0x0004
#define WM8350_GP1_DIR 0x0002
#define WM8350_GP0_DIR 0x0001
/*
* R135 (0x87) - GPIO Pin Polarity / Type
*/
#define WM8350_GP12_CFG 0x1000
#define WM8350_GP11_CFG 0x0800
#define WM8350_GP10_CFG 0x0400
#define WM8350_GP9_CFG 0x0200
#define WM8350_GP8_CFG 0x0100
#define WM8350_GP7_CFG 0x0080
#define WM8350_GP6_CFG 0x0040
#define WM8350_GP5_CFG 0x0020
#define WM8350_GP4_CFG 0x0010
#define WM8350_GP3_CFG 0x0008
#define WM8350_GP2_CFG 0x0004
#define WM8350_GP1_CFG 0x0002
#define WM8350_GP0_CFG 0x0001
/*
* R140 (0x8C) - GPIO Function Select 1
*/
#define WM8350_GP3_FN_MASK 0xF000
#define WM8350_GP2_FN_MASK 0x0F00
#define WM8350_GP1_FN_MASK 0x00F0
#define WM8350_GP0_FN_MASK 0x000F
/*
* R141 (0x8D) - GPIO Function Select 2
*/
#define WM8350_GP7_FN_MASK 0xF000
#define WM8350_GP6_FN_MASK 0x0F00
#define WM8350_GP5_FN_MASK 0x00F0
#define WM8350_GP4_FN_MASK 0x000F
/*
* R142 (0x8E) - GPIO Function Select 3
*/
#define WM8350_GP11_FN_MASK 0xF000
#define WM8350_GP10_FN_MASK 0x0F00
#define WM8350_GP9_FN_MASK 0x00F0
#define WM8350_GP8_FN_MASK 0x000F
/*
* R143 (0x8F) - GPIO Function Select 4
*/
#define WM8350_GP12_FN_MASK 0x000F
/*
* R230 (0xE6) - GPIO Pin Status
*/
#define WM8350_GP12_LVL 0x1000
#define WM8350_GP11_LVL 0x0800
#define WM8350_GP10_LVL 0x0400
#define WM8350_GP9_LVL 0x0200
#define WM8350_GP8_LVL 0x0100
#define WM8350_GP7_LVL 0x0080
#define WM8350_GP6_LVL 0x0040
#define WM8350_GP5_LVL 0x0020
#define WM8350_GP4_LVL 0x0010
#define WM8350_GP3_LVL 0x0008
#define WM8350_GP2_LVL 0x0004
#define WM8350_GP1_LVL 0x0002
#define WM8350_GP0_LVL 0x0001
struct wm8350;
int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func,
int pol, int pull, int invert, int debounce);
struct wm8350_gpio {
struct platform_device *pdev;
};
/*
* GPIO Interrupts
*/
#define WM8350_IRQ_GPIO(x) (50 + x)
#endif

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include/linux/mfd/wm8350/pmic.h Normal file
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/*
* pmic.h -- Power Managment Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_PMIC_H
#define __LINUX_MFD_WM8350_PMIC_H
/*
* Register values.
*/
#define WM8350_CURRENT_SINK_DRIVER_A 0xAC
#define WM8350_CSA_FLASH_CONTROL 0xAD
#define WM8350_CURRENT_SINK_DRIVER_B 0xAE
#define WM8350_CSB_FLASH_CONTROL 0xAF
#define WM8350_DCDC_LDO_REQUESTED 0xB0
#define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
#define WM8350_DCDC_SLEEP_OPTIONS 0xB2
#define WM8350_POWER_CHECK_COMPARATOR 0xB3
#define WM8350_DCDC1_CONTROL 0xB4
#define WM8350_DCDC1_TIMEOUTS 0xB5
#define WM8350_DCDC1_LOW_POWER 0xB6
#define WM8350_DCDC2_CONTROL 0xB7
#define WM8350_DCDC2_TIMEOUTS 0xB8
#define WM8350_DCDC3_CONTROL 0xBA
#define WM8350_DCDC3_TIMEOUTS 0xBB
#define WM8350_DCDC3_LOW_POWER 0xBC
#define WM8350_DCDC4_CONTROL 0xBD
#define WM8350_DCDC4_TIMEOUTS 0xBE
#define WM8350_DCDC4_LOW_POWER 0xBF
#define WM8350_DCDC5_CONTROL 0xC0
#define WM8350_DCDC5_TIMEOUTS 0xC1
#define WM8350_DCDC6_CONTROL 0xC3
#define WM8350_DCDC6_TIMEOUTS 0xC4
#define WM8350_DCDC6_LOW_POWER 0xC5
#define WM8350_LIMIT_SWITCH_CONTROL 0xC7
#define WM8350_LDO1_CONTROL 0xC8
#define WM8350_LDO1_TIMEOUTS 0xC9
#define WM8350_LDO1_LOW_POWER 0xCA
#define WM8350_LDO2_CONTROL 0xCB
#define WM8350_LDO2_TIMEOUTS 0xCC
#define WM8350_LDO2_LOW_POWER 0xCD
#define WM8350_LDO3_CONTROL 0xCE
#define WM8350_LDO3_TIMEOUTS 0xCF
#define WM8350_LDO3_LOW_POWER 0xD0
#define WM8350_LDO4_CONTROL 0xD1
#define WM8350_LDO4_TIMEOUTS 0xD2
#define WM8350_LDO4_LOW_POWER 0xD3
#define WM8350_VCC_FAULT_MASKS 0xD7
#define WM8350_MAIN_BANDGAP_CONTROL 0xD8
#define WM8350_OSC_CONTROL 0xD9
#define WM8350_RTC_TICK_CONTROL 0xDA
#define WM8350_SECURITY 0xDB
#define WM8350_RAM_BIST_1 0xDC
#define WM8350_DCDC_LDO_STATUS 0xE1
#define WM8350_GPIO_PIN_STATUS 0xE6
#define WM8350_DCDC1_FORCE_PWM 0xF8
#define WM8350_DCDC3_FORCE_PWM 0xFA
#define WM8350_DCDC4_FORCE_PWM 0xFB
#define WM8350_DCDC6_FORCE_PWM 0xFD
/*
* R172 (0xAC) - Current Sink Driver A
*/
#define WM8350_CS1_HIB_MODE 0x1000
#define WM8350_CS1_HIB_MODE_MASK 0x1000
#define WM8350_CS1_HIB_MODE_SHIFT 12
#define WM8350_CS1_ISEL_MASK 0x003F
#define WM8350_CS1_ISEL_SHIFT 0
/* Bit values for R172 (0xAC) */
#define WM8350_CS1_HIB_MODE_DISABLE 0
#define WM8350_CS1_HIB_MODE_LEAVE 1
#define WM8350_CS1_ISEL_220M 0x3F
/*
* R173 (0xAD) - CSA Flash control
*/
#define WM8350_CS1_FLASH_MODE 0x8000
#define WM8350_CS1_TRIGSRC 0x4000
#define WM8350_CS1_DRIVE 0x2000
#define WM8350_CS1_FLASH_DUR_MASK 0x0300
#define WM8350_CS1_OFF_RAMP_MASK 0x0030
#define WM8350_CS1_ON_RAMP_MASK 0x0003
/*
* R174 (0xAE) - Current Sink Driver B
*/
#define WM8350_CS2_HIB_MODE 0x1000
#define WM8350_CS2_ISEL_MASK 0x003F
/*
* R175 (0xAF) - CSB Flash control
*/
#define WM8350_CS2_FLASH_MODE 0x8000
#define WM8350_CS2_TRIGSRC 0x4000
#define WM8350_CS2_DRIVE 0x2000
#define WM8350_CS2_FLASH_DUR_MASK 0x0300
#define WM8350_CS2_OFF_RAMP_MASK 0x0030
#define WM8350_CS2_ON_RAMP_MASK 0x0003
/*
* R176 (0xB0) - DCDC/LDO requested
*/
#define WM8350_LS_ENA 0x8000
#define WM8350_LDO4_ENA 0x0800
#define WM8350_LDO3_ENA 0x0400
#define WM8350_LDO2_ENA 0x0200
#define WM8350_LDO1_ENA 0x0100
#define WM8350_DC6_ENA 0x0020
#define WM8350_DC5_ENA 0x0010
#define WM8350_DC4_ENA 0x0008
#define WM8350_DC3_ENA 0x0004
#define WM8350_DC2_ENA 0x0002
#define WM8350_DC1_ENA 0x0001
/*
* R177 (0xB1) - DCDC Active options
*/
#define WM8350_PUTO_MASK 0x3000
#define WM8350_PWRUP_DELAY_MASK 0x0300
#define WM8350_DC6_ACTIVE 0x0020
#define WM8350_DC4_ACTIVE 0x0008
#define WM8350_DC3_ACTIVE 0x0004
#define WM8350_DC1_ACTIVE 0x0001
/*
* R178 (0xB2) - DCDC Sleep options
*/
#define WM8350_DC6_SLEEP 0x0020
#define WM8350_DC4_SLEEP 0x0008
#define WM8350_DC3_SLEEP 0x0004
#define WM8350_DC1_SLEEP 0x0001
/*
* R179 (0xB3) - Power-check comparator
*/
#define WM8350_PCCMP_ERRACT 0x4000
#define WM8350_PCCMP_RAIL 0x0100
#define WM8350_PCCMP_OFF_THR_MASK 0x0070
#define WM8350_PCCMP_ON_THR_MASK 0x0007
/*
* R180 (0xB4) - DCDC1 Control
*/
#define WM8350_DC1_OPFLT 0x0400
#define WM8350_DC1_VSEL_MASK 0x007F
#define WM8350_DC1_VSEL_SHIFT 0
/*
* R181 (0xB5) - DCDC1 Timeouts
*/
#define WM8350_DC1_ERRACT_MASK 0xC000
#define WM8350_DC1_ERRACT_SHIFT 14
#define WM8350_DC1_ENSLOT_MASK 0x3C00
#define WM8350_DC1_ENSLOT_SHIFT 10
#define WM8350_DC1_SDSLOT_MASK 0x03C0
#define WM8350_DC1_UVTO_MASK 0x0030
#define WM8350_DC1_SDSLOT_SHIFT 6
/* Bit values for R181 (0xB5) */
#define WM8350_DC1_ERRACT_NONE 0
#define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2
/*
* R182 (0xB6) - DCDC1 Low Power
*/
#define WM8350_DC1_HIB_MODE_MASK 0x7000
#define WM8350_DC1_HIB_TRIG_MASK 0x0300
#define WM8350_DC1_VIMG_MASK 0x007F
/*
* R183 (0xB7) - DCDC2 Control
*/
#define WM8350_DC2_MODE 0x4000
#define WM8350_DC2_MODE_MASK 0x4000
#define WM8350_DC2_MODE_SHIFT 14
#define WM8350_DC2_HIB_MODE 0x1000
#define WM8350_DC2_HIB_MODE_MASK 0x1000
#define WM8350_DC2_HIB_MODE_SHIFT 12
#define WM8350_DC2_HIB_TRIG_MASK 0x0300
#define WM8350_DC2_HIB_TRIG_SHIFT 8
#define WM8350_DC2_ILIM 0x0040
#define WM8350_DC2_ILIM_MASK 0x0040
#define WM8350_DC2_ILIM_SHIFT 6
#define WM8350_DC2_RMP_MASK 0x0018
#define WM8350_DC2_RMP_SHIFT 3
#define WM8350_DC2_FBSRC_MASK 0x0003
#define WM8350_DC2_FBSRC_SHIFT 0
/* Bit values for R183 (0xB7) */
#define WM8350_DC2_MODE_BOOST 0
#define WM8350_DC2_MODE_SWITCH 1
#define WM8350_DC2_HIB_MODE_ACTIVE 1
#define WM8350_DC2_HIB_MODE_DISABLE 0
#define WM8350_DC2_HIB_TRIG_NONE 0
#define WM8350_DC2_HIB_TRIG_LPWR1 1
#define WM8350_DC2_HIB_TRIG_LPWR2 2
#define WM8350_DC2_HIB_TRIG_LPWR3 3
#define WM8350_DC2_ILIM_HIGH 0
#define WM8350_DC2_ILIM_LOW 1
#define WM8350_DC2_RMP_30V 0
#define WM8350_DC2_RMP_20V 1
#define WM8350_DC2_RMP_10V 2
#define WM8350_DC2_RMP_5V 3
#define WM8350_DC2_FBSRC_FB2 0
#define WM8350_DC2_FBSRC_ISINKA 1
#define WM8350_DC2_FBSRC_ISINKB 2
#define WM8350_DC2_FBSRC_USB 3
/*
* R184 (0xB8) - DCDC2 Timeouts
*/
#define WM8350_DC2_ERRACT_MASK 0xC000
#define WM8350_DC2_ERRACT_SHIFT 14
#define WM8350_DC2_ENSLOT_MASK 0x3C00
#define WM8350_DC2_ENSLOT_SHIFT 10
#define WM8350_DC2_SDSLOT_MASK 0x03C0
#define WM8350_DC2_UVTO_MASK 0x0030
/* Bit values for R184 (0xB8) */
#define WM8350_DC2_ERRACT_NONE 0
#define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2
/*
* R186 (0xBA) - DCDC3 Control
*/
#define WM8350_DC3_OPFLT 0x0400
#define WM8350_DC3_VSEL_MASK 0x007F
#define WM8350_DC3_VSEL_SHIFT 0
/*
* R187 (0xBB) - DCDC3 Timeouts
*/
#define WM8350_DC3_ERRACT_MASK 0xC000
#define WM8350_DC3_ERRACT_SHIFT 14
#define WM8350_DC3_ENSLOT_MASK 0x3C00
#define WM8350_DC3_ENSLOT_SHIFT 10
#define WM8350_DC3_SDSLOT_MASK 0x03C0
#define WM8350_DC3_UVTO_MASK 0x0030
#define WM8350_DC3_SDSLOT_SHIFT 6
/* Bit values for R187 (0xBB) */
#define WM8350_DC3_ERRACT_NONE 0
#define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2
/*
* R188 (0xBC) - DCDC3 Low Power
*/
#define WM8350_DC3_HIB_MODE_MASK 0x7000
#define WM8350_DC3_HIB_TRIG_MASK 0x0300
#define WM8350_DC3_VIMG_MASK 0x007F
/*
* R189 (0xBD) - DCDC4 Control
*/
#define WM8350_DC4_OPFLT 0x0400
#define WM8350_DC4_VSEL_MASK 0x007F
#define WM8350_DC4_VSEL_SHIFT 0
/*
* R190 (0xBE) - DCDC4 Timeouts
*/
#define WM8350_DC4_ERRACT_MASK 0xC000
#define WM8350_DC4_ERRACT_SHIFT 14
#define WM8350_DC4_ENSLOT_MASK 0x3C00
#define WM8350_DC4_ENSLOT_SHIFT 10
#define WM8350_DC4_SDSLOT_MASK 0x03C0
#define WM8350_DC4_UVTO_MASK 0x0030
#define WM8350_DC4_SDSLOT_SHIFT 6
/* Bit values for R190 (0xBE) */
#define WM8350_DC4_ERRACT_NONE 0
#define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2
/*
* R191 (0xBF) - DCDC4 Low Power
*/
#define WM8350_DC4_HIB_MODE_MASK 0x7000
#define WM8350_DC4_HIB_TRIG_MASK 0x0300
#define WM8350_DC4_VIMG_MASK 0x007F
/*
* R192 (0xC0) - DCDC5 Control
*/
#define WM8350_DC5_MODE 0x4000
#define WM8350_DC5_MODE_MASK 0x4000
#define WM8350_DC5_MODE_SHIFT 14
#define WM8350_DC5_HIB_MODE 0x1000
#define WM8350_DC5_HIB_MODE_MASK 0x1000
#define WM8350_DC5_HIB_MODE_SHIFT 12
#define WM8350_DC5_HIB_TRIG_MASK 0x0300
#define WM8350_DC5_HIB_TRIG_SHIFT 8
#define WM8350_DC5_ILIM 0x0040
#define WM8350_DC5_ILIM_MASK 0x0040
#define WM8350_DC5_ILIM_SHIFT 6
#define WM8350_DC5_RMP_MASK 0x0018
#define WM8350_DC5_RMP_SHIFT 3
#define WM8350_DC5_FBSRC_MASK 0x0003
#define WM8350_DC5_FBSRC_SHIFT 0
/* Bit values for R192 (0xC0) */
#define WM8350_DC5_MODE_BOOST 0
#define WM8350_DC5_MODE_SWITCH 1
#define WM8350_DC5_HIB_MODE_ACTIVE 1
#define WM8350_DC5_HIB_MODE_DISABLE 0
#define WM8350_DC5_HIB_TRIG_NONE 0
#define WM8350_DC5_HIB_TRIG_LPWR1 1
#define WM8350_DC5_HIB_TRIG_LPWR2 2
#define WM8350_DC5_HIB_TRIG_LPWR3 3
#define WM8350_DC5_ILIM_HIGH 0
#define WM8350_DC5_ILIM_LOW 1
#define WM8350_DC5_RMP_30V 0
#define WM8350_DC5_RMP_20V 1
#define WM8350_DC5_RMP_10V 2
#define WM8350_DC5_RMP_5V 3
#define WM8350_DC5_FBSRC_FB2 0
#define WM8350_DC5_FBSRC_ISINKA 1
#define WM8350_DC5_FBSRC_ISINKB 2
#define WM8350_DC5_FBSRC_USB 3
/*
* R193 (0xC1) - DCDC5 Timeouts
*/
#define WM8350_DC5_ERRACT_MASK 0xC000
#define WM8350_DC5_ERRACT_SHIFT 14
#define WM8350_DC5_ENSLOT_MASK 0x3C00
#define WM8350_DC5_ENSLOT_SHIFT 10
#define WM8350_DC5_SDSLOT_MASK 0x03C0
#define WM8350_DC5_UVTO_MASK 0x0030
#define WM8350_DC5_SDSLOT_SHIFT 6
/* Bit values for R193 (0xC1) */
#define WM8350_DC5_ERRACT_NONE 0
#define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2
/*
* R195 (0xC3) - DCDC6 Control
*/
#define WM8350_DC6_OPFLT 0x0400
#define WM8350_DC6_VSEL_MASK 0x007F
#define WM8350_DC6_VSEL_SHIFT 0
/*
* R196 (0xC4) - DCDC6 Timeouts
*/
#define WM8350_DC6_ERRACT_MASK 0xC000
#define WM8350_DC6_ERRACT_SHIFT 14
#define WM8350_DC6_ENSLOT_MASK 0x3C00
#define WM8350_DC6_ENSLOT_SHIFT 10
#define WM8350_DC6_SDSLOT_MASK 0x03C0
#define WM8350_DC6_UVTO_MASK 0x0030
#define WM8350_DC6_SDSLOT_SHIFT 6
/* Bit values for R196 (0xC4) */
#define WM8350_DC6_ERRACT_NONE 0
#define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2
/*
* R197 (0xC5) - DCDC6 Low Power
*/
#define WM8350_DC6_HIB_MODE_MASK 0x7000
#define WM8350_DC6_HIB_TRIG_MASK 0x0300
#define WM8350_DC6_VIMG_MASK 0x007F
/*
* R199 (0xC7) - Limit Switch Control
*/
#define WM8350_LS_ERRACT_MASK 0xC000
#define WM8350_LS_ERRACT_SHIFT 14
#define WM8350_LS_ENSLOT_MASK 0x3C00
#define WM8350_LS_ENSLOT_SHIFT 10
#define WM8350_LS_SDSLOT_MASK 0x03C0
#define WM8350_LS_SDSLOT_SHIFT 6
#define WM8350_LS_HIB_MODE 0x0010
#define WM8350_LS_HIB_MODE_MASK 0x0010
#define WM8350_LS_HIB_MODE_SHIFT 4
#define WM8350_LS_HIB_PROT 0x0002
#define WM8350_LS_HIB_PROT_MASK 0x0002
#define WM8350_LS_HIB_PROT_SHIFT 1
#define WM8350_LS_PROT 0x0001
#define WM8350_LS_PROT_MASK 0x0001
#define WM8350_LS_PROT_SHIFT 0
/* Bit values for R199 (0xC7) */
#define WM8350_LS_ERRACT_NONE 0
#define WM8350_LS_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LS_ERRACT_SHUTDOWN_SYS 2
/*
* R200 (0xC8) - LDO1 Control
*/
#define WM8350_LDO1_SWI 0x4000
#define WM8350_LDO1_OPFLT 0x0400
#define WM8350_LDO1_VSEL_MASK 0x001F
#define WM8350_LDO1_VSEL_SHIFT 0
/*
* R201 (0xC9) - LDO1 Timeouts
*/
#define WM8350_LDO1_ERRACT_MASK 0xC000
#define WM8350_LDO1_ERRACT_SHIFT 14
#define WM8350_LDO1_ENSLOT_MASK 0x3C00
#define WM8350_LDO1_ENSLOT_SHIFT 10
#define WM8350_LDO1_SDSLOT_MASK 0x03C0
#define WM8350_LDO1_UVTO_MASK 0x0030
#define WM8350_LDO1_SDSLOT_SHIFT 6
/* Bit values for R201 (0xC9) */
#define WM8350_LDO1_ERRACT_NONE 0
#define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2
/*
* R202 (0xCA) - LDO1 Low Power
*/
#define WM8350_LDO1_HIB_MODE_MASK 0x3000
#define WM8350_LDO1_HIB_TRIG_MASK 0x0300
#define WM8350_LDO1_VIMG_MASK 0x001F
#define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12)
/*
* R203 (0xCB) - LDO2 Control
*/
#define WM8350_LDO2_SWI 0x4000
#define WM8350_LDO2_OPFLT 0x0400
#define WM8350_LDO2_VSEL_MASK 0x001F
#define WM8350_LDO2_VSEL_SHIFT 0
/*
* R204 (0xCC) - LDO2 Timeouts
*/
#define WM8350_LDO2_ERRACT_MASK 0xC000
#define WM8350_LDO2_ERRACT_SHIFT 14
#define WM8350_LDO2_ENSLOT_MASK 0x3C00
#define WM8350_LDO2_ENSLOT_SHIFT 10
#define WM8350_LDO2_SDSLOT_MASK 0x03C0
#define WM8350_LDO2_SDSLOT_SHIFT 6
/* Bit values for R204 (0xCC) */
#define WM8350_LDO2_ERRACT_NONE 0
#define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2
/*
* R205 (0xCD) - LDO2 Low Power
*/
#define WM8350_LDO2_HIB_MODE_MASK 0x3000
#define WM8350_LDO2_HIB_TRIG_MASK 0x0300
#define WM8350_LDO2_VIMG_MASK 0x001F
/*
* R206 (0xCE) - LDO3 Control
*/
#define WM8350_LDO3_SWI 0x4000
#define WM8350_LDO3_OPFLT 0x0400
#define WM8350_LDO3_VSEL_MASK 0x001F
#define WM8350_LDO3_VSEL_SHIFT 0
/*
* R207 (0xCF) - LDO3 Timeouts
*/
#define WM8350_LDO3_ERRACT_MASK 0xC000
#define WM8350_LDO3_ERRACT_SHIFT 14
#define WM8350_LDO3_ENSLOT_MASK 0x3C00
#define WM8350_LDO3_ENSLOT_SHIFT 10
#define WM8350_LDO3_SDSLOT_MASK 0x03C0
#define WM8350_LDO3_UVTO_MASK 0x0030
#define WM8350_LDO3_SDSLOT_SHIFT 6
/* Bit values for R207 (0xCF) */
#define WM8350_LDO3_ERRACT_NONE 0
#define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2
/*
* R208 (0xD0) - LDO3 Low Power
*/
#define WM8350_LDO3_HIB_MODE_MASK 0x3000
#define WM8350_LDO3_HIB_TRIG_MASK 0x0300
#define WM8350_LDO3_VIMG_MASK 0x001F
/*
* R209 (0xD1) - LDO4 Control
*/
#define WM8350_LDO4_SWI 0x4000
#define WM8350_LDO4_OPFLT 0x0400
#define WM8350_LDO4_VSEL_MASK 0x001F
#define WM8350_LDO4_VSEL_SHIFT 0
/*
* R210 (0xD2) - LDO4 Timeouts
*/
#define WM8350_LDO4_ERRACT_MASK 0xC000
#define WM8350_LDO4_ERRACT_SHIFT 14
#define WM8350_LDO4_ENSLOT_MASK 0x3C00
#define WM8350_LDO4_ENSLOT_SHIFT 10
#define WM8350_LDO4_SDSLOT_MASK 0x03C0
#define WM8350_LDO4_UVTO_MASK 0x0030
#define WM8350_LDO4_SDSLOT_SHIFT 6
/* Bit values for R210 (0xD2) */
#define WM8350_LDO4_ERRACT_NONE 0
#define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2
/*
* R211 (0xD3) - LDO4 Low Power
*/
#define WM8350_LDO4_HIB_MODE_MASK 0x3000
#define WM8350_LDO4_HIB_TRIG_MASK 0x0300
#define WM8350_LDO4_VIMG_MASK 0x001F
/*
* R215 (0xD7) - VCC_FAULT Masks
*/
#define WM8350_LS_FAULT 0x8000
#define WM8350_LDO4_FAULT 0x0800
#define WM8350_LDO3_FAULT 0x0400
#define WM8350_LDO2_FAULT 0x0200
#define WM8350_LDO1_FAULT 0x0100
#define WM8350_DC6_FAULT 0x0020
#define WM8350_DC5_FAULT 0x0010
#define WM8350_DC4_FAULT 0x0008
#define WM8350_DC3_FAULT 0x0004
#define WM8350_DC2_FAULT 0x0002
#define WM8350_DC1_FAULT 0x0001
/*
* R216 (0xD8) - Main Bandgap Control
*/
#define WM8350_MBG_LOAD_FUSES 0x8000
#define WM8350_MBG_FUSE_WPREP 0x4000
#define WM8350_MBG_FUSE_WRITE 0x2000
#define WM8350_MBG_FUSE_TRIM_MASK 0x1F00
#define WM8350_MBG_TRIM_SRC 0x0020
#define WM8350_MBG_USER_TRIM_MASK 0x001F
/*
* R217 (0xD9) - OSC Control
*/
#define WM8350_OSC_LOAD_FUSES 0x8000
#define WM8350_OSC_FUSE_WPREP 0x4000
#define WM8350_OSC_FUSE_WRITE 0x2000
#define WM8350_OSC_FUSE_TRIM_MASK 0x0F00
#define WM8350_OSC_TRIM_SRC 0x0020
#define WM8350_OSC_USER_TRIM_MASK 0x000F
/*
* R248 (0xF8) - DCDC1 Force PWM
*/
#define WM8350_DCDC1_FORCE_PWM_ENA 0x0010
/*
* R250 (0xFA) - DCDC3 Force PWM
*/
#define WM8350_DCDC3_FORCE_PWM_ENA 0x0010
/*
* R251 (0xFB) - DCDC4 Force PWM
*/
#define WM8350_DCDC4_FORCE_PWM_ENA 0x0010
/*
* R253 (0xFD) - DCDC1 Force PWM
*/
#define WM8350_DCDC6_FORCE_PWM_ENA 0x0010
/*
* DCDC's
*/
#define WM8350_DCDC_1 0
#define WM8350_DCDC_2 1
#define WM8350_DCDC_3 2
#define WM8350_DCDC_4 3
#define WM8350_DCDC_5 4
#define WM8350_DCDC_6 5
/* DCDC modes */
#define WM8350_DCDC_ACTIVE_STANDBY 0
#define WM8350_DCDC_ACTIVE_PULSE 1
#define WM8350_DCDC_SLEEP_NORMAL 0
#define WM8350_DCDC_SLEEP_LOW 1
/* DCDC Low power (Hibernate) mode */
#define WM8350_DCDC_HIB_MODE_CUR (0 << 12)
#define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12)
#define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12)
#define WM8350_DCDC_HIB_MODE_LDO (4 << 12)
#define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12)
#define WM8350_DCDC_HIB_MODE_DIS (7 << 12)
#define WM8350_DCDC_HIB_MODE_MASK (7 << 12)
/* DCDC Low Power (Hibernate) signal */
#define WM8350_DCDC_HIB_SIG_REG (0 << 8)
#define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8)
#define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8)
#define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8)
/* LDO Low power (Hibernate) mode */
#define WM8350_LDO_HIB_MODE_IMAGE (0 << 0)
#define WM8350_LDO_HIB_MODE_DIS (1 << 0)
/* LDO Low Power (Hibernate) signal */
#define WM8350_LDO_HIB_SIG_REG (0 << 8)
#define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8)
#define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8)
#define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8)
/*
* LDOs
*/
#define WM8350_LDO_1 6
#define WM8350_LDO_2 7
#define WM8350_LDO_3 8
#define WM8350_LDO_4 9
/*
* ISINKs
*/
#define WM8350_ISINK_A 10
#define WM8350_ISINK_B 11
#define WM8350_ISINK_MODE_BOOST 0
#define WM8350_ISINK_MODE_SWITCH 1
#define WM8350_ISINK_ILIM_NORMAL 0
#define WM8350_ISINK_ILIM_LOW 1
#define WM8350_ISINK_FLASH_DISABLE 0
#define WM8350_ISINK_FLASH_ENABLE 1
#define WM8350_ISINK_FLASH_TRIG_BIT 0
#define WM8350_ISINK_FLASH_TRIG_GPIO 1
#define WM8350_ISINK_FLASH_MODE_EN (1 << 13)
#define WM8350_ISINK_FLASH_MODE_DIS (0 << 13)
#define WM8350_ISINK_FLASH_DUR_32MS (0 << 8)
#define WM8350_ISINK_FLASH_DUR_64MS (1 << 8)
#define WM8350_ISINK_FLASH_DUR_96MS (2 << 8)
#define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8)
#define WM8350_ISINK_FLASH_ON_INSTANT (0 << 4)
#define WM8350_ISINK_FLASH_ON_0_25S (1 << 4)
#define WM8350_ISINK_FLASH_ON_0_50S (2 << 4)
#define WM8350_ISINK_FLASH_ON_1_00S (3 << 4)
#define WM8350_ISINK_FLASH_ON_1_95S (1 << 4)
#define WM8350_ISINK_FLASH_ON_3_91S (2 << 4)
#define WM8350_ISINK_FLASH_ON_7_80S (3 << 4)
#define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 0)
#define WM8350_ISINK_FLASH_OFF_0_25S (1 << 0)
#define WM8350_ISINK_FLASH_OFF_0_50S (2 << 0)
#define WM8350_ISINK_FLASH_OFF_1_00S (3 << 0)
#define WM8350_ISINK_FLASH_OFF_1_95S (1 << 0)
#define WM8350_ISINK_FLASH_OFF_3_91S (2 << 0)
#define WM8350_ISINK_FLASH_OFF_7_80S (3 << 0)
/*
* Regulator Interrupts.
*/
#define WM8350_IRQ_CS1 13
#define WM8350_IRQ_CS2 14
#define WM8350_IRQ_UV_LDO4 25
#define WM8350_IRQ_UV_LDO3 26
#define WM8350_IRQ_UV_LDO2 27
#define WM8350_IRQ_UV_LDO1 28
#define WM8350_IRQ_UV_DC6 29
#define WM8350_IRQ_UV_DC5 30
#define WM8350_IRQ_UV_DC4 31
#define WM8350_IRQ_UV_DC3 32
#define WM8350_IRQ_UV_DC2 33
#define WM8350_IRQ_UV_DC1 34
#define WM8350_IRQ_OC_LS 35
#define NUM_WM8350_REGULATORS 12
struct wm8350;
struct platform_device;
struct regulator_init_data;
struct wm8350_pmic {
/* ISINK to DCDC mapping */
int isink_A_dcdc;
int isink_B_dcdc;
/* hibernate configs */
u16 dcdc1_hib_mode;
u16 dcdc3_hib_mode;
u16 dcdc4_hib_mode;
u16 dcdc6_hib_mode;
/* regulator devices */
struct platform_device *pdev[NUM_WM8350_REGULATORS];
};
int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
struct regulator_init_data *initdata);
/*
* Additional DCDC control not supported via regulator API
*/
int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
u16 stop, u16 fault);
int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
u16 ilim, u16 ramp, u16 feedback);
/*
* Additional LDO control not supported via regulator API
*/
int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
/*
* Additional ISINK control not supported via regulator API
*/
int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
u16 trigger, u16 duration, u16 on_ramp,
u16 off_ramp, u16 drive);
#endif

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/*
* rtc.h -- RTC driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_WM8350_RTC_H
#define __LINUX_MFD_WM8350_RTC_H
#include <linux/platform_device.h>
/*
* Register values.
*/
#define WM8350_RTC_SECONDS_MINUTES 0x10
#define WM8350_RTC_HOURS_DAY 0x11
#define WM8350_RTC_DATE_MONTH 0x12
#define WM8350_RTC_YEAR 0x13
#define WM8350_ALARM_SECONDS_MINUTES 0x14
#define WM8350_ALARM_HOURS_DAY 0x15
#define WM8350_ALARM_DATE_MONTH 0x16
#define WM8350_RTC_TIME_CONTROL 0x17
/*
* R16 (0x10) - RTC Seconds/Minutes
*/
#define WM8350_RTC_MINS_MASK 0x7F00
#define WM8350_RTC_MINS_SHIFT 8
#define WM8350_RTC_SECS_MASK 0x007F
#define WM8350_RTC_SECS_SHIFT 0
/*
* R17 (0x11) - RTC Hours/Day
*/
#define WM8350_RTC_DAY_MASK 0x0700
#define WM8350_RTC_DAY_SHIFT 8
#define WM8350_RTC_HPM_MASK 0x0020
#define WM8350_RTC_HPM_SHIFT 5
#define WM8350_RTC_HRS_MASK 0x001F
#define WM8350_RTC_HRS_SHIFT 0
/* Bit values for R21 (0x15) */
#define WM8350_RTC_DAY_SUN 1
#define WM8350_RTC_DAY_MON 2
#define WM8350_RTC_DAY_TUE 3
#define WM8350_RTC_DAY_WED 4
#define WM8350_RTC_DAY_THU 5
#define WM8350_RTC_DAY_FRI 6
#define WM8350_RTC_DAY_SAT 7
#define WM8350_RTC_HPM_AM 0
#define WM8350_RTC_HPM_PM 1
/*
* R18 (0x12) - RTC Date/Month
*/
#define WM8350_RTC_MTH_MASK 0x1F00
#define WM8350_RTC_MTH_SHIFT 8
#define WM8350_RTC_DATE_MASK 0x003F
#define WM8350_RTC_DATE_SHIFT 0
/* Bit values for R22 (0x16) */
#define WM8350_RTC_MTH_JAN 1
#define WM8350_RTC_MTH_FEB 2
#define WM8350_RTC_MTH_MAR 3
#define WM8350_RTC_MTH_APR 4
#define WM8350_RTC_MTH_MAY 5
#define WM8350_RTC_MTH_JUN 6
#define WM8350_RTC_MTH_JUL 7
#define WM8350_RTC_MTH_AUG 8
#define WM8350_RTC_MTH_SEP 9
#define WM8350_RTC_MTH_OCT 10
#define WM8350_RTC_MTH_NOV 11
#define WM8350_RTC_MTH_DEC 12
#define WM8350_RTC_MTH_JAN_BCD 0x01
#define WM8350_RTC_MTH_FEB_BCD 0x02
#define WM8350_RTC_MTH_MAR_BCD 0x03
#define WM8350_RTC_MTH_APR_BCD 0x04
#define WM8350_RTC_MTH_MAY_BCD 0x05
#define WM8350_RTC_MTH_JUN_BCD 0x06
#define WM8350_RTC_MTH_JUL_BCD 0x07
#define WM8350_RTC_MTH_AUG_BCD 0x08
#define WM8350_RTC_MTH_SEP_BCD 0x09
#define WM8350_RTC_MTH_OCT_BCD 0x10
#define WM8350_RTC_MTH_NOV_BCD 0x11
#define WM8350_RTC_MTH_DEC_BCD 0x12
/*
* R19 (0x13) - RTC Year
*/
#define WM8350_RTC_YHUNDREDS_MASK 0x3F00
#define WM8350_RTC_YHUNDREDS_SHIFT 8
#define WM8350_RTC_YUNITS_MASK 0x00FF
#define WM8350_RTC_YUNITS_SHIFT 0
/*
* R20 (0x14) - Alarm Seconds/Minutes
*/
#define WM8350_RTC_ALMMINS_MASK 0x7F00
#define WM8350_RTC_ALMMINS_SHIFT 8
#define WM8350_RTC_ALMSECS_MASK 0x007F
#define WM8350_RTC_ALMSECS_SHIFT 0
/* Bit values for R20 (0x14) */
#define WM8350_RTC_ALMMINS_DONT_CARE -1
#define WM8350_RTC_ALMSECS_DONT_CARE -1
/*
* R21 (0x15) - Alarm Hours/Day
*/
#define WM8350_RTC_ALMDAY_MASK 0x0F00
#define WM8350_RTC_ALMDAY_SHIFT 8
#define WM8350_RTC_ALMHPM_MASK 0x0020
#define WM8350_RTC_ALMHPM_SHIFT 5
#define WM8350_RTC_ALMHRS_MASK 0x001F
#define WM8350_RTC_ALMHRS_SHIFT 0
/* Bit values for R21 (0x15) */
#define WM8350_RTC_ALMDAY_DONT_CARE -1
#define WM8350_RTC_ALMDAY_SUN 1
#define WM8350_RTC_ALMDAY_MON 2
#define WM8350_RTC_ALMDAY_TUE 3
#define WM8350_RTC_ALMDAY_WED 4
#define WM8350_RTC_ALMDAY_THU 5
#define WM8350_RTC_ALMDAY_FRI 6
#define WM8350_RTC_ALMDAY_SAT 7
#define WM8350_RTC_ALMHPM_AM 0
#define WM8350_RTC_ALMHPM_PM 1
#define WM8350_RTC_ALMHRS_DONT_CARE -1
/*
* R22 (0x16) - Alarm Date/Month
*/
#define WM8350_RTC_ALMMTH_MASK 0x1F00
#define WM8350_RTC_ALMMTH_SHIFT 8
#define WM8350_RTC_ALMDATE_MASK 0x003F
#define WM8350_RTC_ALMDATE_SHIFT 0
/* Bit values for R22 (0x16) */
#define WM8350_RTC_ALMDATE_DONT_CARE -1
#define WM8350_RTC_ALMMTH_DONT_CARE -1
#define WM8350_RTC_ALMMTH_JAN 1
#define WM8350_RTC_ALMMTH_FEB 2
#define WM8350_RTC_ALMMTH_MAR 3
#define WM8350_RTC_ALMMTH_APR 4
#define WM8350_RTC_ALMMTH_MAY 5
#define WM8350_RTC_ALMMTH_JUN 6
#define WM8350_RTC_ALMMTH_JUL 7
#define WM8350_RTC_ALMMTH_AUG 8
#define WM8350_RTC_ALMMTH_SEP 9
#define WM8350_RTC_ALMMTH_OCT 10
#define WM8350_RTC_ALMMTH_NOV 11
#define WM8350_RTC_ALMMTH_DEC 12
#define WM8350_RTC_ALMMTH_JAN_BCD 0x01
#define WM8350_RTC_ALMMTH_FEB_BCD 0x02
#define WM8350_RTC_ALMMTH_MAR_BCD 0x03
#define WM8350_RTC_ALMMTH_APR_BCD 0x04
#define WM8350_RTC_ALMMTH_MAY_BCD 0x05
#define WM8350_RTC_ALMMTH_JUN_BCD 0x06
#define WM8350_RTC_ALMMTH_JUL_BCD 0x07
#define WM8350_RTC_ALMMTH_AUG_BCD 0x08
#define WM8350_RTC_ALMMTH_SEP_BCD 0x09
#define WM8350_RTC_ALMMTH_OCT_BCD 0x10
#define WM8350_RTC_ALMMTH_NOV_BCD 0x11
#define WM8350_RTC_ALMMTH_DEC_BCD 0x12
/*
* R23 (0x17) - RTC Time Control
*/
#define WM8350_RTC_BCD 0x8000
#define WM8350_RTC_BCD_MASK 0x8000
#define WM8350_RTC_BCD_SHIFT 15
#define WM8350_RTC_12HR 0x4000
#define WM8350_RTC_12HR_MASK 0x4000
#define WM8350_RTC_12HR_SHIFT 14
#define WM8350_RTC_DST 0x2000
#define WM8350_RTC_DST_MASK 0x2000
#define WM8350_RTC_DST_SHIFT 13
#define WM8350_RTC_SET 0x0800
#define WM8350_RTC_SET_MASK 0x0800
#define WM8350_RTC_SET_SHIFT 11
#define WM8350_RTC_STS 0x0400
#define WM8350_RTC_STS_MASK 0x0400
#define WM8350_RTC_STS_SHIFT 10
#define WM8350_RTC_ALMSET 0x0200
#define WM8350_RTC_ALMSET_MASK 0x0200
#define WM8350_RTC_ALMSET_SHIFT 9
#define WM8350_RTC_ALMSTS 0x0100
#define WM8350_RTC_ALMSTS_MASK 0x0100
#define WM8350_RTC_ALMSTS_SHIFT 8
#define WM8350_RTC_PINT 0x0070
#define WM8350_RTC_PINT_MASK 0x0070
#define WM8350_RTC_PINT_SHIFT 4
#define WM8350_RTC_DSW 0x000F
#define WM8350_RTC_DSW_MASK 0x000F
#define WM8350_RTC_DSW_SHIFT 0
/* Bit values for R23 (0x17) */
#define WM8350_RTC_BCD_BINARY 0
#define WM8350_RTC_BCD_BCD 1
#define WM8350_RTC_12HR_24HR 0
#define WM8350_RTC_12HR_12HR 1
#define WM8350_RTC_DST_DISABLED 0
#define WM8350_RTC_DST_ENABLED 1
#define WM8350_RTC_SET_RUN 0
#define WM8350_RTC_SET_SET 1
#define WM8350_RTC_STS_RUNNING 0
#define WM8350_RTC_STS_STOPPED 1
#define WM8350_RTC_ALMSET_RUN 0
#define WM8350_RTC_ALMSET_SET 1
#define WM8350_RTC_ALMSTS_RUNNING 0
#define WM8350_RTC_ALMSTS_STOPPED 1
#define WM8350_RTC_PINT_DISABLED 0
#define WM8350_RTC_PINT_SECS 1
#define WM8350_RTC_PINT_MINS 2
#define WM8350_RTC_PINT_HRS 3
#define WM8350_RTC_PINT_DAYS 4
#define WM8350_RTC_PINT_MTHS 5
#define WM8350_RTC_DSW_DISABLED 0
#define WM8350_RTC_DSW_1HZ 1
#define WM8350_RTC_DSW_2HZ 2
#define WM8350_RTC_DSW_4HZ 3
#define WM8350_RTC_DSW_8HZ 4
#define WM8350_RTC_DSW_16HZ 5
#define WM8350_RTC_DSW_32HZ 6
#define WM8350_RTC_DSW_64HZ 7
#define WM8350_RTC_DSW_128HZ 8
#define WM8350_RTC_DSW_256HZ 9
#define WM8350_RTC_DSW_512HZ 10
#define WM8350_RTC_DSW_1024HZ 11
/*
* R218 (0xDA) - RTC Tick Control
*/
#define WM8350_RTC_TICKSTS 0x4000
#define WM8350_RTC_CLKSRC 0x2000
#define WM8350_RTC_TRIM_MASK 0x03FF
/*
* RTC Interrupts.
*/
#define WM8350_IRQ_RTC_PER 7
#define WM8350_IRQ_RTC_SEC 8
#define WM8350_IRQ_RTC_ALM 9
struct wm8350_rtc {
struct platform_device *pdev;
};
#endif

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/*
* supply.h -- Power Supply Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_SUPPLY_H_
#define __LINUX_MFD_WM8350_SUPPLY_H_
#include <linux/platform_device.h>
/*
* Charger registers
*/
#define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8
#define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9
#define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA
/*
* R168 (0xA8) - Battery Charger Control 1
*/
#define WM8350_CHG_ENA_R168 0x8000
#define WM8350_CHG_THR 0x2000
#define WM8350_CHG_EOC_SEL_MASK 0x1C00
#define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200
#define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100
#define WM8350_CHG_RECOVER_T 0x0080
#define WM8350_CHG_END_ACT 0x0040
#define WM8350_CHG_FAST 0x0020
#define WM8350_CHG_FAST_USB_THROTTLE 0x0010
#define WM8350_CHG_NTC_MON 0x0008
#define WM8350_CHG_BATT_HOT_MON 0x0004
#define WM8350_CHG_BATT_COLD_MON 0x0002
#define WM8350_CHG_CHIP_TEMP_MON 0x0001
/*
* R169 (0xA9) - Battery Charger Control 2
*/
#define WM8350_CHG_ACTIVE 0x8000
#define WM8350_CHG_PAUSE 0x4000
#define WM8350_CHG_STS_MASK 0x3000
#define WM8350_CHG_TIME_MASK 0x0F00
#define WM8350_CHG_MASK_WALL_FB 0x0080
#define WM8350_CHG_TRICKLE_SEL 0x0040
#define WM8350_CHG_VSEL_MASK 0x0030
#define WM8350_CHG_ISEL_MASK 0x000F
#define WM8350_CHG_STS_OFF 0x0000
#define WM8350_CHG_STS_TRICKLE 0x1000
#define WM8350_CHG_STS_FAST 0x2000
/*
* R170 (0xAA) - Battery Charger Control 3
*/
#define WM8350_CHG_THROTTLE_T_MASK 0x0060
#define WM8350_CHG_SMART 0x0010
#define WM8350_CHG_TIMER_ADJT_MASK 0x000F
/*
* Charger Interrupts
*/
#define WM8350_IRQ_CHG_BAT_HOT 0
#define WM8350_IRQ_CHG_BAT_COLD 1
#define WM8350_IRQ_CHG_BAT_FAIL 2
#define WM8350_IRQ_CHG_TO 3
#define WM8350_IRQ_CHG_END 4
#define WM8350_IRQ_CHG_START 5
#define WM8350_IRQ_CHG_FAST_RDY 6
#define WM8350_IRQ_CHG_VBATT_LT_3P9 10
#define WM8350_IRQ_CHG_VBATT_LT_3P1 11
#define WM8350_IRQ_CHG_VBATT_LT_2P85 12
/*
* Charger Policy
*/
#define WM8350_CHG_TRICKLE_50mA (0 << 6)
#define WM8350_CHG_TRICKLE_100mA (1 << 6)
#define WM8350_CHG_4_05V (0 << 4)
#define WM8350_CHG_4_10V (1 << 4)
#define WM8350_CHG_4_15V (2 << 4)
#define WM8350_CHG_4_20V (3 << 4)
#define WM8350_CHG_FAST_LIMIT_mA(x) ((x / 50) & 0xf)
#define WM8350_CHG_EOC_mA(x) (((x - 10) & 0x7) << 10)
#define WM8350_CHG_TRICKLE_3_1V (0 << 13)
#define WM8350_CHG_TRICKLE_3_9V (1 << 13)
/*
* Supply Registers.
*/
#define WM8350_USB_VOLTAGE_READBACK 0x9C
#define WM8350_LINE_VOLTAGE_READBACK 0x9D
#define WM8350_BATT_VOLTAGE_READBACK 0x9E
/*
* Supply Interrupts.
*/
#define WM8350_IRQ_USB_LIMIT 15
#define WM8350_IRQ_EXT_USB_FB 36
#define WM8350_IRQ_EXT_WALL_FB 37
#define WM8350_IRQ_EXT_BAT_FB 38
struct wm8350_power {
struct platform_device *pdev;
};
#endif

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/*
* wdt.h -- Watchdog Driver for Wolfson WM8350 PMIC
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_WM8350_WDT_H_
#define __LINUX_MFD_WM8350_WDT_H_
#include <linux/platform_device.h>
#define WM8350_WDOG_HIB_MODE 0x0080
#define WM8350_WDOG_DEBUG 0x0040
#define WM8350_WDOG_MODE_MASK 0x0030
#define WM8350_WDOG_TO_MASK 0x0007
#define WM8350_IRQ_SYS_WDOG_TO 24
struct wm8350_wdt {
struct platform_device *pdev;
};
#endif

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/*
* wm8400 private definitions.
*
* Copyright 2008 Wolfson Microelectronics plc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __LINUX_MFD_WM8400_PRIV_H
#define __LINUX_MFD_WM8400_PRIV_H
#include <linux/mfd/wm8400.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#define WM8400_REGISTER_COUNT 0x55
struct wm8400 {
struct device *dev;
int (*read_dev)(void *data, char reg, int count, u16 *dst);
int (*write_dev)(void *data, char reg, int count, const u16 *src);
struct mutex io_lock;
void *io_data;
u16 reg_cache[WM8400_REGISTER_COUNT];
struct platform_device regulators[6];
};
/*
* Register values.
*/
#define WM8400_RESET_ID 0x00
#define WM8400_ID 0x01
#define WM8400_POWER_MANAGEMENT_1 0x02
#define WM8400_POWER_MANAGEMENT_2 0x03
#define WM8400_POWER_MANAGEMENT_3 0x04
#define WM8400_AUDIO_INTERFACE_1 0x05
#define WM8400_AUDIO_INTERFACE_2 0x06
#define WM8400_CLOCKING_1 0x07
#define WM8400_CLOCKING_2 0x08
#define WM8400_AUDIO_INTERFACE_3 0x09
#define WM8400_AUDIO_INTERFACE_4 0x0A
#define WM8400_DAC_CTRL 0x0B
#define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C
#define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D
#define WM8400_DIGITAL_SIDE_TONE 0x0E
#define WM8400_ADC_CTRL 0x0F
#define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10
#define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11
#define WM8400_GPIO_CTRL_1 0x12
#define WM8400_GPIO1_GPIO2 0x13
#define WM8400_GPIO3_GPIO4 0x14
#define WM8400_GPIO5_GPIO6 0x15
#define WM8400_GPIOCTRL_2 0x16
#define WM8400_GPIO_POL 0x17
#define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18
#define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19
#define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
#define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
#define WM8400_LEFT_OUTPUT_VOLUME 0x1C
#define WM8400_RIGHT_OUTPUT_VOLUME 0x1D
#define WM8400_LINE_OUTPUTS_VOLUME 0x1E
#define WM8400_OUT3_4_VOLUME 0x1F
#define WM8400_LEFT_OPGA_VOLUME 0x20
#define WM8400_RIGHT_OPGA_VOLUME 0x21
#define WM8400_SPEAKER_VOLUME 0x22
#define WM8400_CLASSD1 0x23
#define WM8400_CLASSD3 0x25
#define WM8400_INPUT_MIXER1 0x27
#define WM8400_INPUT_MIXER2 0x28
#define WM8400_INPUT_MIXER3 0x29
#define WM8400_INPUT_MIXER4 0x2A
#define WM8400_INPUT_MIXER5 0x2B
#define WM8400_INPUT_MIXER6 0x2C
#define WM8400_OUTPUT_MIXER1 0x2D
#define WM8400_OUTPUT_MIXER2 0x2E
#define WM8400_OUTPUT_MIXER3 0x2F
#define WM8400_OUTPUT_MIXER4 0x30
#define WM8400_OUTPUT_MIXER5 0x31
#define WM8400_OUTPUT_MIXER6 0x32
#define WM8400_OUT3_4_MIXER 0x33
#define WM8400_LINE_MIXER1 0x34
#define WM8400_LINE_MIXER2 0x35
#define WM8400_SPEAKER_MIXER 0x36
#define WM8400_ADDITIONAL_CONTROL 0x37
#define WM8400_ANTIPOP1 0x38
#define WM8400_ANTIPOP2 0x39
#define WM8400_MICBIAS 0x3A
#define WM8400_FLL_CONTROL_1 0x3C
#define WM8400_FLL_CONTROL_2 0x3D
#define WM8400_FLL_CONTROL_3 0x3E
#define WM8400_FLL_CONTROL_4 0x3F
#define WM8400_LDO1_CONTROL 0x41
#define WM8400_LDO2_CONTROL 0x42
#define WM8400_LDO3_CONTROL 0x43
#define WM8400_LDO4_CONTROL 0x44
#define WM8400_DCDC1_CONTROL_1 0x46
#define WM8400_DCDC1_CONTROL_2 0x47
#define WM8400_DCDC2_CONTROL_1 0x48
#define WM8400_DCDC2_CONTROL_2 0x49
#define WM8400_INTERFACE 0x4B
#define WM8400_PM_GENERAL 0x4C
#define WM8400_PM_SHUTDOWN_CONTROL 0x4E
#define WM8400_INTERRUPT_STATUS_1 0x4F
#define WM8400_INTERRUPT_STATUS_1_MASK 0x50
#define WM8400_INTERRUPT_LEVELS 0x51
#define WM8400_SHUTDOWN_REASON 0x52
#define WM8400_LINE_CIRCUITS 0x54
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Reset/ID
*/
#define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */
#define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */
#define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */
/*
* R1 (0x01) - ID
*/
#define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */
#define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */
#define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */
/*
* R18 (0x12) - GPIO CTRL 1
*/
#define WM8400_IRQ 0x1000 /* IRQ */
#define WM8400_IRQ_MASK 0x1000 /* IRQ */
#define WM8400_IRQ_SHIFT 12 /* IRQ */
#define WM8400_IRQ_WIDTH 1 /* IRQ */
#define WM8400_TEMPOK 0x0800 /* TEMPOK */
#define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */
#define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */
#define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */
#define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */
#define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */
#define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */
#define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */
#define WM8400_MIC1DET 0x0200 /* MIC1DET */
#define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */
#define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */
#define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */
#define WM8400_FLL_LCK 0x0100 /* FLL_LCK */
#define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */
#define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */
#define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */
#define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */
#define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */
#define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */
/*
* R19 (0x13) - GPIO1 & GPIO2
*/
#define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */
#define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */
#define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */
#define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
#define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */
#define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */
#define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */
#define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
#define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
#define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */
#define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */
#define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */
#define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
#define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
#define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
#define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */
#define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
#define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
#define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
#define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
#define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
#define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
/*
* R20 (0x14) - GPIO3 & GPIO4
*/
#define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */
#define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */
#define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */
#define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */
#define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */
#define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */
#define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */
#define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */
#define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
#define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */
#define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */
#define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */
#define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
#define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
#define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
#define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */
#define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
#define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
#define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
#define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
#define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
#define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
/*
* R21 (0x15) - GPIO5 & GPIO6
*/
#define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */
#define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */
#define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */
#define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */
#define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */
#define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */
#define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */
#define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */
#define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
#define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */
#define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */
#define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */
#define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */
#define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */
#define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */
#define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */
#define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */
#define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */
#define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */
#define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
#define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */
#define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */
/*
* R22 (0x16) - GPIOCTRL 2
*/
#define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
#define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */
#define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */
#define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA_SHIFT 9 /* MIC1DET_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA_WIDTH 1 /* MIC1DET_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8 /* FLL_LCK_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1 /* FLL_LCK_IRQ_ENA */
#define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
#define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */
#define WM8400_GPI8_DEB_ENA_SHIFT 7 /* GPI8_DEB_ENA */
#define WM8400_GPI8_DEB_ENA_WIDTH 1 /* GPI8_DEB_ENA */
#define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_IRQ_ENA_SHIFT 6 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_IRQ_ENA_WIDTH 1 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */
#define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */
#define WM8400_GPI8_ENA_SHIFT 4 /* GPI8_ENA */
#define WM8400_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
#define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
#define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */
#define WM8400_GPI7_DEB_ENA_SHIFT 3 /* GPI7_DEB_ENA */
#define WM8400_GPI7_DEB_ENA_WIDTH 1 /* GPI7_DEB_ENA */
#define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_IRQ_ENA_SHIFT 2 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_IRQ_ENA_WIDTH 1 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */
#define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */
#define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */
#define WM8400_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
/*
* R23 (0x17) - GPIO_POL
*/
#define WM8400_IRQ_INV 0x1000 /* IRQ_INV */
#define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */
#define WM8400_IRQ_INV_SHIFT 12 /* IRQ_INV */
#define WM8400_IRQ_INV_WIDTH 1 /* IRQ_INV */
#define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */
#define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */
#define WM8400_TEMPOK_POL_SHIFT 11 /* TEMPOK_POL */
#define WM8400_TEMPOK_POL_WIDTH 1 /* TEMPOK_POL */
#define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */
#define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */
#define WM8400_MIC1SHRT_POL_SHIFT 10 /* MIC1SHRT_POL */
#define WM8400_MIC1SHRT_POL_WIDTH 1 /* MIC1SHRT_POL */
#define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */
#define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */
#define WM8400_MIC1DET_POL_SHIFT 9 /* MIC1DET_POL */
#define WM8400_MIC1DET_POL_WIDTH 1 /* MIC1DET_POL */
#define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */
#define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */
#define WM8400_FLL_LCK_POL_SHIFT 8 /* FLL_LCK_POL */
#define WM8400_FLL_LCK_POL_WIDTH 1 /* FLL_LCK_POL */
#define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */
#define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */
#define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */
/*
* R65 (0x41) - LDO 1 Control
*/
#define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */
#define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */
#define WM8400_LDO1_ENA_SHIFT 15 /* LDO1_ENA */
#define WM8400_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
#define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */
#define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */
#define WM8400_LDO1_SWI_SHIFT 14 /* LDO1_SWI */
#define WM8400_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
#define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */
#define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */
#define WM8400_LDO1_OPFLT_SHIFT 12 /* LDO1_OPFLT */
#define WM8400_LDO1_OPFLT_WIDTH 1 /* LDO1_OPFLT */
#define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */
#define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */
#define WM8400_LDO1_ERRACT_SHIFT 11 /* LDO1_ERRACT */
#define WM8400_LDO1_ERRACT_WIDTH 1 /* LDO1_ERRACT */
#define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */
#define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */
#define WM8400_LDO1_HIB_MODE_SHIFT 10 /* LDO1_HIB_MODE */
#define WM8400_LDO1_HIB_MODE_WIDTH 1 /* LDO1_HIB_MODE */
#define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */
#define WM8400_LDO1_VIMG_SHIFT 5 /* LDO1_VIMG - [9:5] */
#define WM8400_LDO1_VIMG_WIDTH 5 /* LDO1_VIMG - [9:5] */
#define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */
#define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */
#define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */
/*
* R66 (0x42) - LDO 2 Control
*/
#define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */
#define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */
#define WM8400_LDO2_ENA_SHIFT 15 /* LDO2_ENA */
#define WM8400_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
#define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */
#define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */
#define WM8400_LDO2_SWI_SHIFT 14 /* LDO2_SWI */
#define WM8400_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
#define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */
#define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */
#define WM8400_LDO2_OPFLT_SHIFT 12 /* LDO2_OPFLT */
#define WM8400_LDO2_OPFLT_WIDTH 1 /* LDO2_OPFLT */
#define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */
#define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */
#define WM8400_LDO2_ERRACT_SHIFT 11 /* LDO2_ERRACT */
#define WM8400_LDO2_ERRACT_WIDTH 1 /* LDO2_ERRACT */
#define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */
#define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */
#define WM8400_LDO2_HIB_MODE_SHIFT 10 /* LDO2_HIB_MODE */
#define WM8400_LDO2_HIB_MODE_WIDTH 1 /* LDO2_HIB_MODE */
#define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */
#define WM8400_LDO2_VIMG_SHIFT 5 /* LDO2_VIMG - [9:5] */
#define WM8400_LDO2_VIMG_WIDTH 5 /* LDO2_VIMG - [9:5] */
#define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */
#define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */
#define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */
/*
* R67 (0x43) - LDO 3 Control
*/
#define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */
#define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */
#define WM8400_LDO3_ENA_SHIFT 15 /* LDO3_ENA */
#define WM8400_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
#define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */
#define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */
#define WM8400_LDO3_SWI_SHIFT 14 /* LDO3_SWI */
#define WM8400_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
#define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */
#define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */
#define WM8400_LDO3_OPFLT_SHIFT 12 /* LDO3_OPFLT */
#define WM8400_LDO3_OPFLT_WIDTH 1 /* LDO3_OPFLT */
#define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */
#define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */
#define WM8400_LDO3_ERRACT_SHIFT 11 /* LDO3_ERRACT */
#define WM8400_LDO3_ERRACT_WIDTH 1 /* LDO3_ERRACT */
#define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */
#define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */
#define WM8400_LDO3_HIB_MODE_SHIFT 10 /* LDO3_HIB_MODE */
#define WM8400_LDO3_HIB_MODE_WIDTH 1 /* LDO3_HIB_MODE */
#define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */
#define WM8400_LDO3_VIMG_SHIFT 5 /* LDO3_VIMG - [9:5] */
#define WM8400_LDO3_VIMG_WIDTH 5 /* LDO3_VIMG - [9:5] */
#define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */
#define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */
#define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */
/*
* R68 (0x44) - LDO 4 Control
*/
#define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */
#define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */
#define WM8400_LDO4_ENA_SHIFT 15 /* LDO4_ENA */
#define WM8400_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
#define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */
#define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */
#define WM8400_LDO4_SWI_SHIFT 14 /* LDO4_SWI */
#define WM8400_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
#define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */
#define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */
#define WM8400_LDO4_OPFLT_SHIFT 12 /* LDO4_OPFLT */
#define WM8400_LDO4_OPFLT_WIDTH 1 /* LDO4_OPFLT */
#define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */
#define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */
#define WM8400_LDO4_ERRACT_SHIFT 11 /* LDO4_ERRACT */
#define WM8400_LDO4_ERRACT_WIDTH 1 /* LDO4_ERRACT */
#define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */
#define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */
#define WM8400_LDO4_HIB_MODE_SHIFT 10 /* LDO4_HIB_MODE */
#define WM8400_LDO4_HIB_MODE_WIDTH 1 /* LDO4_HIB_MODE */
#define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */
#define WM8400_LDO4_VIMG_SHIFT 5 /* LDO4_VIMG - [9:5] */
#define WM8400_LDO4_VIMG_WIDTH 5 /* LDO4_VIMG - [9:5] */
#define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */
#define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */
#define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */
/*
* R70 (0x46) - DCDC1 Control 1
*/
#define WM8400_DC1_ENA 0x8000 /* DC1_ENA */
#define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */
#define WM8400_DC1_ENA_SHIFT 15 /* DC1_ENA */
#define WM8400_DC1_ENA_WIDTH 1 /* DC1_ENA */
#define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */
#define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */
#define WM8400_DC1_ACTIVE_SHIFT 14 /* DC1_ACTIVE */
#define WM8400_DC1_ACTIVE_WIDTH 1 /* DC1_ACTIVE */
#define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */
#define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */
#define WM8400_DC1_SLEEP_SHIFT 13 /* DC1_SLEEP */
#define WM8400_DC1_SLEEP_WIDTH 1 /* DC1_SLEEP */
#define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */
#define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */
#define WM8400_DC1_OPFLT_SHIFT 12 /* DC1_OPFLT */
#define WM8400_DC1_OPFLT_WIDTH 1 /* DC1_OPFLT */
#define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */
#define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */
#define WM8400_DC1_ERRACT_SHIFT 11 /* DC1_ERRACT */
#define WM8400_DC1_ERRACT_WIDTH 1 /* DC1_ERRACT */
#define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */
#define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */
#define WM8400_DC1_HIB_MODE_SHIFT 10 /* DC1_HIB_MODE */
#define WM8400_DC1_HIB_MODE_WIDTH 1 /* DC1_HIB_MODE */
#define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */
#define WM8400_DC1_SOFTST_SHIFT 8 /* DC1_SOFTST - [9:8] */
#define WM8400_DC1_SOFTST_WIDTH 2 /* DC1_SOFTST - [9:8] */
#define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */
#define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */
#define WM8400_DC1_OV_PROT_SHIFT 7 /* DC1_OV_PROT */
#define WM8400_DC1_OV_PROT_WIDTH 1 /* DC1_OV_PROT */
#define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */
#define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */
#define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */
/*
* R71 (0x47) - DCDC1 Control 2
*/
#define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */
#define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */
#define WM8400_DC1_FRC_PWM_SHIFT 13 /* DC1_FRC_PWM */
#define WM8400_DC1_FRC_PWM_WIDTH 1 /* DC1_FRC_PWM */
#define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */
#define WM8400_DC1_STBY_LIM_SHIFT 8 /* DC1_STBY_LIM - [9:8] */
#define WM8400_DC1_STBY_LIM_WIDTH 2 /* DC1_STBY_LIM - [9:8] */
#define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */
#define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */
#define WM8400_DC1_ACT_LIM_SHIFT 7 /* DC1_ACT_LIM */
#define WM8400_DC1_ACT_LIM_WIDTH 1 /* DC1_ACT_LIM */
#define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */
#define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */
#define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */
/*
* R72 (0x48) - DCDC2 Control 1
*/
#define WM8400_DC2_ENA 0x8000 /* DC2_ENA */
#define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */
#define WM8400_DC2_ENA_SHIFT 15 /* DC2_ENA */
#define WM8400_DC2_ENA_WIDTH 1 /* DC2_ENA */
#define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */
#define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */
#define WM8400_DC2_ACTIVE_SHIFT 14 /* DC2_ACTIVE */
#define WM8400_DC2_ACTIVE_WIDTH 1 /* DC2_ACTIVE */
#define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */
#define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */
#define WM8400_DC2_SLEEP_SHIFT 13 /* DC2_SLEEP */
#define WM8400_DC2_SLEEP_WIDTH 1 /* DC2_SLEEP */
#define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */
#define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */
#define WM8400_DC2_OPFLT_SHIFT 12 /* DC2_OPFLT */
#define WM8400_DC2_OPFLT_WIDTH 1 /* DC2_OPFLT */
#define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */
#define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */
#define WM8400_DC2_ERRACT_SHIFT 11 /* DC2_ERRACT */
#define WM8400_DC2_ERRACT_WIDTH 1 /* DC2_ERRACT */
#define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */
#define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */
#define WM8400_DC2_HIB_MODE_SHIFT 10 /* DC2_HIB_MODE */
#define WM8400_DC2_HIB_MODE_WIDTH 1 /* DC2_HIB_MODE */
#define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */
#define WM8400_DC2_SOFTST_SHIFT 8 /* DC2_SOFTST - [9:8] */
#define WM8400_DC2_SOFTST_WIDTH 2 /* DC2_SOFTST - [9:8] */
#define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */
#define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */
#define WM8400_DC2_OV_PROT_SHIFT 7 /* DC2_OV_PROT */
#define WM8400_DC2_OV_PROT_WIDTH 1 /* DC2_OV_PROT */
#define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */
#define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */
#define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */
/*
* R73 (0x49) - DCDC2 Control 2
*/
#define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */
#define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */
#define WM8400_DC2_FRC_PWM_SHIFT 13 /* DC2_FRC_PWM */
#define WM8400_DC2_FRC_PWM_WIDTH 1 /* DC2_FRC_PWM */
#define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */
#define WM8400_DC2_STBY_LIM_SHIFT 8 /* DC2_STBY_LIM - [9:8] */
#define WM8400_DC2_STBY_LIM_WIDTH 2 /* DC2_STBY_LIM - [9:8] */
#define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */
#define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */
#define WM8400_DC2_ACT_LIM_SHIFT 7 /* DC2_ACT_LIM */
#define WM8400_DC2_ACT_LIM_WIDTH 1 /* DC2_ACT_LIM */
#define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */
#define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */
#define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */
/*
* R75 (0x4B) - Interface
*/
#define WM8400_AUTOINC 0x0008 /* AUTOINC */
#define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */
#define WM8400_AUTOINC_SHIFT 3 /* AUTOINC */
#define WM8400_AUTOINC_WIDTH 1 /* AUTOINC */
#define WM8400_ARA_ENA 0x0004 /* ARA_ENA */
#define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */
#define WM8400_ARA_ENA_SHIFT 2 /* ARA_ENA */
#define WM8400_ARA_ENA_WIDTH 1 /* ARA_ENA */
#define WM8400_SPI_CFG 0x0002 /* SPI_CFG */
#define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */
#define WM8400_SPI_CFG_SHIFT 1 /* SPI_CFG */
#define WM8400_SPI_CFG_WIDTH 1 /* SPI_CFG */
/*
* R76 (0x4C) - PM GENERAL
*/
#define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTST_SHIFT 15 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTST_WIDTH 1 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */
#define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */
#define WM8400_CODEC_SOFTSD_SHIFT 14 /* CODEC_SOFTSD */
#define WM8400_CODEC_SOFTSD_WIDTH 1 /* CODEC_SOFTSD */
#define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */
#define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */
#define WM8400_CHIP_SOFTSD_SHIFT 13 /* CHIP_SOFTSD */
#define WM8400_CHIP_SOFTSD_WIDTH 1 /* CHIP_SOFTSD */
#define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */
#define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */
#define WM8400_DSLEEP1_POL_SHIFT 3 /* DSLEEP1_POL */
#define WM8400_DSLEEP1_POL_WIDTH 1 /* DSLEEP1_POL */
#define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */
#define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */
#define WM8400_DSLEEP2_POL_SHIFT 2 /* DSLEEP2_POL */
#define WM8400_DSLEEP2_POL_WIDTH 1 /* DSLEEP2_POL */
#define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */
#define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */
#define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */
/*
* R78 (0x4E) - PM Shutdown Control
*/
#define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT150_ERRACT_SHIFT 9 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT150_ERRACT_WIDTH 1 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */
#define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */
#define WM8400_CHIP_GT115_ERRACT_SHIFT 8 /* CHIP_GT115_ERRACT */
#define WM8400_CHIP_GT115_ERRACT_WIDTH 1 /* CHIP_GT115_ERRACT */
#define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */
#define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */
#define WM8400_LINE_CMP_ERRACT_SHIFT 7 /* LINE_CMP_ERRACT */
#define WM8400_LINE_CMP_ERRACT_WIDTH 1 /* LINE_CMP_ERRACT */
#define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */
#define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */
#define WM8400_UVLO_ERRACT_SHIFT 6 /* UVLO_ERRACT */
#define WM8400_UVLO_ERRACT_WIDTH 1 /* UVLO_ERRACT */
/*
* R79 (0x4F) - Interrupt Status 1
*/
#define WM8400_MICD_CINT 0x8000 /* MICD_CINT */
#define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */
#define WM8400_MICD_CINT_SHIFT 15 /* MICD_CINT */
#define WM8400_MICD_CINT_WIDTH 1 /* MICD_CINT */
#define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */
#define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */
#define WM8400_MICSCD_CINT_SHIFT 14 /* MICSCD_CINT */
#define WM8400_MICSCD_CINT_WIDTH 1 /* MICSCD_CINT */
#define WM8400_JDL_CINT 0x2000 /* JDL_CINT */
#define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */
#define WM8400_JDL_CINT_SHIFT 13 /* JDL_CINT */
#define WM8400_JDL_CINT_WIDTH 1 /* JDL_CINT */
#define WM8400_JDR_CINT 0x1000 /* JDR_CINT */
#define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */
#define WM8400_JDR_CINT_SHIFT 12 /* JDR_CINT */
#define WM8400_JDR_CINT_WIDTH 1 /* JDR_CINT */
#define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */
#define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */
#define WM8400_CODEC_SEQ_END_EINT_SHIFT 11 /* CODEC_SEQ_END_EINT */
#define WM8400_CODEC_SEQ_END_EINT_WIDTH 1 /* CODEC_SEQ_END_EINT */
#define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */
#define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */
#define WM8400_CDEL_TO_EINT_SHIFT 10 /* CDEL_TO_EINT */
#define WM8400_CDEL_TO_EINT_WIDTH 1 /* CDEL_TO_EINT */
#define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT150_EINT_SHIFT 9 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT150_EINT_WIDTH 1 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */
#define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */
#define WM8400_CHIP_GT115_EINT_SHIFT 8 /* CHIP_GT115_EINT */
#define WM8400_CHIP_GT115_EINT_WIDTH 1 /* CHIP_GT115_EINT */
#define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */
#define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */
#define WM8400_LINE_CMP_EINT_SHIFT 7 /* LINE_CMP_EINT */
#define WM8400_LINE_CMP_EINT_WIDTH 1 /* LINE_CMP_EINT */
#define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */
#define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */
#define WM8400_UVLO_EINT_SHIFT 6 /* UVLO_EINT */
#define WM8400_UVLO_EINT_WIDTH 1 /* UVLO_EINT */
#define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */
#define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */
#define WM8400_DC2_UV_EINT_SHIFT 5 /* DC2_UV_EINT */
#define WM8400_DC2_UV_EINT_WIDTH 1 /* DC2_UV_EINT */
#define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */
#define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */
#define WM8400_DC1_UV_EINT_SHIFT 4 /* DC1_UV_EINT */
#define WM8400_DC1_UV_EINT_WIDTH 1 /* DC1_UV_EINT */
#define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */
#define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */
#define WM8400_LDO4_UV_EINT_SHIFT 3 /* LDO4_UV_EINT */
#define WM8400_LDO4_UV_EINT_WIDTH 1 /* LDO4_UV_EINT */
#define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */
#define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */
#define WM8400_LDO3_UV_EINT_SHIFT 2 /* LDO3_UV_EINT */
#define WM8400_LDO3_UV_EINT_WIDTH 1 /* LDO3_UV_EINT */
#define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */
#define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */
#define WM8400_LDO2_UV_EINT_SHIFT 1 /* LDO2_UV_EINT */
#define WM8400_LDO2_UV_EINT_WIDTH 1 /* LDO2_UV_EINT */
#define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */
#define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */
#define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */
#define WM8400_LDO1_UV_EINT_WIDTH 1 /* LDO1_UV_EINT */
/*
* R80 (0x50) - Interrupt Status 1 Mask
*/
#define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */
#define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */
#define WM8400_IM_MICD_CINT_SHIFT 15 /* IM_MICD_CINT */
#define WM8400_IM_MICD_CINT_WIDTH 1 /* IM_MICD_CINT */
#define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */
#define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */
#define WM8400_IM_MICSCD_CINT_SHIFT 14 /* IM_MICSCD_CINT */
#define WM8400_IM_MICSCD_CINT_WIDTH 1 /* IM_MICSCD_CINT */
#define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */
#define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */
#define WM8400_IM_JDL_CINT_SHIFT 13 /* IM_JDL_CINT */
#define WM8400_IM_JDL_CINT_WIDTH 1 /* IM_JDL_CINT */
#define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */
#define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */
#define WM8400_IM_JDR_CINT_SHIFT 12 /* IM_JDR_CINT */
#define WM8400_IM_JDR_CINT_WIDTH 1 /* IM_JDR_CINT */
#define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CDEL_TO_EINT_SHIFT 10 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CDEL_TO_EINT_WIDTH 1 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT150_EINT_SHIFT 9 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT150_EINT_WIDTH 1 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_CHIP_GT115_EINT_SHIFT 8 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_CHIP_GT115_EINT_WIDTH 1 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */
#define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */
#define WM8400_IM_LINE_CMP_EINT_SHIFT 7 /* IM_LINE_CMP_EINT */
#define WM8400_IM_LINE_CMP_EINT_WIDTH 1 /* IM_LINE_CMP_EINT */
#define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */
#define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */
#define WM8400_IM_UVLO_EINT_SHIFT 6 /* IM_UVLO_EINT */
#define WM8400_IM_UVLO_EINT_WIDTH 1 /* IM_UVLO_EINT */
#define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC2_UV_EINT_SHIFT 5 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC2_UV_EINT_WIDTH 1 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */
#define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */
#define WM8400_IM_DC1_UV_EINT_SHIFT 4 /* IM_DC1_UV_EINT */
#define WM8400_IM_DC1_UV_EINT_WIDTH 1 /* IM_DC1_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT_SHIFT 3 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT_WIDTH 1 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT_SHIFT 2 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT_WIDTH 1 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT_SHIFT 1 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT_WIDTH 1 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT_WIDTH 1 /* IM_LDO1_UV_EINT */
/*
* R81 (0x51) - Interrupt Levels
*/
#define WM8400_MICD_LVL 0x8000 /* MICD_LVL */
#define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */
#define WM8400_MICD_LVL_SHIFT 15 /* MICD_LVL */
#define WM8400_MICD_LVL_WIDTH 1 /* MICD_LVL */
#define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */
#define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */
#define WM8400_MICSCD_LVL_SHIFT 14 /* MICSCD_LVL */
#define WM8400_MICSCD_LVL_WIDTH 1 /* MICSCD_LVL */
#define WM8400_JDL_LVL 0x2000 /* JDL_LVL */
#define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */
#define WM8400_JDL_LVL_SHIFT 13 /* JDL_LVL */
#define WM8400_JDL_LVL_WIDTH 1 /* JDL_LVL */
#define WM8400_JDR_LVL 0x1000 /* JDR_LVL */
#define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */
#define WM8400_JDR_LVL_SHIFT 12 /* JDR_LVL */
#define WM8400_JDR_LVL_WIDTH 1 /* JDR_LVL */
#define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */
#define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */
#define WM8400_CODEC_SEQ_END_LVL_SHIFT 11 /* CODEC_SEQ_END_LVL */
#define WM8400_CODEC_SEQ_END_LVL_WIDTH 1 /* CODEC_SEQ_END_LVL */
#define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */
#define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */
#define WM8400_CDEL_TO_LVL_SHIFT 10 /* CDEL_TO_LVL */
#define WM8400_CDEL_TO_LVL_WIDTH 1 /* CDEL_TO_LVL */
#define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT150_LVL_SHIFT 9 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT150_LVL_WIDTH 1 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */
#define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */
#define WM8400_CHIP_GT115_LVL_SHIFT 8 /* CHIP_GT115_LVL */
#define WM8400_CHIP_GT115_LVL_WIDTH 1 /* CHIP_GT115_LVL */
#define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */
#define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */
#define WM8400_LINE_CMP_LVL_SHIFT 7 /* LINE_CMP_LVL */
#define WM8400_LINE_CMP_LVL_WIDTH 1 /* LINE_CMP_LVL */
#define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */
#define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */
#define WM8400_UVLO_LVL_SHIFT 6 /* UVLO_LVL */
#define WM8400_UVLO_LVL_WIDTH 1 /* UVLO_LVL */
#define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */
#define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */
#define WM8400_DC2_UV_LVL_SHIFT 5 /* DC2_UV_LVL */
#define WM8400_DC2_UV_LVL_WIDTH 1 /* DC2_UV_LVL */
#define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */
#define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */
#define WM8400_DC1_UV_LVL_SHIFT 4 /* DC1_UV_LVL */
#define WM8400_DC1_UV_LVL_WIDTH 1 /* DC1_UV_LVL */
#define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */
#define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */
#define WM8400_LDO4_UV_LVL_SHIFT 3 /* LDO4_UV_LVL */
#define WM8400_LDO4_UV_LVL_WIDTH 1 /* LDO4_UV_LVL */
#define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */
#define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */
#define WM8400_LDO3_UV_LVL_SHIFT 2 /* LDO3_UV_LVL */
#define WM8400_LDO3_UV_LVL_WIDTH 1 /* LDO3_UV_LVL */
#define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */
#define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */
#define WM8400_LDO2_UV_LVL_SHIFT 1 /* LDO2_UV_LVL */
#define WM8400_LDO2_UV_LVL_WIDTH 1 /* LDO2_UV_LVL */
#define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */
#define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */
#define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */
#define WM8400_LDO1_UV_LVL_WIDTH 1 /* LDO1_UV_LVL */
/*
* R82 (0x52) - Shutdown Reason
*/
#define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_CHIP_SOFTSD_SHIFT 13 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_CHIP_SOFTSD_WIDTH 1 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */
#define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */
#define WM8400_SDR_NPDN_SHIFT 11 /* SDR_NPDN */
#define WM8400_SDR_NPDN_WIDTH 1 /* SDR_NPDN */
#define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT150_SHIFT 9 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT150_WIDTH 1 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */
#define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */
#define WM8400_SDR_CHIP_GT115_SHIFT 8 /* SDR_CHIP_GT115 */
#define WM8400_SDR_CHIP_GT115_WIDTH 1 /* SDR_CHIP_GT115 */
#define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */
#define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */
#define WM8400_SDR_LINE_CMP_SHIFT 7 /* SDR_LINE_CMP */
#define WM8400_SDR_LINE_CMP_WIDTH 1 /* SDR_LINE_CMP */
#define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */
#define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */
#define WM8400_SDR_UVLO_SHIFT 6 /* SDR_UVLO */
#define WM8400_SDR_UVLO_WIDTH 1 /* SDR_UVLO */
#define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */
#define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */
#define WM8400_SDR_DC2_UV_SHIFT 5 /* SDR_DC2_UV */
#define WM8400_SDR_DC2_UV_WIDTH 1 /* SDR_DC2_UV */
#define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */
#define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */
#define WM8400_SDR_DC1_UV_SHIFT 4 /* SDR_DC1_UV */
#define WM8400_SDR_DC1_UV_WIDTH 1 /* SDR_DC1_UV */
#define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO4_UV_SHIFT 3 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO4_UV_WIDTH 1 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO3_UV_SHIFT 2 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO3_UV_WIDTH 1 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO2_UV_SHIFT 1 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO2_UV_WIDTH 1 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */
#define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */
#define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */
#define WM8400_SDR_LDO1_UV_WIDTH 1 /* SDR_LDO1_UV */
/*
* R84 (0x54) - Line Circuits
*/
#define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */
#define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */
#define WM8400_BG_LINE_COMP_SHIFT 15 /* BG_LINE_COMP */
#define WM8400_BG_LINE_COMP_WIDTH 1 /* BG_LINE_COMP */
#define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */
#define WM8400_LINE_CMP_VTHI_SHIFT 4 /* LINE_CMP_VTHI - [7:4] */
#define WM8400_LINE_CMP_VTHI_WIDTH 4 /* LINE_CMP_VTHI - [7:4] */
#define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */
#define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */
#define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */
u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val);
#endif

40
include/linux/mfd/wm8400.h Normal file
View file

@ -0,0 +1,40 @@
/*
* wm8400 client interface
*
* Copyright 2008 Wolfson Microelectronics plc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __LINUX_MFD_WM8400_H
#define __LINUX_MFD_WM8400_H
#include <linux/regulator/machine.h>
#define WM8400_LDO1 0
#define WM8400_LDO2 1
#define WM8400_LDO3 2
#define WM8400_LDO4 3
#define WM8400_DCDC1 4
#define WM8400_DCDC2 5
struct wm8400_platform_data {
int (*platform_init)(struct device *dev);
};
int wm8400_register_regulator(struct device *dev, int reg,
struct regulator_init_data *initdata);
#endif

4
include/linux/mlx4/device.h
View file

@ -141,6 +141,10 @@ enum {
MLX4_STAT_RATE_OFFSET = 5
};
enum {
MLX4_MTT_FLAG_PRESENT = 1
};
static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
{
return (major << 32) | (minor << 16) | subminor;

13
include/linux/mm.h
View file

@ -7,6 +7,7 @@
#include <linux/gfp.h>
#include <linux/list.h>
#include <linux/mmdebug.h>
#include <linux/mmzone.h>
#include <linux/rbtree.h>
#include <linux/prio_tree.h>
@ -219,12 +220,6 @@ struct inode;
*/
#include <linux/page-flags.h>
#ifdef CONFIG_DEBUG_VM
#define VM_BUG_ON(cond) BUG_ON(cond)
#else
#define VM_BUG_ON(condition) do { } while(0)
#endif
/*
* Methods to modify the page usage count.
*
@ -919,7 +914,7 @@ static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long a
}
#endif /* CONFIG_MMU && !__ARCH_HAS_4LEVEL_HACK */
#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
#if USE_SPLIT_PTLOCKS
/*
* We tuck a spinlock to guard each pagetable page into its struct page,
* at page->private, with BUILD_BUG_ON to make sure that this will not
@ -932,14 +927,14 @@ static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long a
} while (0)
#define pte_lock_deinit(page) ((page)->mapping = NULL)
#define pte_lockptr(mm, pmd) ({(void)(mm); __pte_lockptr(pmd_page(*(pmd)));})
#else
#else /* !USE_SPLIT_PTLOCKS */
/*
* We use mm->page_table_lock to guard all pagetable pages of the mm.
*/
#define pte_lock_init(page) do {} while (0)
#define pte_lock_deinit(page) do {} while (0)
#define pte_lockptr(mm, pmd) ({(void)(pmd); &(mm)->page_table_lock;})
#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
#endif /* USE_SPLIT_PTLOCKS */
static inline void pgtable_page_ctor(struct page *page)
{

10
include/linux/mm_types.h
View file

@ -21,11 +21,13 @@
struct address_space;
#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
#define USE_SPLIT_PTLOCKS (NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS)
#if USE_SPLIT_PTLOCKS
typedef atomic_long_t mm_counter_t;
#else /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
#else /* !USE_SPLIT_PTLOCKS */
typedef unsigned long mm_counter_t;
#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
#endif /* !USE_SPLIT_PTLOCKS */
/*
* Each physical page in the system has a struct page associated with
@ -65,7 +67,7 @@ struct page {
* see PAGE_MAPPING_ANON below.
*/
};
#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
#if USE_SPLIT_PTLOCKS
spinlock_t ptl;
#endif
struct kmem_cache *slab; /* SLUB: Pointer to slab */

2
include/linux/mmc/host.h
View file

@ -65,7 +65,7 @@ struct mmc_host_ops {
* -ENOSYS when not supported (equal to NULL callback)
* or a negative errno value when something bad happened
*
* Return values for the get_ro callback should be:
* Return values for the get_cd callback should be:
* 0 for a absent card
* 1 for a present card
* -ENOSYS when not supported (equal to NULL callback)

18
include/linux/mmdebug.h Normal file
View file

@ -0,0 +1,18 @@
#ifndef LINUX_MM_DEBUG_H
#define LINUX_MM_DEBUG_H 1
#include <linux/autoconf.h>
#ifdef CONFIG_DEBUG_VM
#define VM_BUG_ON(cond) BUG_ON(cond)
#else
#define VM_BUG_ON(cond) do { } while (0)
#endif
#ifdef CONFIG_DEBUG_VIRTUAL
#define VIRTUAL_BUG_ON(cond) BUG_ON(cond)
#else
#define VIRTUAL_BUG_ON(cond) do { } while (0)
#endif
#endif

12
include/linux/mmzone.h
View file

@ -751,8 +751,9 @@ static inline int zonelist_node_idx(struct zoneref *zoneref)
*
* This function returns the next zone at or below a given zone index that is
* within the allowed nodemask using a cursor as the starting point for the
* search. The zoneref returned is a cursor that is used as the next starting
* point for future calls to next_zones_zonelist().
* search. The zoneref returned is a cursor that represents the current zone
* being examined. It should be advanced by one before calling
* next_zones_zonelist again.
*/
struct zoneref *next_zones_zonelist(struct zoneref *z,
enum zone_type highest_zoneidx,
@ -768,9 +769,8 @@ struct zoneref *next_zones_zonelist(struct zoneref *z,
*
* This function returns the first zone at or below a given zone index that is
* within the allowed nodemask. The zoneref returned is a cursor that can be
* used to iterate the zonelist with next_zones_zonelist. The cursor should
* not be used by the caller as it does not match the value of the zone
* returned.
* used to iterate the zonelist with next_zones_zonelist by advancing it by
* one before calling.
*/
static inline struct zoneref *first_zones_zonelist(struct zonelist *zonelist,
enum zone_type highest_zoneidx,
@ -795,7 +795,7 @@ static inline struct zoneref *first_zones_zonelist(struct zonelist *zonelist,
#define for_each_zone_zonelist_nodemask(zone, z, zlist, highidx, nodemask) \
for (z = first_zones_zonelist(zlist, highidx, nodemask, &zone); \
zone; \
z = next_zones_zonelist(z, highidx, nodemask, &zone)) \
z = next_zones_zonelist(++z, highidx, nodemask, &zone)) \
/**
* for_each_zone_zonelist - helper macro to iterate over valid zones in a zonelist at or below a given zone index

47
include/linux/mod_devicetable.h
View file

@ -388,5 +388,52 @@ struct i2c_device_id {
__attribute__((aligned(sizeof(kernel_ulong_t))));
};
/* dmi */
enum dmi_field {
DMI_NONE,
DMI_BIOS_VENDOR,
DMI_BIOS_VERSION,
DMI_BIOS_DATE,
DMI_SYS_VENDOR,
DMI_PRODUCT_NAME,
DMI_PRODUCT_VERSION,
DMI_PRODUCT_SERIAL,
DMI_PRODUCT_UUID,
DMI_BOARD_VENDOR,
DMI_BOARD_NAME,
DMI_BOARD_VERSION,
DMI_BOARD_SERIAL,
DMI_BOARD_ASSET_TAG,
DMI_CHASSIS_VENDOR,
DMI_CHASSIS_TYPE,
DMI_CHASSIS_VERSION,
DMI_CHASSIS_SERIAL,
DMI_CHASSIS_ASSET_TAG,
DMI_STRING_MAX,
};
struct dmi_strmatch {
unsigned char slot;
char substr[79];
};
#ifndef __KERNEL__
struct dmi_system_id {
kernel_ulong_t callback;
kernel_ulong_t ident;
struct dmi_strmatch matches[4];
kernel_ulong_t driver_data
__attribute__((aligned(sizeof(kernel_ulong_t))));
};
#else
struct dmi_system_id {
int (*callback)(const struct dmi_system_id *);
const char *ident;
struct dmi_strmatch matches[4];
void *driver_data;
};
#endif
#define DMI_MATCH(a, b) { a, b }
#endif /* LINUX_MOD_DEVICETABLE_H */

2
include/linux/mtd/blktrans.h
View file

@ -41,6 +41,8 @@ struct mtd_blktrans_ops {
unsigned long block, char *buffer);
int (*writesect)(struct mtd_blktrans_dev *dev,
unsigned long block, char *buffer);
int (*discard)(struct mtd_blktrans_dev *dev,
unsigned long block, unsigned nr_blocks);
/* Block layer ioctls */
int (*getgeo)(struct mtd_blktrans_dev *dev, struct hd_geometry *geo);

13
include/linux/mv643xx_eth.h
View file

@ -17,9 +17,14 @@
struct mv643xx_eth_shared_platform_data {
struct mbus_dram_target_info *dram;
struct platform_device *shared_smi;
unsigned int t_clk;
};
#define MV643XX_ETH_PHY_ADDR_DEFAULT 0
#define MV643XX_ETH_PHY_ADDR(x) (0x80 | (x))
#define MV643XX_ETH_PHY_NONE 0xff
struct mv643xx_eth_platform_data {
/*
* Pointer back to our parent instance, and our port number.
@ -30,8 +35,6 @@ struct mv643xx_eth_platform_data {
/*
* Whether a PHY is present, and if yes, at which address.
*/
struct platform_device *shared_smi;
int force_phy_addr;
int phy_addr;
/*
@ -49,10 +52,10 @@ struct mv643xx_eth_platform_data {
int duplex;
/*
* Which RX/TX queues to use.
* How many RX/TX queues to use.
*/
int rx_queue_mask;
int tx_queue_mask;
int rx_queue_count;
int tx_queue_count;
/*
* Override default RX/TX queue sizes if nonzero.

33
include/linux/netdevice.h
View file

@ -11,7 +11,7 @@
* Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
* Corey Minyard <wf-rch!minyard@relay.EU.net>
* Donald J. Becker, <becker@cesdis.gsfc.nasa.gov>
* Alan Cox, <Alan.Cox@linux.org>
* Alan Cox, <alan@lxorguk.ukuu.org.uk>
* Bjorn Ekwall. <bj0rn@blox.se>
* Pekka Riikonen <priikone@poseidon.pspt.fi>
*
@ -42,6 +42,7 @@
#include <linux/workqueue.h>
#include <net/net_namespace.h>
#include <net/dsa.h>
struct vlan_group;
struct ethtool_ops;
@ -471,6 +472,8 @@ struct net_device
char name[IFNAMSIZ];
/* device name hash chain */
struct hlist_node name_hlist;
/* snmp alias */
char *ifalias;
/*
* I/O specific fields
@ -605,6 +608,9 @@ struct net_device
/* Protocol specific pointers */
#ifdef CONFIG_NET_DSA
void *dsa_ptr; /* dsa specific data */
#endif
void *atalk_ptr; /* AppleTalk link */
void *ip_ptr; /* IPv4 specific data */
void *dn_ptr; /* DECnet specific data */
@ -796,6 +802,26 @@ void dev_net_set(struct net_device *dev, struct net *net)
#endif
}
static inline bool netdev_uses_dsa_tags(struct net_device *dev)
{
#ifdef CONFIG_NET_DSA_TAG_DSA
if (dev->dsa_ptr != NULL)
return dsa_uses_dsa_tags(dev->dsa_ptr);
#endif
return 0;
}
static inline bool netdev_uses_trailer_tags(struct net_device *dev)
{
#ifdef CONFIG_NET_DSA_TAG_TRAILER
if (dev->dsa_ptr != NULL)
return dsa_uses_trailer_tags(dev->dsa_ptr);
#endif
return 0;
}
/**
* netdev_priv - access network device private data
* @dev: network device
@ -1223,7 +1249,8 @@ extern int dev_ioctl(struct net *net, unsigned int cmd, void __user *);
extern int dev_ethtool(struct net *net, struct ifreq *);
extern unsigned dev_get_flags(const struct net_device *);
extern int dev_change_flags(struct net_device *, unsigned);
extern int dev_change_name(struct net_device *, char *);
extern int dev_change_name(struct net_device *, const char *);
extern int dev_set_alias(struct net_device *, const char *, size_t);
extern int dev_change_net_namespace(struct net_device *,
struct net *, const char *);
extern int dev_set_mtu(struct net_device *, int);
@ -1667,7 +1694,7 @@ extern void dev_seq_stop(struct seq_file *seq, void *v);
extern int netdev_class_create_file(struct class_attribute *class_attr);
extern void netdev_class_remove_file(struct class_attribute *class_attr);
extern char *netdev_drivername(struct net_device *dev, char *buffer, int len);
extern char *netdev_drivername(const struct net_device *dev, char *buffer, int len);
extern void linkwatch_run_queue(void);

97
include/linux/netfilter.h
View file

@ -5,13 +5,11 @@
#include <linux/init.h>
#include <linux/skbuff.h>
#include <linux/net.h>
#include <linux/netdevice.h>
#include <linux/if.h>
#include <linux/in.h>
#include <linux/in6.h>
#include <linux/wait.h>
#include <linux/list.h>
#include <net/net_namespace.h>
#endif
#include <linux/types.h>
#include <linux/compiler.h>
@ -52,6 +50,16 @@ enum nf_inet_hooks {
NF_INET_NUMHOOKS
};
enum {
NFPROTO_UNSPEC = 0,
NFPROTO_IPV4 = 2,
NFPROTO_ARP = 3,
NFPROTO_BRIDGE = 7,
NFPROTO_IPV6 = 10,
NFPROTO_DECNET = 12,
NFPROTO_NUMPROTO,
};
union nf_inet_addr {
__u32 all[4];
__be32 ip;
@ -92,8 +100,8 @@ struct nf_hook_ops
/* User fills in from here down. */
nf_hookfn *hook;
struct module *owner;
int pf;
int hooknum;
u_int8_t pf;
unsigned int hooknum;
/* Hooks are ordered in ascending priority. */
int priority;
};
@ -102,7 +110,7 @@ struct nf_sockopt_ops
{
struct list_head list;
int pf;
u_int8_t pf;
/* Non-inclusive ranges: use 0/0/NULL to never get called. */
int set_optmin;
@ -138,9 +146,9 @@ extern struct ctl_path nf_net_netfilter_sysctl_path[];
extern struct ctl_path nf_net_ipv4_netfilter_sysctl_path[];
#endif /* CONFIG_SYSCTL */
extern struct list_head nf_hooks[NPROTO][NF_MAX_HOOKS];
extern struct list_head nf_hooks[NFPROTO_NUMPROTO][NF_MAX_HOOKS];
int nf_hook_slow(int pf, unsigned int hook, struct sk_buff *skb,
int nf_hook_slow(u_int8_t pf, unsigned int hook, struct sk_buff *skb,
struct net_device *indev, struct net_device *outdev,
int (*okfn)(struct sk_buff *), int thresh);
@ -151,7 +159,7 @@ int nf_hook_slow(int pf, unsigned int hook, struct sk_buff *skb,
* okfn must be invoked by the caller in this case. Any other return
* value indicates the packet has been consumed by the hook.
*/
static inline int nf_hook_thresh(int pf, unsigned int hook,
static inline int nf_hook_thresh(u_int8_t pf, unsigned int hook,
struct sk_buff *skb,
struct net_device *indev,
struct net_device *outdev,
@ -167,7 +175,7 @@ static inline int nf_hook_thresh(int pf, unsigned int hook,
return nf_hook_slow(pf, hook, skb, indev, outdev, okfn, thresh);
}
static inline int nf_hook(int pf, unsigned int hook, struct sk_buff *skb,
static inline int nf_hook(u_int8_t pf, unsigned int hook, struct sk_buff *skb,
struct net_device *indev, struct net_device *outdev,
int (*okfn)(struct sk_buff *))
{
@ -212,14 +220,14 @@ __ret;})
NF_HOOK_THRESH(pf, hook, skb, indev, outdev, okfn, INT_MIN)
/* Call setsockopt() */
int nf_setsockopt(struct sock *sk, int pf, int optval, char __user *opt,
int nf_setsockopt(struct sock *sk, u_int8_t pf, int optval, char __user *opt,
int len);
int nf_getsockopt(struct sock *sk, int pf, int optval, char __user *opt,
int nf_getsockopt(struct sock *sk, u_int8_t pf, int optval, char __user *opt,
int *len);
int compat_nf_setsockopt(struct sock *sk, int pf, int optval,
int compat_nf_setsockopt(struct sock *sk, u_int8_t pf, int optval,
char __user *opt, int len);
int compat_nf_getsockopt(struct sock *sk, int pf, int optval,
int compat_nf_getsockopt(struct sock *sk, u_int8_t pf, int optval,
char __user *opt, int *len);
/* Call this before modifying an existing packet: ensures it is
@ -247,7 +255,7 @@ struct nf_afinfo {
int route_key_size;
};
extern const struct nf_afinfo *nf_afinfo[NPROTO];
extern const struct nf_afinfo *nf_afinfo[NFPROTO_NUMPROTO];
static inline const struct nf_afinfo *nf_get_afinfo(unsigned short family)
{
return rcu_dereference(nf_afinfo[family]);
@ -292,7 +300,7 @@ extern void nf_unregister_afinfo(const struct nf_afinfo *afinfo);
extern void (*ip_nat_decode_session)(struct sk_buff *, struct flowi *);
static inline void
nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, int family)
nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, u_int8_t family)
{
#ifdef CONFIG_NF_NAT_NEEDED
void (*decodefn)(struct sk_buff *, struct flowi *);
@ -315,7 +323,7 @@ extern struct proc_dir_entry *proc_net_netfilter;
#else /* !CONFIG_NETFILTER */
#define NF_HOOK(pf, hook, skb, indev, outdev, okfn) (okfn)(skb)
#define NF_HOOK_COND(pf, hook, skb, indev, outdev, okfn, cond) (okfn)(skb)
static inline int nf_hook_thresh(int pf, unsigned int hook,
static inline int nf_hook_thresh(u_int8_t pf, unsigned int hook,
struct sk_buff *skb,
struct net_device *indev,
struct net_device *outdev,
@ -324,7 +332,7 @@ static inline int nf_hook_thresh(int pf, unsigned int hook,
{
return okfn(skb);
}
static inline int nf_hook(int pf, unsigned int hook, struct sk_buff *skb,
static inline int nf_hook(u_int8_t pf, unsigned int hook, struct sk_buff *skb,
struct net_device *indev, struct net_device *outdev,
int (*okfn)(struct sk_buff *))
{
@ -332,7 +340,9 @@ static inline int nf_hook(int pf, unsigned int hook, struct sk_buff *skb,
}
struct flowi;
static inline void
nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, int family) {}
nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, u_int8_t family)
{
}
#endif /*CONFIG_NETFILTER*/
#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
@ -343,56 +353,5 @@ extern void (*nf_ct_destroy)(struct nf_conntrack *);
static inline void nf_ct_attach(struct sk_buff *new, struct sk_buff *skb) {}
#endif
static inline struct net *nf_pre_routing_net(const struct net_device *in,
const struct net_device *out)
{
#ifdef CONFIG_NET_NS
return in->nd_net;
#else
return &init_net;
#endif
}
static inline struct net *nf_local_in_net(const struct net_device *in,
const struct net_device *out)
{
#ifdef CONFIG_NET_NS
return in->nd_net;
#else
return &init_net;
#endif
}
static inline struct net *nf_forward_net(const struct net_device *in,
const struct net_device *out)
{
#ifdef CONFIG_NET_NS
BUG_ON(in->nd_net != out->nd_net);
return in->nd_net;
#else
return &init_net;
#endif
}
static inline struct net *nf_local_out_net(const struct net_device *in,
const struct net_device *out)
{
#ifdef CONFIG_NET_NS
return out->nd_net;
#else
return &init_net;
#endif
}
static inline struct net *nf_post_routing_net(const struct net_device *in,
const struct net_device *out)
{
#ifdef CONFIG_NET_NS
return out->nd_net;
#else
return &init_net;
#endif
}
#endif /*__KERNEL__*/
#endif /*__LINUX_NETFILTER_H*/

1
include/linux/netfilter/Kbuild
View file

@ -32,6 +32,7 @@ header-y += xt_owner.h
header-y += xt_pkttype.h
header-y += xt_rateest.h
header-y += xt_realm.h
header-y += xt_recent.h
header-y += xt_sctp.h
header-y += xt_state.h
header-y += xt_statistic.h

2
include/linux/netfilter/nf_conntrack_proto_gre.h
View file

@ -87,7 +87,7 @@ int nf_ct_gre_keymap_add(struct nf_conn *ct, enum ip_conntrack_dir dir,
/* delete keymap entries */
void nf_ct_gre_keymap_destroy(struct nf_conn *ct);
extern void nf_ct_gre_keymap_flush(void);
extern void nf_ct_gre_keymap_flush(struct net *net);
extern void nf_nat_need_gre(void);
#endif /* __KERNEL__ */

161
include/linux/netfilter/x_tables.h
View file

@ -173,6 +173,98 @@ struct xt_counters_info
#include <linux/netdevice.h>
/**
* struct xt_match_param - parameters for match extensions' match functions
*
* @in: input netdevice
* @out: output netdevice
* @match: struct xt_match through which this function was invoked
* @matchinfo: per-match data
* @fragoff: packet is a fragment, this is the data offset
* @thoff: position of transport header relative to skb->data
* @hotdrop: drop packet if we had inspection problems
* @family: Actual NFPROTO_* through which the function is invoked
* (helpful when match->family == NFPROTO_UNSPEC)
*/
struct xt_match_param {
const struct net_device *in, *out;
const struct xt_match *match;
const void *matchinfo;
int fragoff;
unsigned int thoff;
bool *hotdrop;
u_int8_t family;
};
/**
* struct xt_mtchk_param - parameters for match extensions'
* checkentry functions
*
* @table: table the rule is tried to be inserted into
* @entryinfo: the family-specific rule data
* (struct ipt_ip, ip6t_ip, ebt_entry)
* @match: struct xt_match through which this function was invoked
* @matchinfo: per-match data
* @hook_mask: via which hooks the new rule is reachable
*/
struct xt_mtchk_param {
const char *table;
const void *entryinfo;
const struct xt_match *match;
void *matchinfo;
unsigned int hook_mask;
u_int8_t family;
};
/* Match destructor parameters */
struct xt_mtdtor_param {
const struct xt_match *match;
void *matchinfo;
u_int8_t family;
};
/**
* struct xt_target_param - parameters for target extensions' target functions
*
* @hooknum: hook through which this target was invoked
* @target: struct xt_target through which this function was invoked
* @targinfo: per-target data
*
* Other fields see above.
*/
struct xt_target_param {
const struct net_device *in, *out;
unsigned int hooknum;
const struct xt_target *target;
const void *targinfo;
u_int8_t family;
};
/**
* struct xt_tgchk_param - parameters for target extensions'
* checkentry functions
*
* @entryinfo: the family-specific rule data
* (struct ipt_entry, ip6t_entry, arpt_entry, ebt_entry)
*
* Other fields see above.
*/
struct xt_tgchk_param {
const char *table;
void *entryinfo;
const struct xt_target *target;
void *targinfo;
unsigned int hook_mask;
u_int8_t family;
};
/* Target destructor parameters */
struct xt_tgdtor_param {
const struct xt_target *target;
void *targinfo;
u_int8_t family;
};
struct xt_match
{
struct list_head list;
@ -185,24 +277,13 @@ struct xt_match
non-linear skb, using skb_header_pointer and
skb_ip_make_writable. */
bool (*match)(const struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
const struct xt_match *match,
const void *matchinfo,
int offset,
unsigned int protoff,
bool *hotdrop);
const struct xt_match_param *);
/* Called when user tries to insert an entry of this type. */
/* Should return true or false. */
bool (*checkentry)(const char *tablename,
const void *ip,
const struct xt_match *match,
void *matchinfo,
unsigned int hook_mask);
bool (*checkentry)(const struct xt_mtchk_param *);
/* Called when entry of this type deleted. */
void (*destroy)(const struct xt_match *match, void *matchinfo);
void (*destroy)(const struct xt_mtdtor_param *);
/* Called when userspace align differs from kernel space one */
void (*compat_from_user)(void *dst, void *src);
@ -235,24 +316,16 @@ struct xt_target
must now handle non-linear skbs, using skb_copy_bits and
skb_ip_make_writable. */
unsigned int (*target)(struct sk_buff *skb,
const struct net_device *in,
const struct net_device *out,
unsigned int hooknum,
const struct xt_target *target,
const void *targinfo);
const struct xt_target_param *);
/* Called when user tries to insert an entry of this type:
hook_mask is a bitmask of hooks from which it can be
called. */
/* Should return true or false. */
bool (*checkentry)(const char *tablename,
const void *entry,
const struct xt_target *target,
void *targinfo,
unsigned int hook_mask);
bool (*checkentry)(const struct xt_tgchk_param *);
/* Called when entry of this type deleted. */
void (*destroy)(const struct xt_target *target, void *targinfo);
void (*destroy)(const struct xt_tgdtor_param *);
/* Called when userspace align differs from kernel space one */
void (*compat_from_user)(void *dst, void *src);
@ -292,7 +365,7 @@ struct xt_table
/* Set this to THIS_MODULE if you are a module, otherwise NULL */
struct module *me;
int af; /* address/protocol family */
u_int8_t af; /* address/protocol family */
};
#include <linux/netfilter_ipv4.h>
@ -328,12 +401,10 @@ extern void xt_unregister_match(struct xt_match *target);
extern int xt_register_matches(struct xt_match *match, unsigned int n);
extern void xt_unregister_matches(struct xt_match *match, unsigned int n);
extern int xt_check_match(const struct xt_match *match, unsigned short family,
unsigned int size, const char *table, unsigned int hook,
unsigned short proto, int inv_proto);
extern int xt_check_target(const struct xt_target *target, unsigned short family,
unsigned int size, const char *table, unsigned int hook,
unsigned short proto, int inv_proto);
extern int xt_check_match(struct xt_mtchk_param *,
unsigned int size, u_int8_t proto, bool inv_proto);
extern int xt_check_target(struct xt_tgchk_param *,
unsigned int size, u_int8_t proto, bool inv_proto);
extern struct xt_table *xt_register_table(struct net *net,
struct xt_table *table,
@ -346,19 +417,19 @@ extern struct xt_table_info *xt_replace_table(struct xt_table *table,
struct xt_table_info *newinfo,
int *error);
extern struct xt_match *xt_find_match(int af, const char *name, u8 revision);
extern struct xt_target *xt_find_target(int af, const char *name, u8 revision);
extern struct xt_target *xt_request_find_target(int af, const char *name,
extern struct xt_match *xt_find_match(u8 af, const char *name, u8 revision);
extern struct xt_target *xt_find_target(u8 af, const char *name, u8 revision);
extern struct xt_target *xt_request_find_target(u8 af, const char *name,
u8 revision);
extern int xt_find_revision(int af, const char *name, u8 revision, int target,
int *err);
extern int xt_find_revision(u8 af, const char *name, u8 revision,
int target, int *err);
extern struct xt_table *xt_find_table_lock(struct net *net, int af,
extern struct xt_table *xt_find_table_lock(struct net *net, u_int8_t af,
const char *name);
extern void xt_table_unlock(struct xt_table *t);
extern int xt_proto_init(struct net *net, int af);
extern void xt_proto_fini(struct net *net, int af);
extern int xt_proto_init(struct net *net, u_int8_t af);
extern void xt_proto_fini(struct net *net, u_int8_t af);
extern struct xt_table_info *xt_alloc_table_info(unsigned int size);
extern void xt_free_table_info(struct xt_table_info *info);
@ -423,12 +494,12 @@ struct compat_xt_counters_info
#define COMPAT_XT_ALIGN(s) (((s) + (__alignof__(struct compat_xt_counters)-1)) \
& ~(__alignof__(struct compat_xt_counters)-1))
extern void xt_compat_lock(int af);
extern void xt_compat_unlock(int af);
extern void xt_compat_lock(u_int8_t af);
extern void xt_compat_unlock(u_int8_t af);
extern int xt_compat_add_offset(int af, unsigned int offset, short delta);
extern void xt_compat_flush_offsets(int af);
extern short xt_compat_calc_jump(int af, unsigned int offset);
extern int xt_compat_add_offset(u_int8_t af, unsigned int offset, short delta);
extern void xt_compat_flush_offsets(u_int8_t af);
extern short xt_compat_calc_jump(u_int8_t af, unsigned int offset);
extern int xt_compat_match_offset(const struct xt_match *match);
extern int xt_compat_match_from_user(struct xt_entry_match *m,

14
include/linux/netfilter/xt_TPROXY.h Normal file
View file

@ -0,0 +1,14 @@
#ifndef _XT_TPROXY_H_target
#define _XT_TPROXY_H_target
/* TPROXY target is capable of marking the packet to perform
* redirection. We can get rid of that whenever we get support for
* mutliple targets in the same rule. */
struct xt_tproxy_target_info {
u_int32_t mark_mask;
u_int32_t mark_value;
__be32 laddr;
__be16 lport;
};
#endif /* _XT_TPROXY_H_target */

26
include/linux/netfilter/xt_recent.h Normal file
View file

@ -0,0 +1,26 @@
#ifndef _LINUX_NETFILTER_XT_RECENT_H
#define _LINUX_NETFILTER_XT_RECENT_H 1
enum {
XT_RECENT_CHECK = 1 << 0,
XT_RECENT_SET = 1 << 1,
XT_RECENT_UPDATE = 1 << 2,
XT_RECENT_REMOVE = 1 << 3,
XT_RECENT_TTL = 1 << 4,
XT_RECENT_SOURCE = 0,
XT_RECENT_DEST = 1,
XT_RECENT_NAME_LEN = 200,
};
struct xt_recent_mtinfo {
u_int32_t seconds;
u_int32_t hit_count;
u_int8_t check_set;
u_int8_t invert;
char name[XT_RECENT_NAME_LEN];
u_int8_t side;
};
#endif /* _LINUX_NETFILTER_XT_RECENT_H */

76
include/linux/netfilter_bridge/ebtables.h
View file

@ -31,6 +31,9 @@
* The 4 lsb are more than enough to store the verdict. */
#define EBT_VERDICT_BITS 0x0000000F
struct xt_match;
struct xt_target;
struct ebt_counter
{
uint64_t pcnt;
@ -121,7 +124,7 @@ struct ebt_entry_match
{
union {
char name[EBT_FUNCTION_MAXNAMELEN];
struct ebt_match *match;
struct xt_match *match;
} u;
/* size of data */
unsigned int match_size;
@ -132,7 +135,7 @@ struct ebt_entry_watcher
{
union {
char name[EBT_FUNCTION_MAXNAMELEN];
struct ebt_watcher *watcher;
struct xt_target *watcher;
} u;
/* size of data */
unsigned int watcher_size;
@ -143,7 +146,7 @@ struct ebt_entry_target
{
union {
char name[EBT_FUNCTION_MAXNAMELEN];
struct ebt_target *target;
struct xt_target *target;
} u;
/* size of data */
unsigned int target_size;
@ -207,14 +210,17 @@ struct ebt_match
{
struct list_head list;
const char name[EBT_FUNCTION_MAXNAMELEN];
/* 0 == it matches */
int (*match)(const struct sk_buff *skb, const struct net_device *in,
const struct net_device *out, const void *matchdata,
unsigned int datalen);
/* 0 == let it in */
int (*check)(const char *tablename, unsigned int hookmask,
const struct ebt_entry *e, void *matchdata, unsigned int datalen);
void (*destroy)(void *matchdata, unsigned int datalen);
bool (*match)(const struct sk_buff *skb, const struct net_device *in,
const struct net_device *out, const struct xt_match *match,
const void *matchinfo, int offset, unsigned int protoff,
bool *hotdrop);
bool (*checkentry)(const char *table, const void *entry,
const struct xt_match *match, void *matchinfo,
unsigned int hook_mask);
void (*destroy)(const struct xt_match *match, void *matchinfo);
unsigned int matchsize;
u_int8_t revision;
u_int8_t family;
struct module *me;
};
@ -222,13 +228,17 @@ struct ebt_watcher
{
struct list_head list;
const char name[EBT_FUNCTION_MAXNAMELEN];
void (*watcher)(const struct sk_buff *skb, unsigned int hooknr,
const struct net_device *in, const struct net_device *out,
const void *watcherdata, unsigned int datalen);
/* 0 == let it in */
int (*check)(const char *tablename, unsigned int hookmask,
const struct ebt_entry *e, void *watcherdata, unsigned int datalen);
void (*destroy)(void *watcherdata, unsigned int datalen);
unsigned int (*target)(struct sk_buff *skb,
const struct net_device *in, const struct net_device *out,
unsigned int hook_num, const struct xt_target *target,
const void *targinfo);
bool (*checkentry)(const char *table, const void *entry,
const struct xt_target *target, void *targinfo,
unsigned int hook_mask);
void (*destroy)(const struct xt_target *target, void *targinfo);
unsigned int targetsize;
u_int8_t revision;
u_int8_t family;
struct module *me;
};
@ -236,14 +246,18 @@ struct ebt_target
{
struct list_head list;
const char name[EBT_FUNCTION_MAXNAMELEN];
/* returns one of the standard verdicts */
int (*target)(struct sk_buff *skb, unsigned int hooknr,
const struct net_device *in, const struct net_device *out,
const void *targetdata, unsigned int datalen);
/* 0 == let it in */
int (*check)(const char *tablename, unsigned int hookmask,
const struct ebt_entry *e, void *targetdata, unsigned int datalen);
void (*destroy)(void *targetdata, unsigned int datalen);
/* returns one of the standard EBT_* verdicts */
unsigned int (*target)(struct sk_buff *skb,
const struct net_device *in, const struct net_device *out,
unsigned int hook_num, const struct xt_target *target,
const void *targinfo);
bool (*checkentry)(const char *table, const void *entry,
const struct xt_target *target, void *targinfo,
unsigned int hook_mask);
void (*destroy)(const struct xt_target *target, void *targinfo);
unsigned int targetsize;
u_int8_t revision;
u_int8_t family;
struct module *me;
};
@ -288,12 +302,6 @@ struct ebt_table
~(__alignof__(struct ebt_replace)-1))
extern int ebt_register_table(struct ebt_table *table);
extern void ebt_unregister_table(struct ebt_table *table);
extern int ebt_register_match(struct ebt_match *match);
extern void ebt_unregister_match(struct ebt_match *match);
extern int ebt_register_watcher(struct ebt_watcher *watcher);
extern void ebt_unregister_watcher(struct ebt_watcher *watcher);
extern int ebt_register_target(struct ebt_target *target);
extern void ebt_unregister_target(struct ebt_target *target);
extern unsigned int ebt_do_table(unsigned int hook, struct sk_buff *skb,
const struct net_device *in, const struct net_device *out,
struct ebt_table *table);
@ -302,9 +310,9 @@ extern unsigned int ebt_do_table(unsigned int hook, struct sk_buff *skb,
#define FWINV(bool,invflg) ((bool) ^ !!(info->invflags & invflg))
/* True if the hook mask denotes that the rule is in a base chain,
* used in the check() functions */
#define BASE_CHAIN (hookmask & (1 << NF_BR_NUMHOOKS))
#define BASE_CHAIN (par->hook_mask & (1 << NF_BR_NUMHOOKS))
/* Clear the bit in the hook mask that tells if the rule is on a base chain */
#define CLEAR_BASE_CHAIN_BIT (hookmask &= ~(1 << NF_BR_NUMHOOKS))
#define CLEAR_BASE_CHAIN_BIT (par->hook_mask &= ~(1 << NF_BR_NUMHOOKS))
/* True if the target is not a standard target */
#define INVALID_TARGET (info->target < -NUM_STANDARD_TARGETS || info->target >= 0)

28
include/linux/netfilter_ipv4/ipt_recent.h
View file

@ -1,27 +1,21 @@
#ifndef _IPT_RECENT_H
#define _IPT_RECENT_H
#define RECENT_NAME "ipt_recent"
#define RECENT_VER "v0.3.1"
#include <linux/netfilter/xt_recent.h>
#define IPT_RECENT_CHECK 1
#define IPT_RECENT_SET 2
#define IPT_RECENT_UPDATE 4
#define IPT_RECENT_REMOVE 8
#define IPT_RECENT_TTL 16
#define ipt_recent_info xt_recent_mtinfo
#define IPT_RECENT_SOURCE 0
#define IPT_RECENT_DEST 1
enum {
IPT_RECENT_CHECK = XT_RECENT_CHECK,
IPT_RECENT_SET = XT_RECENT_SET,
IPT_RECENT_UPDATE = XT_RECENT_UPDATE,
IPT_RECENT_REMOVE = XT_RECENT_REMOVE,
IPT_RECENT_TTL = XT_RECENT_TTL,
#define IPT_RECENT_NAME_LEN 200
IPT_RECENT_SOURCE = XT_RECENT_SOURCE,
IPT_RECENT_DEST = XT_RECENT_DEST,
struct ipt_recent_info {
u_int32_t seconds;
u_int32_t hit_count;
u_int8_t check_set;
u_int8_t invert;
char name[IPT_RECENT_NAME_LEN];
u_int8_t side;
IPT_RECENT_NAME_LEN = XT_RECENT_NAME_LEN,
};
#endif /*_IPT_RECENT_H*/

3
include/linux/nfsd/nfsd.h
View file

@ -38,6 +38,7 @@
#define NFSD_MAY_LOCK 32
#define NFSD_MAY_OWNER_OVERRIDE 64
#define NFSD_MAY_LOCAL_ACCESS 128 /* IRIX doing local access check on device special file*/
#define NFSD_MAY_BYPASS_GSS_ON_ROOT 256
#define NFSD_MAY_CREATE (NFSD_MAY_EXEC|NFSD_MAY_WRITE)
#define NFSD_MAY_REMOVE (NFSD_MAY_EXEC|NFSD_MAY_WRITE|NFSD_MAY_TRUNC)
@ -125,7 +126,7 @@ int nfsd_truncate(struct svc_rqst *, struct svc_fh *,
__be32 nfsd_readdir(struct svc_rqst *, struct svc_fh *,
loff_t *, struct readdir_cd *, filldir_t);
__be32 nfsd_statfs(struct svc_rqst *, struct svc_fh *,
struct kstatfs *);
struct kstatfs *, int access);
int nfsd_notify_change(struct inode *, struct iattr *);
__be32 nfsd_permission(struct svc_rqst *, struct svc_export *,

133
include/linux/nl80211.h
View file

@ -89,6 +89,22 @@
* @NL80211_CMD_DEL_PATH: Remove a mesh path identified by %NL80211_ATTR_MAC
* or, if no MAC address given, all mesh paths, on the interface identified
* by %NL80211_ATTR_IFINDEX.
* @NL80211_CMD_SET_BSS: Set BSS attributes for BSS identified by
* %NL80211_ATTR_IFINDEX.
*
* @NL80211_CMD_SET_REG: Set current regulatory domain. CRDA sends this command
* after being queried by the kernel. CRDA replies by sending a regulatory
* domain structure which consists of %NL80211_ATTR_REG_ALPHA set to our
* current alpha2 if it found a match. It also provides
* NL80211_ATTR_REG_RULE_FLAGS, and a set of regulatory rules. Each
* regulatory rule is a nested set of attributes given by
* %NL80211_ATTR_REG_RULE_FREQ_[START|END] and
* %NL80211_ATTR_FREQ_RANGE_MAX_BW with an attached power rule given by
* %NL80211_ATTR_REG_RULE_POWER_MAX_ANT_GAIN and
* %NL80211_ATTR_REG_RULE_POWER_MAX_EIRP.
* @NL80211_CMD_REQ_SET_REG: ask the wireless core to set the regulatory domain
* to the the specified ISO/IEC 3166-1 alpha2 country code. The core will
* store this as a valid request and then query userspace for it.
*
* @NL80211_CMD_MAX: highest used command number
* @__NL80211_CMD_AFTER_LAST: internal use
@ -127,13 +143,23 @@ enum nl80211_commands {
NL80211_CMD_NEW_MPATH,
NL80211_CMD_DEL_MPATH,
/* add commands here */
NL80211_CMD_SET_BSS,
NL80211_CMD_SET_REG,
NL80211_CMD_REQ_SET_REG,
/* add new commands above here */
/* used to define NL80211_CMD_MAX below */
__NL80211_CMD_AFTER_LAST,
NL80211_CMD_MAX = __NL80211_CMD_AFTER_LAST - 1
};
/*
* Allow user space programs to use #ifdef on new commands by defining them
* here
*/
#define NL80211_CMD_SET_BSS NL80211_CMD_SET_BSS
/**
* enum nl80211_attrs - nl80211 netlink attributes
@ -188,10 +214,34 @@ enum nl80211_commands {
* info given for %NL80211_CMD_GET_MPATH, nested attribute described at
* &enum nl80211_mpath_info.
*
*
* @NL80211_ATTR_MNTR_FLAGS: flags, nested element with NLA_FLAG attributes of
* &enum nl80211_mntr_flags.
*
* @NL80211_ATTR_REG_ALPHA2: an ISO-3166-alpha2 country code for which the
* current regulatory domain should be set to or is already set to.
* For example, 'CR', for Costa Rica. This attribute is used by the kernel
* to query the CRDA to retrieve one regulatory domain. This attribute can
* also be used by userspace to query the kernel for the currently set
* regulatory domain. We chose an alpha2 as that is also used by the
* IEEE-802.11d country information element to identify a country.
* Users can also simply ask the wireless core to set regulatory domain
* to a specific alpha2.
* @NL80211_ATTR_REG_RULES: a nested array of regulatory domain regulatory
* rules.
*
* @NL80211_ATTR_BSS_CTS_PROT: whether CTS protection is enabled (u8, 0 or 1)
* @NL80211_ATTR_BSS_SHORT_PREAMBLE: whether short preamble is enabled
* (u8, 0 or 1)
* @NL80211_ATTR_BSS_SHORT_SLOT_TIME: whether short slot time enabled
* (u8, 0 or 1)
*
* @NL80211_ATTR_HT_CAPABILITY: HT Capability information element (from
* association request when used with NL80211_CMD_NEW_STATION)
*
* @NL80211_ATTR_SUPPORTED_IFTYPES: nested attribute containing all
* supported interface types, each a flag attribute with the number
* of the interface mode.
*
* @NL80211_ATTR_MAX: highest attribute number currently defined
* @__NL80211_ATTR_AFTER_LAST: internal use
*/
@ -235,16 +285,35 @@ enum nl80211_attrs {
NL80211_ATTR_MPATH_NEXT_HOP,
NL80211_ATTR_MPATH_INFO,
NL80211_ATTR_BSS_CTS_PROT,
NL80211_ATTR_BSS_SHORT_PREAMBLE,
NL80211_ATTR_BSS_SHORT_SLOT_TIME,
NL80211_ATTR_HT_CAPABILITY,
NL80211_ATTR_SUPPORTED_IFTYPES,
NL80211_ATTR_REG_ALPHA2,
NL80211_ATTR_REG_RULES,
/* add attributes here, update the policy in nl80211.c */
__NL80211_ATTR_AFTER_LAST,
NL80211_ATTR_MAX = __NL80211_ATTR_AFTER_LAST - 1
};
/*
* Allow user space programs to use #ifdef on new attributes by defining them
* here
*/
#define NL80211_ATTR_HT_CAPABILITY NL80211_ATTR_HT_CAPABILITY
#define NL80211_MAX_SUPP_RATES 32
#define NL80211_MAX_SUPP_REG_RULES 32
#define NL80211_TKIP_DATA_OFFSET_ENCR_KEY 0
#define NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY 16
#define NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY 24
#define NL80211_HT_CAPABILITY_LEN 26
/**
* enum nl80211_iftype - (virtual) interface types
@ -435,6 +504,66 @@ enum nl80211_bitrate_attr {
NL80211_BITRATE_ATTR_MAX = __NL80211_BITRATE_ATTR_AFTER_LAST - 1
};
/**
* enum nl80211_reg_rule_attr - regulatory rule attributes
* @NL80211_ATTR_REG_RULE_FLAGS: a set of flags which specify additional
* considerations for a given frequency range. These are the
* &enum nl80211_reg_rule_flags.
* @NL80211_ATTR_FREQ_RANGE_START: starting frequencry for the regulatory
* rule in KHz. This is not a center of frequency but an actual regulatory
* band edge.
* @NL80211_ATTR_FREQ_RANGE_END: ending frequency for the regulatory rule
* in KHz. This is not a center a frequency but an actual regulatory
* band edge.
* @NL80211_ATTR_FREQ_RANGE_MAX_BW: maximum allowed bandwidth for this
* frequency range, in KHz.
* @NL80211_ATTR_POWER_RULE_MAX_ANT_GAIN: the maximum allowed antenna gain
* for a given frequency range. The value is in mBi (100 * dBi).
* If you don't have one then don't send this.
* @NL80211_ATTR_POWER_RULE_MAX_EIRP: the maximum allowed EIRP for
* a given frequency range. The value is in mBm (100 * dBm).
*/
enum nl80211_reg_rule_attr {
__NL80211_REG_RULE_ATTR_INVALID,
NL80211_ATTR_REG_RULE_FLAGS,
NL80211_ATTR_FREQ_RANGE_START,
NL80211_ATTR_FREQ_RANGE_END,
NL80211_ATTR_FREQ_RANGE_MAX_BW,
NL80211_ATTR_POWER_RULE_MAX_ANT_GAIN,
NL80211_ATTR_POWER_RULE_MAX_EIRP,
/* keep last */
__NL80211_REG_RULE_ATTR_AFTER_LAST,
NL80211_REG_RULE_ATTR_MAX = __NL80211_REG_RULE_ATTR_AFTER_LAST - 1
};
/**
* enum nl80211_reg_rule_flags - regulatory rule flags
*
* @NL80211_RRF_NO_OFDM: OFDM modulation not allowed
* @NL80211_RRF_NO_CCK: CCK modulation not allowed
* @NL80211_RRF_NO_INDOOR: indoor operation not allowed
* @NL80211_RRF_NO_OUTDOOR: outdoor operation not allowed
* @NL80211_RRF_DFS: DFS support is required to be used
* @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
* @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
* @NL80211_RRF_PASSIVE_SCAN: passive scan is required
* @NL80211_RRF_NO_IBSS: no IBSS is allowed
*/
enum nl80211_reg_rule_flags {
NL80211_RRF_NO_OFDM = 1<<0,
NL80211_RRF_NO_CCK = 1<<1,
NL80211_RRF_NO_INDOOR = 1<<2,
NL80211_RRF_NO_OUTDOOR = 1<<3,
NL80211_RRF_DFS = 1<<4,
NL80211_RRF_PTP_ONLY = 1<<5,
NL80211_RRF_PTMP_ONLY = 1<<6,
NL80211_RRF_PASSIVE_SCAN = 1<<7,
NL80211_RRF_NO_IBSS = 1<<8,
};
/**
* enum nl80211_mntr_flags - monitor configuration flags
*

10
include/linux/notifier.h
View file

@ -213,9 +213,16 @@ static inline int notifier_to_errno(int ret)
#define CPU_DOWN_FAILED 0x0006 /* CPU (unsigned)v NOT going down */
#define CPU_DEAD 0x0007 /* CPU (unsigned)v dead */
#define CPU_DYING 0x0008 /* CPU (unsigned)v not running any task,
* not handling interrupts, soon dead */
* not handling interrupts, soon dead.
* Called on the dying cpu, interrupts
* are already disabled. Must not
* sleep, must not fail */
#define CPU_POST_DEAD 0x0009 /* CPU (unsigned)v dead, cpu_hotplug
* lock is dropped */
#define CPU_STARTING 0x000A /* CPU (unsigned)v soon running.
* Called on the new cpu, just before
* enabling interrupts. Must not sleep,
* must not fail */
/* Used for CPU hotplug events occuring while tasks are frozen due to a suspend
* operation in progress
@ -229,6 +236,7 @@ static inline int notifier_to_errno(int ret)
#define CPU_DOWN_FAILED_FROZEN (CPU_DOWN_FAILED | CPU_TASKS_FROZEN)
#define CPU_DEAD_FROZEN (CPU_DEAD | CPU_TASKS_FROZEN)
#define CPU_DYING_FROZEN (CPU_DYING | CPU_TASKS_FROZEN)
#define CPU_STARTING_FROZEN (CPU_STARTING | CPU_TASKS_FROZEN)
/* Hibernation and suspend events */
#define PM_HIBERNATION_PREPARE 0x0001 /* Going to hibernate */

2
include/linux/oprofile.h
View file

@ -36,6 +36,8 @@
#define XEN_ENTER_SWITCH_CODE 10
#define SPU_PROFILING_CODE 11
#define SPU_CTX_SWITCH_CODE 12
#define IBS_FETCH_CODE 13
#define IBS_OP_CODE 14
struct super_block;
struct dentry;

2
include/linux/parser.h
View file

@ -25,7 +25,7 @@ typedef struct {
char *to;
} substring_t;
int match_token(char *, match_table_t table, substring_t args[]);
int match_token(char *, const match_table_t table, substring_t args[]);
int match_int(substring_t *, int *result);
int match_octal(substring_t *, int *result);
int match_hex(substring_t *, int *result);

8
include/linux/pci.h
View file

@ -534,7 +534,7 @@ extern void pci_sort_breadthfirst(void);
#ifdef CONFIG_PCI_LEGACY
struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
unsigned int device,
const struct pci_dev *from);
struct pci_dev *from);
struct pci_dev __deprecated *pci_find_slot(unsigned int bus,
unsigned int devfn);
#endif /* CONFIG_PCI_LEGACY */
@ -550,7 +550,7 @@ struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
struct pci_dev *from);
struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
unsigned int ss_vendor, unsigned int ss_device,
const struct pci_dev *from);
struct pci_dev *from);
struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
@ -816,7 +816,7 @@ _PCI_NOP_ALL(write,)
static inline struct pci_dev *pci_find_device(unsigned int vendor,
unsigned int device,
const struct pci_dev *from)
struct pci_dev *from)
{
return NULL;
}
@ -838,7 +838,7 @@ static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
unsigned int device,
unsigned int ss_vendor,
unsigned int ss_device,
const struct pci_dev *from)
struct pci_dev *from)
{
return NULL;
}

27
include/linux/pci_ids.h
View file

@ -497,6 +497,16 @@
#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP 0x1101
#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL 0x1102
#define PCI_DEVICE_ID_AMD_K8_NB_MISC 0x1103
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
#define PCI_DEVICE_ID_AMD_10H_NB_MAP 0x1201
#define PCI_DEVICE_ID_AMD_10H_NB_DRAM 0x1202
#define PCI_DEVICE_ID_AMD_10H_NB_MISC 0x1203
#define PCI_DEVICE_ID_AMD_10H_NB_LINK 0x1204
#define PCI_DEVICE_ID_AMD_11H_NB_HT 0x1300
#define PCI_DEVICE_ID_AMD_11H_NB_MAP 0x1301
#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302
#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
#define PCI_DEVICE_ID_AMD_SCSI 0x2020
@ -1411,6 +1421,8 @@
#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013
#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014
#define PCI_VENDOR_ID_CISCO 0x1137
#define PCI_VENDOR_ID_ZIATECH 0x1138
#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550
@ -1521,7 +1533,9 @@
#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480
#define PCI_DEVICE_ID_MARVELL_CAFE_SD 0x4101
#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND 0x4100
#define PCI_DEVICE_ID_MARVELL_88ALP01_SD 0x4101
#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC 0x4102
#define PCI_VENDOR_ID_V3 0x11b0
#define PCI_DEVICE_ID_V3_V960 0x0001
@ -2213,6 +2227,7 @@
#define PCI_VENDOR_ID_ATTANSIC 0x1969
#define PCI_DEVICE_ID_ATTANSIC_L1 0x1048
#define PCI_DEVICE_ID_ATTANSIC_L2 0x2048
#define PCI_VENDOR_ID_JMICRON 0x197B
#define PCI_DEVICE_ID_JMICRON_JMB360 0x2360
@ -2244,6 +2259,16 @@
#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007
#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
#define PCI_VENDOR_ID_NETXEN 0x4040
#define PCI_DEVICE_ID_NX2031_10GXSR 0x0001
#define PCI_DEVICE_ID_NX2031_10GCX4 0x0002
#define PCI_DEVICE_ID_NX2031_4GCU 0x0003
#define PCI_DEVICE_ID_NX2031_IMEZ 0x0004
#define PCI_DEVICE_ID_NX2031_HMEZ 0x0005
#define PCI_DEVICE_ID_NX2031_XG_MGMT 0x0024
#define PCI_DEVICE_ID_NX2031_XG_MGMT2 0x0025
#define PCI_DEVICE_ID_NX3031 0x0100
#define PCI_VENDOR_ID_AKS 0x416c
#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100

7
include/linux/percpu.h
View file

@ -23,12 +23,19 @@
__attribute__((__section__(SHARED_ALIGNED_SECTION))) \
PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name \
____cacheline_aligned_in_smp
#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \
__attribute__((__section__(".data.percpu.page_aligned"))) \
PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name
#else
#define DEFINE_PER_CPU(type, name) \
PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name
#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \
DEFINE_PER_CPU(type, name)
#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \
DEFINE_PER_CPU(type, name)
#endif
#define EXPORT_PER_CPU_SYMBOL(var) EXPORT_SYMBOL(per_cpu__##var)

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