From bf051c2def0424f440b77114d29c6bdcdcd8fe60 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 6 Aug 2020 17:25:06 +0530 Subject: [PATCH] ARM: dts: msm: Add PM qos and regulator dt entry for ufs Add PM qos and regulator dt entry for ufs. Change-Id: I311802348d4bbc9308f1b8d68a8137814de5a86d --- qcom/shima-idp.dtsi | 5 ++--- qcom/shima-qrd.dtsi | 7 ++----- qcom/shima.dtsi | 28 +++++++++++++++++++++------- 3 files changed, 25 insertions(+), 15 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a96103389b05..8d4951fe3d01 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -44,16 +44,15 @@ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; + vccq-min-microamp = <0>; vccq2-supply = <&S10B>; vccq2-voltage-level = <1800000 1800000>; vccq2-max-microamp = <800000>; - vccq2-min-microamp = <0>; qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; - /* put vdd-ref-clk regulator to lpm */ - qcom,vddp-ref-clk-min-uV = <0>; + qcom,vddp-ref-clk-min-microamp = <0>; status = "ok"; }; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index c9fc56515407..bed6ecd71a52 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -44,17 +44,14 @@ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; + vccq-min-microamp = <0>; vccq2-supply = <&S10B>; vccq2-voltage-level = <1800000 1800000>; - vccq2-max-microamp = <800000>; - vccq2-min-microamp = <0>; qcom,vddp-ref-clk-supply = <&L9B>; qcom,vddp-ref-clk-max-microamp = <100>; - /* put vdd-ref-clk regulator to lpm */ - qcom,vddp-ref-clk-min-uV = <0>; - + qcom,vddp-ref-clk-min-microamp = <0>; status = "ok"; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index b121ec2093ba..b929c9547c5f 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1283,15 +1283,29 @@ "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "MAX"; - reset-gpios = <&tlmm 204 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; + reset-gpios = <&tlmm 204 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; - iommus = <&apps_smmu 0x80 0x0>; - qcom,iommu-dma = "bypass"; - dma-coherent; + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "bypass"; + dma-coherent; + + rpm-level = <3>; + spm-level = <5>; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <59>; + }; + + qos1 { + mask = <0x0f>; + vote = <65>; + }; - status = "disabled"; }; sdhc_1: sdhci@7C4000 {