diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index a7a6ad055c14..49be829d1454 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -158,6 +158,7 @@ struct clk_rcg2 {
 	u8			cfg_off;
 	u8			flags;
 #define FORCE_ENABLE_RCG	BIT(0)
+#define HW_CLK_CTRL_MODE	BIT(1)
 };
 
 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 2512f144c10b..eede9dfca08f 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -69,16 +69,6 @@ static struct freq_tbl cxo_f = {
 	.n = 0,
 };
 
-static void update_src_map(struct clk_hw *hw)
-{
-	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-	int i, num_parents = clk_hw_get_num_parents(hw);
-
-	for (i = 0; i < num_parents; i++)
-		if (!rcg->parent_map[i].cfg)
-			cxo_f.src = rcg->parent_map[i].src;
-}
-
 static int clk_rcg2_is_enabled(struct clk_hw *hw)
 {
 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -416,6 +406,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
 	if (rcg->mnd_width && f->n && (f->m != f->n))
 		cfg |= CFG_MODE_DUAL_EDGE;
+	if (rcg->flags & HW_CLK_CTRL_MODE)
+		cfg |= CFG_HW_CLK_CTRL_MASK;
+
 	return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
 					mask, cfg);
 }
@@ -453,12 +446,6 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (!f)
 		return -EINVAL;
 
-	/*
-	 * Set the correct source value for CXO as per
-	 * as per defined parent map.
-	 */
-	update_src_map(hw);
-
 	/*
 	 * Return if the RCG is currently disabled. This configuration update
 	 * will happen as part of the RCG enable sequence.
@@ -542,12 +529,6 @@ static int clk_rcg2_enable(struct clk_hw *hw)
 	unsigned long rate;
 	const struct freq_tbl *f;
 
-	/*
-	 * Set the correct source value for CXO as per
-	 * as per defined parent map.
-	 */
-	update_src_map(hw);
-
 	if (rcg->flags & FORCE_ENABLE_RCG) {
 		clk_rcg2_set_force_enable(hw);
 		return 0;
@@ -589,12 +570,6 @@ static void clk_rcg2_disable(struct clk_hw *hw)
 {
 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 
-	/*
-	 * Set the correct source value for CXO as per
-	 * as per defined parent map.
-	 */
-	update_src_map(hw);
-
 	if (rcg->flags & FORCE_ENABLE_RCG) {
 		clk_rcg2_clear_force_enable(hw);
 		return;