From 638d2fe7e5380ca8a53a60a7a7cc8241377e1f9b Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 7 Jan 2019 15:38:50 +0530 Subject: [PATCH 1/2] clk: qcom: rcg2: Remove support for update_src_map The commit 7533b7fb5495 ("clk: qcom: clk-rcg2: Read RCG source before calculating clk rate")' had introduced a function to update the src map, but there could be a race where a set_rate for a clock from a particular CC on a CPU could override the global cxo_f which was set by clock enable/disable for a clock from another CC. Change-Id: Id86818895e226a387e7fd1a09e2034eee18fd361 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-rcg2.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 2512f144c10b..a2c752fe3412 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -69,16 +69,6 @@ static struct freq_tbl cxo_f = { .n = 0, }; -static void update_src_map(struct clk_hw *hw) -{ - struct clk_rcg2 *rcg = to_clk_rcg2(hw); - int i, num_parents = clk_hw_get_num_parents(hw); - - for (i = 0; i < num_parents; i++) - if (!rcg->parent_map[i].cfg) - cxo_f.src = rcg->parent_map[i].src; -} - static int clk_rcg2_is_enabled(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -453,12 +443,6 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, if (!f) return -EINVAL; - /* - * Set the correct source value for CXO as per - * as per defined parent map. - */ - update_src_map(hw); - /* * Return if the RCG is currently disabled. This configuration update * will happen as part of the RCG enable sequence. @@ -542,12 +526,6 @@ static int clk_rcg2_enable(struct clk_hw *hw) unsigned long rate; const struct freq_tbl *f; - /* - * Set the correct source value for CXO as per - * as per defined parent map. - */ - update_src_map(hw); - if (rcg->flags & FORCE_ENABLE_RCG) { clk_rcg2_set_force_enable(hw); return 0; @@ -589,12 +567,6 @@ static void clk_rcg2_disable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - /* - * Set the correct source value for CXO as per - * as per defined parent map. - */ - update_src_map(hw); - if (rcg->flags & FORCE_ENABLE_RCG) { clk_rcg2_clear_force_enable(hw); return; From 8a604ad3ccf3554abeba1876ea2dee9e9e617719 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 14 Dec 2018 12:36:24 +0530 Subject: [PATCH 2/2] clk: qcom: rcg2: Add support for hardware control mode Add a flag to indicate to support and enable hardware control mode of an RCG. Change-Id: I21194a463441ea13b7575a4174b1f96504b42b1e Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index a7a6ad055c14..49be829d1454 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -158,6 +158,7 @@ struct clk_rcg2 { u8 cfg_off; u8 flags; #define FORCE_ENABLE_RCG BIT(0) +#define HW_CLK_CTRL_MODE BIT(1) }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index a2c752fe3412..eede9dfca08f 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -406,6 +406,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; + if (rcg->flags & HW_CLK_CTRL_MODE) + cfg |= CFG_HW_CLK_CTRL_MASK; + return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), mask, cfg); }