From 95cfc3de4fbdd3436d4a876e1b0faeb1be147b83 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 26 Jan 2021 23:41:51 +0530 Subject: [PATCH] ARM: dts: msm: Add handles for PCIE clocks for Yupik PCIE cocks need to be enabled for QoS settings programming, so add PCIE clock handles. Change-Id: Iba060132a1645fb63dd75680b9a56d129966c1a0 --- qcom/yupik.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a1093c241474..15b4b21b6403 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1450,7 +1450,9 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; @@ -1460,10 +1462,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 {