From 6edb8712a37695414d82a5e8d2363b85a5ee5fbd Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 17 Nov 2020 15:45:01 +0530 Subject: [PATCH] ARM: dts: msm: Add eMMC, SD card support for yupik Add eMMC, SD card support for yupik. Change-Id: I09dfa009575967b5263a7b057a1e4e758c7990ed --- qcom/yupik-pinctrl.dtsi | 102 ++++++++++++++++++++++++++++++++++++++++ qcom/yupik-rumi.dtsi | 42 ++++++++++++++++- qcom/yupik.dtsi | 77 ++++++++++++++++++++++++++++++ 3 files changed, 220 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index acc672a31e62..5c51c0efa182 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -37,6 +37,108 @@ }; }; + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio91"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio91"; + bias-disable; + drive-strength = <2>; + }; + }; + qupv3_se0_spi_pins: qupv3_se0_spi_pins { qupv3_se0_spi_active: qupv3_se0_spi_active { mux { diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 66cf1b93aed5..33c0546db1eb 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -1,5 +1,5 @@ #include - +#include &soc { timer { clock-frequency = <5000000>; @@ -54,6 +54,46 @@ }; }; +&sdhc_1 { + status = "disabled"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + cap-mmc-highspeed; +}; + +&sdhc_2 { + status = "disabled"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cap-sd-highspeed; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qrbtc-sdm845"; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6fc836586383..4050cb4d5098 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -26,6 +26,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ }; firmware: firmware { @@ -1229,6 +1231,81 @@ interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; }; + sdhc_1: sdhci@7C4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + bus-width = <8>; + non-removable; + supports-cqe; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <61>; + }; + + qos1 { + mask = <0xf0>; + vote = <67>; + }; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + + bus-width = <4>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 202000000>; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <61>; + }; + + qos1 { + mask = <0xf0>; + vote = <67>; + }; + }; + qcom,lpass@3700000 { compatible = "qcom,pil-tz-generic"; reg = <0x3700000 0x00100>;