bindings: clock: Add CPU clock controller bindings for SDXNIGHTJAR

Add CPU clock controller bindings to support SDXNIGHTJAR. While
at it, also cleanup few properties for the CPU clock.

Change-Id: I28ef84b8a9f16dda4ee2bcf3b05cdda517913393
This commit is contained in:
Rakesh Kota 2020-12-18 12:18:39 +05:30
commit 6f8bfd2a58

View file

@ -7,15 +7,15 @@ clocks and allows CPU frequency scaling on qcs405 based platforms.
Required properties:
- compatible: Shall contain following:
"qcom,sdxlemur-apsscc"
"qcom,sdxnightjar-apsscc"
- clocks: Phandle to the clock device.
- clock-names: Names of the used clocks. Shall contain following:
"xo_ao", "gpll0_ao"
- reg: Shall contain base register offset and size.
- reg-names: Names of the bases for the above registers. Shall contain following:
"apcs_cmd", "apcs_pll"
- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL.
- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL.
- cpu-vdd-supply: The regulator powering the APSS RCG.
- vdd-pll-supply: The regulator(active only) powering the Analog logic of APSS PLL.
- cpu-vdd-supply: The regulator(active only) powering the APSS RCG.
- qcom,speedX-bin-vZ: A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
Format: <freq uV>
This represents the max frequency possible for each possible
@ -25,7 +25,6 @@ Required properties:
Optional properties:
- reg-names: "efuse"
- qcom,cpucc-init-rate: Initial rate which needs to be set from cpu driver.
Example:
clock_cpu: qcom,clock-cpu@17808100 {
@ -33,10 +32,9 @@ Example:
clocks = <&rpmhcc RPMH_CXO_CLK>>;
<&gcc GPLL0_AO_OUT_MAIN>;;
clock-names = "xo_ao", "gpll0_ao" ;
reg = <0x17810008 0x8>,
<0x17808100 0x44>;
reg = <0x17810008 0x8>, <0x17808100 0x44>;
reg-names = "apcs_cmd" , "apcs_pll";
vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
vdd-pll-supply = <&VDD_CX_LEVEL_AO>;
cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
qcom,speed0-bin-v0 =
< 0 RPMH_REGULATOR_LEVEL_OFF>,