Change are regulator nodes for the cpu and gpu regulators on the act8846

variant of the rk3288-evb and the setting of a clock for the watchdog.
 Also the lcd and hdmi controllers on both the firefly and the evb get
 enabled and let us now boot into fbcon console sucessfully.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJUy+f+AAoJEPOmecmc0R2BdFcH/i+9hgt9ElJxKbpPPVPVv81O
 QzmIi3g+B4WqAoKBfzkug5l82mSZ4FAvmQK5ad8BYHsBaGl+GRjwwaqRqZkPUOzl
 umXk0GneZ5sPK+S1UdA/S/v7hTwgEpXOLnGUCGUXbLt7Gqda99ume08jgCe2JbH5
 Tfjoia5uRlOgdZIf3KBr4TkPR+LHog1i/DI9N3XrAsjLtj/igHpoRmFydBmv7noo
 OuRuPY0afg1jKs/MextjM0W1JzQbGyv4Jp4NjVFv60+KZrMgS64vTDZamxYEK4Sv
 wn0pQUZgevQhd3ewdLtqrcbo4wIGiLWBXQK0vzonmo5tCk8r+59QFKxeMiq2C7Q=
 =ZVrD
 -----END PGP SIGNATURE-----

Merge tag 'v3.20-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "ARM: rockchip: third (and last) batch of dts updates for 3.20" from
Heiko Stübner:

Change are regulator nodes for the cpu and gpu regulators on the act8846
variant of the rk3288-evb and the setting of a clock for the watchdog.
Also the lcd and hdmi controllers on both the firefly and the evb get
enabled and let us now boot into fbcon console sucessfully.

* tag 'v3.20-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards
  ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb
  ARM: dts: rockchip: housekeeping off i2c0 on rk3288-evb boards
  ARM: dts: rockchip: add cpu and gpu regulators to rk3288-evb-act8846
  ARM: dts: rockchip: add rk3288 watchdog clock
  clk: rockchip: add id for watchdog pclk on rk3288
  clk: rockchip: add clock IDs for the PVTM clocks
  clk: rockchip: add clock ID for usbphy480m_src

Signed-off-by: Olof Johansson <[email protected]>
This commit is contained in:
Olof Johansson 2015-02-06 00:03:28 -08:00
commit 6f8c8f6baf
6 changed files with 80 additions and 2 deletions

View file

@ -80,6 +80,9 @@
#define SCLK_SDIO0_SAMPLE 119
#define SCLK_SDIO1_SAMPLE 120
#define SCLK_EMMC_SAMPLE 121
#define SCLK_USBPHY480M_SRC 122
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
#define DCLK_VOP0 190
#define DCLK_VOP1 191
@ -154,6 +157,7 @@
#define PCLK_PUBL0 365
#define PCLK_DDRUPCTL1 366
#define PCLK_PUBL1 367
#define PCLK_WDT 368
/* hclk gates */
#define HCLK_GPS 448