mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
Merge branches 'arm-mm', 'at91', 'clkevts', 'imx', 'iop', 'misc', 'netx', 'ns9xxx', 'omap', 'pxa', 'rpc', 's3c' and 'sa1100' into devel
This commit is contained in:
Russell King
Russell King
parent
3603ab2b62
93afa75230
075192ae80
ff4bfb2163
ad902cb9e2
1b11652286
fe7fdb80e9
13ea55b04e
fcf126d847
7053acbd78
5559bca8e6
d0fdb5a58e
d0a9d75b9c
commit
6f95416ebe
130 changed files with 5222 additions and 1106 deletions
61
include/asm-arm/arch-at91/at91_adc.h
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61
include/asm-arm/arch-at91/at91_adc.h
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@ -0,0 +1,61 @@
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/*
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* include/asm-arm/arch-at91/at91_adc.h
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*
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* Copyright (C) SAN People
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*
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* Analog-to-Digital Converter (ADC) registers.
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* Based on AT91SAM9260 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_ADC_H
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#define AT91_ADC_H
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#define AT91_ADC_CR 0x00 /* Control Register */
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#define AT91_ADC_SWRST (1 << 0) /* Software Reset */
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#define AT91_ADC_START (1 << 1) /* Start Conversion */
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#define AT91_ADC_MR 0x04 /* Mode Register */
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#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
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#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
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#define AT91_ADC_TRGSEL_TC0 (0 << 1)
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#define AT91_ADC_TRGSEL_TC1 (1 << 1)
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#define AT91_ADC_TRGSEL_TC2 (2 << 1)
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#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
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#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
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#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
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#define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */
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#define AT91_ADC_PRESCAL_(x) ((x) << 8)
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#define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */
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#define AT91_ADC_STARTUP_(x) ((x) << 16)
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#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
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#define AT91_ADC_SHTIM_(x) ((x) << 24)
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#define AT91_ADC_CHER 0x10 /* Channel Enable Register */
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#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
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#define AT91_ADC_CHSR 0x18 /* Channel Status Register */
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#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
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#define AT91_ADC_SR 0x1C /* Status Register */
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#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
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#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
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#define AT91_ADC_DRDY (1 << 16) /* Data Ready */
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#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
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#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
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#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
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#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
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#define AT91_ADC_LDATA (0x3ff)
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#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
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#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
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#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
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#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */
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#define AT91_ADC_DATA (0x3ff)
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#endif
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@ -62,7 +62,7 @@ struct at91_mmc_data {
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};
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extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
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/* Ethernet */
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/* Ethernet (EMAC & MACB) */
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struct at91_eth_data {
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u8 phy_irq_pin; /* PHY IRQ */
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u8 is_rmii; /* using RMII interface? */
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@ -114,6 +114,16 @@ struct atmel_uart_data {
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};
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extern void __init at91_add_device_serial(void);
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/* LCD Controller */
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struct atmel_lcdfb_info;
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extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
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/* AC97 */
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struct atmel_ac97_data {
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u8 reset_pin; /* reset */
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}
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extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
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/* LEDs */
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extern u8 at91_leds_cpu;
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extern u8 at91_leds_timer;
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@ -477,122 +477,4 @@
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#define LCDISR_EOF (1<<1)
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#define LCDISR_BOF (1<<0)
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/*
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* UART Module. Takes the UART base address as argument
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*/
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#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
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#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
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#define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */
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#define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */
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#define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */
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#define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */
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#define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */
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#define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */
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#define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */
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#define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */
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#define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */
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#define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */
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#define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */
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#define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */
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#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
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#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
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#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
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#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
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#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
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#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
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#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
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#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
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#define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */
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/* UART Control Register Bit Fields.*/
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#define URXD_CHARRDY (1<<15)
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#define URXD_ERR (1<<14)
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#define URXD_OVRRUN (1<<13)
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#define URXD_FRMERR (1<<12)
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#define URXD_BRK (1<<11)
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#define URXD_PRERR (1<<10)
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#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
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#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Recv data ready */
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#define UTS_FRCPERR (1<<13) /* Force parity error */
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#define UTS_LOOP (1<<12) /* Loop tx and rx */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_RXFULL (1<<3) /* RxFIFO full */
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#define UTS_SOFTRST (1<<0) /* Software reset */
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#endif // _IMX_REGS_H
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@ -8,6 +8,7 @@ extern u32 iop13xx_atue_pmmr_offset;
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void iop13xx_init_irq(void);
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void iop13xx_map_io(void);
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void iop13xx_platform_init(void);
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void iop13xx_add_tpmi_devices(void);
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void iop13xx_init_irq(void);
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/* CPUID CP6 R0 Page 0 */
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@ -27,19 +28,24 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
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/* PCI MAP
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* 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
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* 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
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*/
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* bus range cpu phys cpu virt note
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* 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
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* 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
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* 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
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*
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* IO MAP
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* 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
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* 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
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*/
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#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
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#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
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#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
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#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
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#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
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#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
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#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
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IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
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IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
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IOP13XX_PCIX_LOWER_IO_BA)
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#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
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(IOP13XX_PCIX_LOWER_IO_PA\
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- IOP13XX_PCIX_LOWER_IO_VA))
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@ -65,15 +71,14 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
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#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
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#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
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#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
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#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
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#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
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#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
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IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
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IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
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IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
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#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
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IOP13XX_PCIE_LOWER_IO_BA)
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#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
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(IOP13XX_PCIE_LOWER_IO_PA\
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- IOP13XX_PCIE_LOWER_IO_VA))
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@ -451,4 +456,5 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
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#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
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#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
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#endif /* _IOP13XX_HW_H_ */
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@ -7,9 +7,65 @@
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#define IOP_TMR_PRIVILEGED 0x08
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#define IOP_TMR_RATIO_1_1 0x00
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#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
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#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
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#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
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#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
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#define IOP13XX_CORE_FREQ_MASK (7 << 16)
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#define IOP13XX_CORE_FREQ_600 (0 << 16)
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#define IOP13XX_CORE_FREQ_667 (1 << 16)
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#define IOP13XX_CORE_FREQ_800 (2 << 16)
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#define IOP13XX_CORE_FREQ_933 (3 << 16)
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#define IOP13XX_CORE_FREQ_1000 (4 << 16)
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#define IOP13XX_CORE_FREQ_1200 (5 << 16)
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void iop_init_time(unsigned long tickrate);
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unsigned long iop_gettimeoffset(void);
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static inline unsigned long iop13xx_core_freq(void)
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{
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unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
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freq &= IOP13XX_CORE_FREQ_MASK;
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switch (freq) {
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case IOP13XX_CORE_FREQ_600:
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return 600000000;
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case IOP13XX_CORE_FREQ_667:
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return 667000000;
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case IOP13XX_CORE_FREQ_800:
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return 800000000;
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case IOP13XX_CORE_FREQ_933:
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return 933000000;
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case IOP13XX_CORE_FREQ_1000:
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return 1000000000;
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case IOP13XX_CORE_FREQ_1200:
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return 1200000000;
|
||||
default:
|
||||
printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
|
||||
__FUNCTION__);
|
||||
}
|
||||
|
||||
return 800000000;
|
||||
}
|
||||
|
||||
static inline unsigned long iop13xx_xsi_bus_ratio(void)
|
||||
{
|
||||
unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
|
||||
ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
|
||||
switch (ratio) {
|
||||
case IOP13XX_XSI_FREQ_RATIO_2:
|
||||
return 2;
|
||||
case IOP13XX_XSI_FREQ_RATIO_3:
|
||||
return 3;
|
||||
case IOP13XX_XSI_FREQ_RATIO_4:
|
||||
return 4;
|
||||
default:
|
||||
printk("%s: warning unknown ratio, defaulting to 2\n",
|
||||
__FUNCTION__);
|
||||
}
|
||||
|
||||
return 2;
|
||||
}
|
||||
|
||||
static inline void write_tmr0(u32 val)
|
||||
{
|
||||
asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
|
||||
|
|
|
|||
|
|
@ -24,5 +24,14 @@
|
|||
|
||||
#include <asm/hardware/iop3xx.h>
|
||||
|
||||
/* ATU Parameters
|
||||
* set up a 1:1 bus to physical ram relationship
|
||||
* w/ physical ram on top of pci in the memory map
|
||||
*/
|
||||
#define IOP32X_MAX_RAM_SIZE 0x40000000UL
|
||||
#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
|
||||
#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
|
||||
#define IOP32X_PCI_MEM_WINDOW_SIZE 0x04000000
|
||||
#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP32X_PCI_MEM_WINDOW_SIZE
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@
|
|||
* bus_to_virt: Used to convert an address for DMA operations
|
||||
* to an address that the kernel can use.
|
||||
*/
|
||||
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
|
||||
#define __virt_to_bus(x) (__virt_to_phys(x))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(x))
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -29,5 +29,15 @@
|
|||
#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
|
||||
#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
|
||||
|
||||
/* ATU Parameters
|
||||
* set up a 1:1 bus to physical ram relationship
|
||||
* w/ pci on top of physical ram in memory map
|
||||
*/
|
||||
#define IOP33X_MAX_RAM_SIZE 0x80000000UL
|
||||
#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE
|
||||
#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
|
||||
#define IOP33X_PCI_MEM_WINDOW_SIZE 0x08000000
|
||||
#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP33X_PCI_MEM_WINDOW_SIZE
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@
|
|||
* bus_to_virt: Used to convert an address for DMA operations
|
||||
* to an address that the kernel can use.
|
||||
*/
|
||||
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
|
||||
#define __virt_to_bus(x) (__virt_to_phys(x))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(x))
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -121,8 +121,8 @@
|
|||
#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
|
||||
|
||||
/* FIXME: Docs are not consistent */
|
||||
#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08)
|
||||
/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c) */
|
||||
/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */
|
||||
#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c)
|
||||
|
||||
#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10)
|
||||
#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34)
|
||||
|
|
|
|||
|
|
@ -15,4 +15,6 @@
|
|||
|
||||
#define board_is_a9m9750dev() (machine_is_cc9p9360dev())
|
||||
|
||||
#define board_is_jscc9p9360() (machine_is_cc9p9360js())
|
||||
|
||||
#endif /* ifndef __ASM_ARCH_BOARD_H */
|
||||
|
|
|
|||
|
|
@ -11,13 +11,43 @@
|
|||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
#include <asm/arch-ns9xxx/regs-sys.h>
|
||||
|
||||
#define CRYSTAL 29491200 /* Hz */
|
||||
|
||||
/* The HRM calls this value f_vco */
|
||||
static inline u32 ns9xxx_systemclock(void) __attribute__((const));
|
||||
static inline u32 ns9xxx_systemclock(void)
|
||||
{
|
||||
u32 pll = SYS_PLL;
|
||||
|
||||
/*
|
||||
* This should be a multiple of HZ * TIMERCLOCKSELECT (in time.c)
|
||||
* The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
|
||||
* time.c).
|
||||
*
|
||||
* The following values are given:
|
||||
* - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6}
|
||||
* - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2
|
||||
* - ND in {0 .. 31}
|
||||
* - FS in {0 .. 3}
|
||||
*
|
||||
* Assuming the worst, we consider:
|
||||
* - TIMERCLOCKSELECT == 64
|
||||
* - ND == 0
|
||||
* - FS == 3
|
||||
*
|
||||
* So HZ should be a divisor of:
|
||||
* (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT
|
||||
* == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64
|
||||
* == 2^8 * 3^2 * 5^2
|
||||
* == 57600
|
||||
*
|
||||
* Currently HZ is defined to be 100 for this platform.
|
||||
*
|
||||
* Fine.
|
||||
*/
|
||||
return 353894400;
|
||||
return CRYSTAL * (REGGET(pll, SYS_PLL, ND) + 1)
|
||||
>> REGGET(pll, SYS_PLL, FS);
|
||||
}
|
||||
|
||||
static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
|
||||
|
|
|
|||
|
|
@ -51,8 +51,9 @@
|
|||
~(__REGVAL(reg ## _ ## field, value)))) \
|
||||
| (__REGVAL(reg ## _ ## field, value))))
|
||||
|
||||
# define REGGET(reg, field) \
|
||||
((reg & (reg ## _ ## field)) / (field & (-field)))
|
||||
# define REGGET(var, reg, field) \
|
||||
((var & (reg ## _ ## field)) / \
|
||||
((reg ## _ ## field) & (-(reg ## _ ## field))))
|
||||
|
||||
#else
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#define processor_is_ns9360() (machine_is_cc9p9360dev())
|
||||
#define processor_is_ns9360() (machine_is_cc9p9360dev() \
|
||||
|| machine_is_cc9p9360js())
|
||||
|
||||
#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
|
||||
|
|
|
|||
|
|
@ -48,6 +48,12 @@
|
|||
/* PLL Configuration register */
|
||||
#define SYS_PLL __REG(0xa0900188)
|
||||
|
||||
/* PLL FS status */
|
||||
#define SYS_PLL_FS __REGBITS(24, 23)
|
||||
|
||||
/* PLL ND status */
|
||||
#define SYS_PLL_ND __REGBITS(20, 16)
|
||||
|
||||
/* PLL Configuration register: PLL SW change */
|
||||
#define SYS_PLL_SWC __REGBIT(15)
|
||||
#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0)
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ struct i2c_slave_client;
|
|||
struct i2c_pxa_platform_data {
|
||||
unsigned int slave_addr;
|
||||
struct i2c_slave_client *slave;
|
||||
unsigned int class;
|
||||
};
|
||||
|
||||
extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
|
||||
|
|
|
|||
|
|
@ -1801,35 +1801,35 @@
|
|||
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
|
||||
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
|
||||
|
||||
#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
|
||||
#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
|
||||
#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
|
||||
#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
|
||||
#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
|
||||
#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
|
||||
#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
|
||||
#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
|
||||
#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
|
||||
#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
|
||||
#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
|
||||
#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
|
||||
#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
|
||||
#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
|
||||
#define CKEN10_ASSP (1 << 10) /* ASSP (SSP3) Clock Enable */
|
||||
#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
|
||||
#define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */
|
||||
#define CKEN9_NSSP (1 << 9) /* NSSP (SSP2) Clock Enable */
|
||||
#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
|
||||
#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
|
||||
#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
|
||||
#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
|
||||
#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */
|
||||
#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
|
||||
#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
|
||||
#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
|
||||
#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
|
||||
#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
|
||||
#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
|
||||
#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
|
||||
#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
|
||||
#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
|
||||
#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
|
||||
#define CKEN_IM (20) /* Internal Memory Clock Enable */
|
||||
#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
|
||||
#define CKEN_USIM (18) /* USIM Unit Clock Enable */
|
||||
#define CKEN_MSL (17) /* MSL Unit Clock Enable */
|
||||
#define CKEN_LCD (16) /* LCD Unit Clock Enable */
|
||||
#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
|
||||
#define CKEN_I2C (14) /* I2C Unit Clock Enable */
|
||||
#define CKEN_FICP (13) /* FICP Unit Clock Enable */
|
||||
#define CKEN_MMC (12) /* MMC Unit Clock Enable */
|
||||
#define CKEN_USB (11) /* USB Unit Clock Enable */
|
||||
#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
|
||||
#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
|
||||
#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
|
||||
#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
|
||||
#define CKEN_I2S (8) /* I2S Unit Clock Enable */
|
||||
#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
|
||||
#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
|
||||
#define CKEN_STUART (5) /* STUART Unit Clock Enable */
|
||||
#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
|
||||
#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
|
||||
#define CKEN_SSP (3) /* SSP Unit Clock Enable */
|
||||
#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
|
||||
#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
|
||||
#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
|
||||
#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
|
||||
|
||||
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
|
||||
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
|
||||
|
|
|
|||
|
|
@ -13,11 +13,55 @@
|
|||
#ifndef __ASM_ARCH_REGS_AC97_H
|
||||
#define __ASM_ARCH_REGS_AC97_H __FILE__
|
||||
|
||||
#define S3C_AC97_GLBCTRL (0x00)
|
||||
#define S3C_AC97_GLBSTAT (0x04)
|
||||
#define S3C_AC97_CODEC_CMD (0x08)
|
||||
#define S3C_AC97_PCM_ADDR (0x10)
|
||||
#define S3C_AC97_PCM_DATA (0x18)
|
||||
#define S3C_AC97_MIC_DATA (0x1C)
|
||||
#define S3C_AC97_GLBCTRL (0x00)
|
||||
|
||||
#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
|
||||
#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
|
||||
#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
|
||||
#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
|
||||
#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
|
||||
#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
|
||||
#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
|
||||
#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
|
||||
#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
|
||||
#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
|
||||
#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
|
||||
#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
|
||||
#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
|
||||
#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
|
||||
#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
|
||||
#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
|
||||
#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
|
||||
#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
|
||||
#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
|
||||
#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
|
||||
#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
|
||||
#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
|
||||
#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
|
||||
|
||||
#define S3C_AC97_GLBSTAT (0x04)
|
||||
|
||||
#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
|
||||
#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
|
||||
#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
|
||||
#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
|
||||
#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
|
||||
#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
|
||||
#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
|
||||
#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
|
||||
#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
|
||||
#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
|
||||
#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
|
||||
#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
|
||||
#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
|
||||
|
||||
#define S3C_AC97_CODEC_CMD (0x08)
|
||||
|
||||
#define S3C_AC97_CODEC_CMD_READ (1<<23)
|
||||
|
||||
#define S3C_AC97_STAT (0x0c)
|
||||
#define S3C_AC97_PCM_ADDR (0x10)
|
||||
#define S3C_AC97_PCM_DATA (0x18)
|
||||
#define S3C_AC97_MIC_DATA (0x1C)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_AC97_H */
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@
|
|||
#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
|
||||
#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
|
||||
|
||||
|
||||
#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
|
||||
|
||||
#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
|
||||
#define S3C2410_UDC_PWR_RESET (1<<3) // R
|
||||
|
|
@ -135,10 +135,6 @@
|
|||
#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
|
||||
#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
|
||||
|
||||
#define S3C2410_UDC_SETIX(base,x) \
|
||||
writel(S3C2410_UDC_INDEX_ ## x, base+S3C2410_UDC_INDEX_REG);
|
||||
|
||||
|
||||
#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
|
||||
#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
|
||||
#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
|
||||
|
|
|
|||
|
|
@ -160,6 +160,7 @@ struct expansion_card {
|
|||
unsigned char irqmask; /* IRQ mask */
|
||||
unsigned char fiqmask; /* FIQ mask */
|
||||
unsigned char claimed; /* Card claimed? */
|
||||
unsigned char easi; /* EASI card */
|
||||
|
||||
void *irq_data; /* Data for use for IRQ by card */
|
||||
void *fiq_data; /* Data for use for FIQ by card */
|
||||
|
|
@ -169,7 +170,6 @@ struct expansion_card {
|
|||
CONST unsigned int dma; /* DMA number (for request_dma) */
|
||||
CONST unsigned int irq; /* IRQ number (for request_irq) */
|
||||
CONST unsigned int fiq; /* FIQ number (for request_irq) */
|
||||
CONST card_type_t type; /* Type of card */
|
||||
CONST struct in_ecid cid; /* Card Identification */
|
||||
|
||||
/* Private internal data */
|
||||
|
|
@ -224,56 +224,6 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
|
|||
extern int ecard_request_resources(struct expansion_card *ec);
|
||||
extern void ecard_release_resources(struct expansion_card *ec);
|
||||
|
||||
#ifdef ECARD_C
|
||||
/* Definitions internal to ecard.c - for it's use only!!
|
||||
*
|
||||
* External expansion card header as read from the card
|
||||
*/
|
||||
struct ex_ecid {
|
||||
unsigned char r_irq:1;
|
||||
unsigned char r_zero:1;
|
||||
unsigned char r_fiq:1;
|
||||
unsigned char r_id:4;
|
||||
unsigned char r_a:1;
|
||||
|
||||
unsigned char r_cd:1;
|
||||
unsigned char r_is:1;
|
||||
unsigned char r_w:2;
|
||||
unsigned char r_r1:4;
|
||||
|
||||
unsigned char r_r2:8;
|
||||
|
||||
unsigned char r_prod[2];
|
||||
|
||||
unsigned char r_manu[2];
|
||||
|
||||
unsigned char r_country;
|
||||
|
||||
unsigned char r_fiqmask;
|
||||
unsigned char r_fiqoff[3];
|
||||
|
||||
unsigned char r_irqmask;
|
||||
unsigned char r_irqoff[3];
|
||||
};
|
||||
|
||||
/*
|
||||
* Chunk directory entry as read from the card
|
||||
*/
|
||||
struct ex_chunk_dir {
|
||||
unsigned char r_id;
|
||||
unsigned char r_len[3];
|
||||
unsigned long r_start;
|
||||
union {
|
||||
char string[256];
|
||||
char data[1];
|
||||
} d;
|
||||
#define c_id(x) ((x)->r_id)
|
||||
#define c_len(x) ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
|
||||
#define c_start(x) ((x)->r_start)
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
extern struct bus_type ecard_bus_type;
|
||||
|
||||
#define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev)
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
extern void gpio_line_config(int line, int direction);
|
||||
extern int gpio_line_get(int line);
|
||||
extern void gpio_line_set(int line, int value);
|
||||
extern int init_atu;
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -41,7 +42,7 @@ extern void gpio_line_set(int line, int value);
|
|||
IOP3XX_PERIPHERAL_SIZE - 1)
|
||||
#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
|
||||
IOP3XX_PERIPHERAL_SIZE - 1)
|
||||
#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
|
||||
#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
|
||||
(IOP3XX_PERIPHERAL_PHYS_BASE\
|
||||
- IOP3XX_PERIPHERAL_VIRT_BASE))
|
||||
#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
|
||||
|
|
@ -103,6 +104,21 @@ extern void gpio_line_set(int line, int value);
|
|||
#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
|
||||
#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
|
||||
#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
|
||||
#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
|
||||
#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
|
||||
#define IOP3XX_ATUCR_OUT_EN (1 << 1)
|
||||
|
||||
#define IOP3XX_INIT_ATU_DEFAULT 0
|
||||
#define IOP3XX_INIT_ATU_DISABLE -1
|
||||
#define IOP3XX_INIT_ATU_ENABLE 1
|
||||
|
||||
#ifdef CONFIG_IOP3XX_ATU
|
||||
#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
|
||||
IOP3XX_INIT_ATU_ENABLE : init_atu)
|
||||
#else
|
||||
#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
|
||||
IOP3XX_INIT_ATU_DISABLE : init_atu)
|
||||
#endif
|
||||
|
||||
/* Messaging Unit */
|
||||
#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
|
||||
|
|
@ -253,14 +269,12 @@ extern void gpio_line_set(int line, int value);
|
|||
/*
|
||||
* IOP3XX I/O and Mem space regions for PCI autoconfiguration
|
||||
*/
|
||||
#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
|
||||
#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
|
||||
#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
|
||||
#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
|
||||
|
||||
#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
|
||||
#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
|
||||
#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
|
||||
#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
|
||||
#define IOP3XX_PCI_LOWER_IO_BA 0x90000000
|
||||
#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
|
||||
IOP3XX_PCI_IO_WINDOW_SIZE - 1)
|
||||
#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@ extern struct mutex clocks_mutex;
|
|||
extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
|
||||
|
||||
extern int s3c24xx_register_clock(struct clk *clk);
|
||||
extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
|
||||
|
||||
extern int s3c24xx_setup_clocks(unsigned long xtal,
|
||||
unsigned long fclk,
|
||||
|
|
|
|||
|
|
@ -40,22 +40,6 @@ extern void s3c24xx_init_uartdevs(char *name,
|
|||
struct s3c24xx_uart_resources *res,
|
||||
struct s3c2410_uartcfg *cfg, int no);
|
||||
|
||||
/* the board structure is used at first initialsation time
|
||||
* to get info such as the devices to register for this
|
||||
* board. This is done because platfrom_add_devices() cannot
|
||||
* be called from the map_io entry.
|
||||
*/
|
||||
|
||||
struct s3c24xx_board {
|
||||
struct platform_device **devices;
|
||||
unsigned int devices_count;
|
||||
|
||||
struct clk **clocks;
|
||||
unsigned int clocks_count;
|
||||
};
|
||||
|
||||
extern void s3c24xx_set_board(struct s3c24xx_board *board);
|
||||
|
||||
/* timer for 2410/2440 */
|
||||
|
||||
struct sys_timer;
|
||||
|
|
|
|||
|
|
@ -10,23 +10,19 @@
|
|||
#ifndef __ASM_ARM_PTRACE_H
|
||||
#define __ASM_ARM_PTRACE_H
|
||||
|
||||
|
||||
#define PTRACE_GETREGS 12
|
||||
#define PTRACE_SETREGS 13
|
||||
#define PTRACE_GETFPREGS 14
|
||||
#define PTRACE_SETFPREGS 15
|
||||
|
||||
/* PTRACE_ATTACH is 16 */
|
||||
/* PTRACE_DETACH is 17 */
|
||||
#define PTRACE_GETWMMXREGS 18
|
||||
#define PTRACE_SETWMMXREGS 19
|
||||
|
||||
/* 20 is unused */
|
||||
#define PTRACE_OLDSETOPTIONS 21
|
||||
|
||||
#define PTRACE_GET_THREAD_AREA 22
|
||||
|
||||
#define PTRACE_SET_SYSCALL 23
|
||||
|
||||
/* PTRACE_SYSCALL is 24 */
|
||||
|
||||
#define PTRACE_GETCRUNCHREGS 25
|
||||
#define PTRACE_SETCRUNCHREGS 26
|
||||
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ struct thread_info {
|
|||
__u32 cpu; /* cpu */
|
||||
__u32 cpu_domain; /* cpu domain */
|
||||
struct cpu_context_save cpu_context; /* cpu context */
|
||||
__u32 syscall; /* syscall number */
|
||||
__u8 used_cp[16]; /* thread used copro */
|
||||
unsigned long tp_value;
|
||||
struct crunch_state crunchstate;
|
||||
|
|
|
|||
Loading…
Reference in a new issue