From 6f993bb2f3e822e2ac214cec056f1d25813a1d2b Mon Sep 17 00:00:00 2001
From: Hemant Kumar <hemantk@quicinc.com>
Date: Mon, 29 Mar 2021 16:53:26 -0700
Subject: [PATCH] ARM: dts: msm: Add child node entry for MBB NTN3 i2c client
 on sdxlemur

In order to access NTN3 switch registers add i2c client properties.
By accessing these registers, root complex driver can toggle NTN3
GPIOs tied to downstream endpoint reset. i2c interface is also
used to dump NTN3 registers for debugging PCIe link related issues.

Change-Id: Ia92127f138c2d21ed51e7803b26bcfbb7f2c127f
---
 qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
index 3972cf326b4a..ee8d7977ed58 100644
--- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
+++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
@@ -24,7 +24,20 @@
 
 };
 
+&i2c_3 {
+	pcie_i2c_ctrl: pcie_i2c_ctrl {
+		compatible = "qcom,pcie0-i2c-ntn3";
+		reg = <0x77>;
+		gpio-config-reg = <0x801208>;
+		ep-reset-reg = <0x801210>;
+		ep-reset-gpio-mask = <0x9>;
+		dump-regs = <0x801330 0x801350 0x801370>;
+	};
+};
+
 &pcie0 {
+	pcie-i2c-phandle = <&i2c_3>;
+
 	qcom,filtered-bdfs = <0x02080000>;
 
 	vreg-3p3-supply = <&aqr_vreg>;