mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
coresight: Add snapshot of jtagv8 driver
Add snapshot for jtagv8 driver from msm-4.19
commit c953c9b6eb1f ("include/linux: add notifier for fps change").
Make necessary change to adopt scm framework change.
Change-Id: I289846a1bcb3c0dd11514db69e0088198f7d1cb1
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
This commit is contained in:
Tingwei Zhang
parent
099508939b
commit
6ffa5f7053
8 changed files with 3392 additions and 0 deletions
223
arch/arm64/include/asm/debugv8.h
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223
arch/arm64/include/asm/debugv8.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014,2016-2019, The Linux Foundation. All rights reserved.
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*
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*/
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#ifndef __ASM_DEBUGV8_H
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#define __ASM_DEBUGV8_H
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#include <linux/types.h>
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/* 32 bit register reads for aarch 64 bit */
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#define dbg_readl(reg) RSYSL_##reg()
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/* 64 bit register reads for aarch 64 bit */
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#define dbg_readq(reg) RSYSQ_##reg()
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/* 32 and 64 bit register writes for aarch 64 bit */
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#define dbg_write(val, reg) WSYS_##reg(val)
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#define MRSL(reg) \
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({ \
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uint64_t val; \
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asm volatile("mrs %0, "#reg : "=r" (val)); \
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val; \
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})
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#define MRSQ(reg) \
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({ \
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uint64_t val; \
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asm volatile("mrs %0, "#reg : "=r" (val)); \
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val; \
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})
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#define MSR(val, reg) \
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({ \
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asm volatile("msr "#reg", %0" : : "r" (val)); \
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})
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/*
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* Debug Feature Register
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*
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* Read only
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*/
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#define RSYSQ_ID_AA64DFR0_EL1() MRSQ(ID_AA64DFR0_EL1)
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/*
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* Debug Registers
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*
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* Available only in DBGv8
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*
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* Read only
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* MDCCSR_EL0, MDRAR_EL1, OSLSR_EL1, DBGDTRRX_EL0, DBGAUTHSTATUS_EL1
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*
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* Write only
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* DBGDTRTX_EL0, OSLAR_EL1
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*/
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/* 32 bit registers */
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#define RSYSL_DBGDTRRX_EL0() MRSL(DBGDTRRX_EL0)
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#define RSYSL_MDCCSR_EL0() MRSL(MDCCSR_EL0)
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#define RSYSL_MDSCR_EL1() MRSL(MDSCR_EL1)
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#define RSYSL_OSDTRRX_EL1() MRSL(OSDTRRX_EL1)
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#define RSYSL_OSDTRTX_EL1() MRSL(OSDTRTX_EL1)
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#define RSYSL_OSDLR_EL1() MRSL(OSDLR_EL1)
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#define RSYSL_OSLSR_EL1() MRSL(OSLSR_EL1)
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#define RSYSL_MDCCINT_EL1() MRSL(MDCCINT_EL1)
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#define RSYSL_OSECCR_EL1() MRSL(OSECCR_EL1)
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#define RSYSL_DBGPRCR_EL1() MRSL(DBGPRCR_EL1)
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#define RSYSL_DBGBCR0_EL1() MRSL(DBGBCR0_EL1)
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#define RSYSL_DBGBCR1_EL1() MRSL(DBGBCR1_EL1)
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#define RSYSL_DBGBCR2_EL1() MRSL(DBGBCR2_EL1)
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#define RSYSL_DBGBCR3_EL1() MRSL(DBGBCR3_EL1)
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#define RSYSL_DBGBCR4_EL1() MRSL(DBGBCR4_EL1)
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#define RSYSL_DBGBCR5_EL1() MRSL(DBGBCR5_EL1)
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#define RSYSL_DBGBCR6_EL1() MRSL(DBGBCR6_EL1)
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#define RSYSL_DBGBCR7_EL1() MRSL(DBGBCR7_EL1)
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#define RSYSL_DBGBCR8_EL1() MRSL(DBGBCR8_EL1)
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#define RSYSL_DBGBCR9_EL1() MRSL(DBGBCR9_EL1)
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#define RSYSL_DBGBCR10_EL1() MRSL(DBGBCR10_EL1)
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#define RSYSL_DBGBCR11_EL1() MRSL(DBGBCR11_EL1)
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#define RSYSL_DBGBCR12_EL1() MRSL(DBGBCR12_EL1)
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#define RSYSL_DBGBCR13_EL1() MRSL(DBGBCR13_EL1)
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#define RSYSL_DBGBCR14_EL1() MRSL(DBGBCR14_EL1)
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#define RSYSL_DBGBCR15_EL1() MRSL(DBGBCR15_EL1)
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#define RSYSL_DBGWCR0_EL1() MRSL(DBGWCR0_EL1)
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#define RSYSL_DBGWCR1_EL1() MRSL(DBGWCR1_EL1)
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#define RSYSL_DBGWCR2_EL1() MRSL(DBGWCR2_EL1)
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#define RSYSL_DBGWCR3_EL1() MRSL(DBGWCR3_EL1)
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#define RSYSL_DBGWCR4_EL1() MRSL(DBGWCR4_EL1)
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#define RSYSL_DBGWCR5_EL1() MRSL(DBGWCR5_EL1)
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#define RSYSL_DBGWCR6_EL1() MRSL(DBGWCR6_EL1)
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#define RSYSL_DBGWCR7_EL1() MRSL(DBGWCR7_EL1)
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#define RSYSL_DBGWCR8_EL1() MRSL(DBGWCR8_EL1)
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#define RSYSL_DBGWCR9_EL1() MRSL(DBGWCR9_EL1)
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#define RSYSL_DBGWCR10_EL1() MRSL(DBGWCR10_EL1)
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#define RSYSL_DBGWCR11_EL1() MRSL(DBGWCR11_EL1)
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#define RSYSL_DBGWCR12_EL1() MRSL(DBGWCR12_EL1)
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#define RSYSL_DBGWCR13_EL1() MRSL(DBGWCR13_EL1)
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#define RSYSL_DBGWCR14_EL1() MRSL(DBGWCR14_EL1)
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#define RSYSL_DBGWCR15_EL1() MRSL(DBGWCR15_EL1)
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#define RSYSL_DBGCLAIMSET_EL1() MRSL(DBGCLAIMSET_EL1)
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#define RSYSL_DBGCLAIMCLR_EL1() MRSL(DBGCLAIMCLR_EL1)
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#define RSYSL_DBGAUTHSTATUS_EL1() MRSL(DBGAUTHSTATUS_EL1)
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#define RSYSL_DBGVCR32_EL2() MRSL(DBGVCR32_EL2)
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#define RSYSL_MDCR_EL2() MRSL(MDCR_EL2)
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#define RSYSL_MDCR_EL3() MRSL(MDCR_EL3)
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/* 64 bit registers */
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#define RSYSQ_DBGDTR_EL0() MRSQ(DBGDTR_EL0)
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#define RSYSQ_MDRAR_EL1() MRSQ(MDRAR_EL1)
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#define RSYSQ_DBGBVR0_EL1() MRSQ(DBGBVR0_EL1)
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#define RSYSQ_DBGBVR1_EL1() MRSQ(DBGBVR1_EL1)
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#define RSYSQ_DBGBVR2_EL1() MRSQ(DBGBVR2_EL1)
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#define RSYSQ_DBGBVR3_EL1() MRSQ(DBGBVR3_EL1)
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#define RSYSQ_DBGBVR4_EL1() MRSQ(DBGBVR4_EL1)
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#define RSYSQ_DBGBVR5_EL1() MRSQ(DBGBVR5_EL1)
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#define RSYSQ_DBGBVR6_EL1() MRSQ(DBGBVR6_EL1)
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#define RSYSQ_DBGBVR7_EL1() MRSQ(DBGBVR7_EL1)
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#define RSYSQ_DBGBVR8_EL1() MRSQ(DBGBVR8_EL1)
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#define RSYSQ_DBGBVR9_EL1() MRSQ(DBGBVR9_EL1)
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#define RSYSQ_DBGBVR10_EL1() MRSQ(DBGBVR10_EL1)
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#define RSYSQ_DBGBVR11_EL1() MRSQ(DBGBVR11_EL1)
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#define RSYSQ_DBGBVR12_EL1() MRSQ(DBGBVR12_EL1)
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#define RSYSQ_DBGBVR13_EL1() MRSQ(DBGBVR13_EL1)
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#define RSYSQ_DBGBVR14_EL1() MRSQ(DBGBVR14_EL1)
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#define RSYSQ_DBGBVR15_EL1() MRSQ(DBGBVR15_EL1)
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#define RSYSQ_DBGWVR0_EL1() MRSQ(DBGWVR0_EL1)
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#define RSYSQ_DBGWVR1_EL1() MRSQ(DBGWVR1_EL1)
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#define RSYSQ_DBGWVR2_EL1() MRSQ(DBGWVR2_EL1)
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#define RSYSQ_DBGWVR3_EL1() MRSQ(DBGWVR3_EL1)
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#define RSYSQ_DBGWVR4_EL1() MRSQ(DBGWVR4_EL1)
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#define RSYSQ_DBGWVR5_EL1() MRSQ(DBGWVR5_EL1)
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#define RSYSQ_DBGWVR6_EL1() MRSQ(DBGWVR6_EL1)
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#define RSYSQ_DBGWVR7_EL1() MRSQ(DBGWVR7_EL1)
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#define RSYSQ_DBGWVR8_EL1() MRSQ(DBGWVR8_EL1)
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#define RSYSQ_DBGWVR9_EL1() MRSQ(DBGWVR9_EL1)
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#define RSYSQ_DBGWVR10_EL1() MRSQ(DBGWVR10_EL1)
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#define RSYSQ_DBGWVR11_EL1() MRSQ(DBGWVR11_EL1)
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#define RSYSQ_DBGWVR12_EL1() MRSQ(DBGWVR12_EL1)
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#define RSYSQ_DBGWVR13_EL1() MRSQ(DBGWVR13_EL1)
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#define RSYSQ_DBGWVR14_EL1() MRSQ(DBGWVR14_EL1)
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#define RSYSQ_DBGWVR15_EL1() MRSQ(DBGWVR15_EL1)
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/* 32 bit registers */
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#define WSYS_DBGDTRTX_EL0(val) MSR(val, DBGDTRTX_EL0)
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#define WSYS_MDCCINT_EL1(val) MSR(val, MDCCINT_EL1)
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#define WSYS_MDSCR_EL1(val) MSR(val, MDSCR_EL1)
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#define WSYS_OSDTRRX_EL1(val) MSR(val, OSDTRRX_EL1)
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#define WSYS_OSDTRTX_EL1(val) MSR(val, OSDTRTX_EL1)
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#define WSYS_OSDLR_EL1(val) MSR(val, OSDLR_EL1)
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#define WSYS_OSECCR_EL1(val) MSR(val, OSECCR_EL1)
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#define WSYS_DBGPRCR_EL1(val) MSR(val, DBGPRCR_EL1)
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#define WSYS_DBGBCR0_EL1(val) MSR(val, DBGBCR0_EL1)
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#define WSYS_DBGBCR1_EL1(val) MSR(val, DBGBCR1_EL1)
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#define WSYS_DBGBCR2_EL1(val) MSR(val, DBGBCR2_EL1)
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#define WSYS_DBGBCR3_EL1(val) MSR(val, DBGBCR3_EL1)
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#define WSYS_DBGBCR4_EL1(val) MSR(val, DBGBCR4_EL1)
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#define WSYS_DBGBCR5_EL1(val) MSR(val, DBGBCR5_EL1)
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#define WSYS_DBGBCR6_EL1(val) MSR(val, DBGBCR6_EL1)
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#define WSYS_DBGBCR7_EL1(val) MSR(val, DBGBCR7_EL1)
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#define WSYS_DBGBCR8_EL1(val) MSR(val, DBGBCR8_EL1)
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#define WSYS_DBGBCR9_EL1(val) MSR(val, DBGBCR9_EL1)
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#define WSYS_DBGBCR10_EL1(val) MSR(val, DBGBCR10_EL1)
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#define WSYS_DBGBCR11_EL1(val) MSR(val, DBGBCR11_EL1)
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#define WSYS_DBGBCR12_EL1(val) MSR(val, DBGBCR12_EL1)
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#define WSYS_DBGBCR13_EL1(val) MSR(val, DBGBCR13_EL1)
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#define WSYS_DBGBCR14_EL1(val) MSR(val, DBGBCR14_EL1)
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#define WSYS_DBGBCR15_EL1(val) MSR(val, DBGBCR15_EL1)
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#define WSYS_DBGWCR0_EL1(val) MSR(val, DBGWCR0_EL1)
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#define WSYS_DBGWCR1_EL1(val) MSR(val, DBGWCR1_EL1)
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#define WSYS_DBGWCR2_EL1(val) MSR(val, DBGWCR2_EL1)
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#define WSYS_DBGWCR3_EL1(val) MSR(val, DBGWCR3_EL1)
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#define WSYS_DBGWCR4_EL1(val) MSR(val, DBGWCR4_EL1)
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#define WSYS_DBGWCR5_EL1(val) MSR(val, DBGWCR5_EL1)
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#define WSYS_DBGWCR6_EL1(val) MSR(val, DBGWCR6_EL1)
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#define WSYS_DBGWCR7_EL1(val) MSR(val, DBGWCR7_EL1)
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#define WSYS_DBGWCR8_EL1(val) MSR(val, DBGWCR8_EL1)
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#define WSYS_DBGWCR9_EL1(val) MSR(val, DBGWCR9_EL1)
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#define WSYS_DBGWCR10_EL1(val) MSR(val, DBGWCR10_EL1)
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#define WSYS_DBGWCR11_EL1(val) MSR(val, DBGWCR11_EL1)
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#define WSYS_DBGWCR12_EL1(val) MSR(val, DBGWCR12_EL1)
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#define WSYS_DBGWCR13_EL1(val) MSR(val, DBGWCR13_EL1)
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#define WSYS_DBGWCR14_EL1(val) MSR(val, DBGWCR14_EL1)
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#define WSYS_DBGWCR15_EL1(val) MSR(val, DBGWCR15_EL1)
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#define WSYS_DBGCLAIMSET_EL1(val) MSR(val, DBGCLAIMSET_EL1)
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#define WSYS_DBGCLAIMCLR_EL1(val) MSR(val, DBGCLAIMCLR_EL1)
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#define WSYS_OSLAR_EL1(val) MSR(val, OSLAR_EL1)
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#define WSYS_DBGVCR32_EL2(val) MSR(val, DBGVCR32_EL2)
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#define WSYS_MDCR_EL2(val) MSR(val, MDCR_EL2)
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#define WSYS_MDCR_EL3(val) MSR(val, MDCR_EL3)
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/* 64 bit registers */
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#define WSYS_DBGDTR_EL0(val) MSR(val, DBGDTR_EL0)
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#define WSYS_DBGBVR0_EL1(val) MSR(val, DBGBVR0_EL1)
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#define WSYS_DBGBVR1_EL1(val) MSR(val, DBGBVR1_EL1)
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#define WSYS_DBGBVR2_EL1(val) MSR(val, DBGBVR2_EL1)
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#define WSYS_DBGBVR3_EL1(val) MSR(val, DBGBVR3_EL1)
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#define WSYS_DBGBVR4_EL1(val) MSR(val, DBGBVR4_EL1)
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#define WSYS_DBGBVR5_EL1(val) MSR(val, DBGBVR5_EL1)
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#define WSYS_DBGBVR6_EL1(val) MSR(val, DBGBVR6_EL1)
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#define WSYS_DBGBVR7_EL1(val) MSR(val, DBGBVR7_EL1)
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#define WSYS_DBGBVR8_EL1(val) MSR(val, DBGBVR8_EL1)
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#define WSYS_DBGBVR9_EL1(val) MSR(val, DBGBVR9_EL1)
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#define WSYS_DBGBVR10_EL1(val) MSR(val, DBGBVR10_EL1)
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#define WSYS_DBGBVR11_EL1(val) MSR(val, DBGBVR11_EL1)
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#define WSYS_DBGBVR12_EL1(val) MSR(val, DBGBVR12_EL1)
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#define WSYS_DBGBVR13_EL1(val) MSR(val, DBGBVR13_EL1)
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#define WSYS_DBGBVR14_EL1(val) MSR(val, DBGBVR14_EL1)
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#define WSYS_DBGBVR15_EL1(val) MSR(val, DBGBVR15_EL1)
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#define WSYS_DBGWVR0_EL1(val) MSR(val, DBGWVR0_EL1)
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#define WSYS_DBGWVR1_EL1(val) MSR(val, DBGWVR1_EL1)
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#define WSYS_DBGWVR2_EL1(val) MSR(val, DBGWVR2_EL1)
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#define WSYS_DBGWVR3_EL1(val) MSR(val, DBGWVR3_EL1)
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#define WSYS_DBGWVR4_EL1(val) MSR(val, DBGWVR4_EL1)
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#define WSYS_DBGWVR5_EL1(val) MSR(val, DBGWVR5_EL1)
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#define WSYS_DBGWVR6_EL1(val) MSR(val, DBGWVR6_EL1)
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#define WSYS_DBGWVR7_EL1(val) MSR(val, DBGWVR7_EL1)
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#define WSYS_DBGWVR8_EL1(val) MSR(val, DBGWVR8_EL1)
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#define WSYS_DBGWVR9_EL1(val) MSR(val, DBGWVR9_EL1)
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#define WSYS_DBGWVR10_EL1(val) MSR(val, DBGWVR10_EL1)
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#define WSYS_DBGWVR11_EL1(val) MSR(val, DBGWVR11_EL1)
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#define WSYS_DBGWVR12_EL1(val) MSR(val, DBGWVR12_EL1)
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#define WSYS_DBGWVR13_EL1(val) MSR(val, DBGWVR13_EL1)
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#define WSYS_DBGWVR14_EL1(val) MSR(val, DBGWVR14_EL1)
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#define WSYS_DBGWVR15_EL1(val) MSR(val, DBGWVR15_EL1)
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#endif
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379
arch/arm64/include/asm/etmv4x.h
Normal file
379
arch/arm64/include/asm/etmv4x.h
Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2017, 2019 The Linux Foundation. All rights reserved.
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*/
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#ifndef __ASM_ETMV4X_H
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#define __ASM_ETMV4X_H
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#include <linux/types.h>
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/* 32 bit register reads for AArch64 */
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#define trc_readl(reg) RSYSL_##reg()
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/* 64 bit register reads for AArch64 */
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#define trc_readq(reg) RSYSQ_##reg()
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/* 32 and 64 bit register writes for AArch64 */
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#define trc_write(val, reg) WSYS_##reg(val)
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#define MRSL(op0, op1, crn, crm, op2) \
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({ \
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uint64_t val; \
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asm volatile("mrs %0, S"#op0"_"#op1"_"#crn"_"#crm"_"#op2 : "=r" (val)); \
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val; \
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})
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#define MRSQ(op0, op1, crn, crm, op2) \
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({ \
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uint64_t val; \
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asm volatile("mrs %0, S"#op0"_"#op1"_"#crn"_"#crm"_"#op2 : "=r" (val)); \
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val; \
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})
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#define MSR(val, op0, op1, crn, crm, op2) \
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({ \
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asm volatile("msr S"#op0"_"#op1"_"#crn"_"#crm"_"#op2", %0" : : "r" (val)); \
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})
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/* Clock and Power Management Register */
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#define RSYSL_CPMR_EL1() MRSL(3, 7, c15, c0, 5)
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#define WSYS_CPMR_EL1(val) MSR(val, 3, 7, c15, c0, 5)
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/*
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* ETMv4 Registers
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*
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* Read only
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* ETMAUTHSTATUS, ETMDEVARCH, ETMDEVID, ETMIDRn[0-13], ETMOSLSR, ETMSTATR
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*
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* Write only
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* ETMOSLAR
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*/
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/* 32 bit registers */
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#define RSYSL_ETMAUTHSTATUS() MRSL(2, 1, c7, c14, 6)
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#define RSYSL_ETMAUXCTLR() MRSL(2, 1, c0, c6, 0)
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#define RSYSL_ETMCCCTLR() MRSL(2, 1, c0, c14, 0)
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#define RSYSL_ETMCIDCCTLR0() MRSL(2, 1, c3, c0, 2)
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#define RSYSL_ETMCNTCTLR0() MRSL(2, 1, c0, c4, 5)
|
||||
#define RSYSL_ETMCNTCTLR1() MRSL(2, 1, c0, c5, 5)
|
||||
#define RSYSL_ETMCNTCTLR2() MRSL(2, 1, c0, c6, 5)
|
||||
#define RSYSL_ETMCNTCTLR3() MRSL(2, 1, c0, c7, 5)
|
||||
#define RSYSL_ETMCNTRLDVR0() MRSL(2, 1, c0, c0, 5)
|
||||
#define RSYSL_ETMCNTRLDVR1() MRSL(2, 1, c0, c1, 5)
|
||||
#define RSYSL_ETMCNTRLDVR2() MRSL(2, 1, c0, c2, 5)
|
||||
#define RSYSL_ETMCNTRLDVR3() MRSL(2, 1, c0, c3, 5)
|
||||
#define RSYSL_ETMCNTVR0() MRSL(2, 1, c0, c8, 5)
|
||||
#define RSYSL_ETMCNTVR1() MRSL(2, 1, c0, c9, 5)
|
||||
#define RSYSL_ETMCNTVR2() MRSL(2, 1, c0, c10, 5)
|
||||
#define RSYSL_ETMCNTVR3() MRSL(2, 1, c0, c11, 5)
|
||||
#define RSYSL_ETMCONFIGR() MRSL(2, 1, c0, c4, 0)
|
||||
#define RSYSL_ETMDEVARCH() MRSL(2, 1, c7, c15, 6)
|
||||
#define RSYSL_ETMDEVID() MRSL(2, 1, c7, c2, 7)
|
||||
#define RSYSL_ETMEVENTCTL0R() MRSL(2, 1, c0, c8, 0)
|
||||
#define RSYSL_ETMEVENTCTL1R() MRSL(2, 1, c0, c9, 0)
|
||||
#define RSYSL_ETMEXTINSELR() MRSL(2, 1, c0, c8, 4)
|
||||
#define RSYSL_ETMIDR0() MRSL(2, 1, c0, c8, 7)
|
||||
#define RSYSL_ETMIDR1() MRSL(2, 1, c0, c9, 7)
|
||||
#define RSYSL_ETMIDR10() MRSL(2, 1, c0, c2, 6)
|
||||
#define RSYSL_ETMIDR11() MRSL(2, 1, c0, c3, 6)
|
||||
#define RSYSL_ETMIDR12() MRSL(2, 1, c0, c4, 6)
|
||||
#define RSYSL_ETMIDR13() MRSL(2, 1, c0, c5, 6)
|
||||
#define RSYSL_ETMIDR2() MRSL(2, 1, c0, c10, 7)
|
||||
#define RSYSL_ETMIDR3() MRSL(2, 1, c0, c11, 7)
|
||||
#define RSYSL_ETMIDR4() MRSL(2, 1, c0, c12, 7)
|
||||
#define RSYSL_ETMIDR5() MRSL(2, 1, c0, c13, 7)
|
||||
#define RSYSL_ETMIDR6() MRSL(2, 1, c0, c14, 7)
|
||||
#define RSYSL_ETMIDR7() MRSL(2, 1, c0, c15, 7)
|
||||
#define RSYSL_ETMIDR8() MRSL(2, 1, c0, c0, 6)
|
||||
#define RSYSL_ETMIDR9() MRSL(2, 1, c0, c1, 6)
|
||||
#define RSYSL_ETMIMSPEC0() MRSL(2, 1, c0, c0, 7)
|
||||
#define RSYSL_ETMOSLSR() MRSL(2, 1, c1, c1, 4)
|
||||
#define RSYSL_ETMPRGCTLR() MRSL(2, 1, c0, c1, 0)
|
||||
#define RSYSL_ETMRSCTLR10() MRSL(2, 1, c1, c10, 0)
|
||||
#define RSYSL_ETMRSCTLR11() MRSL(2, 1, c1, c11, 0)
|
||||
#define RSYSL_ETMRSCTLR12() MRSL(2, 1, c1, c12, 0)
|
||||
#define RSYSL_ETMRSCTLR13() MRSL(2, 1, c1, c13, 0)
|
||||
#define RSYSL_ETMRSCTLR14() MRSL(2, 1, c1, c14, 0)
|
||||
#define RSYSL_ETMRSCTLR15() MRSL(2, 1, c1, c15, 0)
|
||||
#define RSYSL_ETMRSCTLR2() MRSL(2, 1, c1, c2, 0)
|
||||
#define RSYSL_ETMRSCTLR3() MRSL(2, 1, c1, c3, 0)
|
||||
#define RSYSL_ETMRSCTLR4() MRSL(2, 1, c1, c4, 0)
|
||||
#define RSYSL_ETMRSCTLR5() MRSL(2, 1, c1, c5, 0)
|
||||
#define RSYSL_ETMRSCTLR6() MRSL(2, 1, c1, c6, 0)
|
||||
#define RSYSL_ETMRSCTLR7() MRSL(2, 1, c1, c7, 0)
|
||||
#define RSYSL_ETMRSCTLR8() MRSL(2, 1, c1, c8, 0)
|
||||
#define RSYSL_ETMRSCTLR9() MRSL(2, 1, c1, c9, 0)
|
||||
#define RSYSL_ETMRSCTLR16() MRSL(2, 1, c1, c0, 1)
|
||||
#define RSYSL_ETMRSCTLR17() MRSL(2, 1, c1, c1, 1)
|
||||
#define RSYSL_ETMRSCTLR18() MRSL(2, 1, c1, c2, 1)
|
||||
#define RSYSL_ETMRSCTLR19() MRSL(2, 1, c1, c3, 1)
|
||||
#define RSYSL_ETMRSCTLR20() MRSL(2, 1, c1, c4, 1)
|
||||
#define RSYSL_ETMRSCTLR21() MRSL(2, 1, c1, c5, 1)
|
||||
#define RSYSL_ETMRSCTLR22() MRSL(2, 1, c1, c6, 1)
|
||||
#define RSYSL_ETMRSCTLR23() MRSL(2, 1, c1, c7, 1)
|
||||
#define RSYSL_ETMRSCTLR24() MRSL(2, 1, c1, c8, 1)
|
||||
#define RSYSL_ETMRSCTLR25() MRSL(2, 1, c1, c9, 1)
|
||||
#define RSYSL_ETMRSCTLR26() MRSL(2, 1, c1, c10, 1)
|
||||
#define RSYSL_ETMRSCTLR27() MRSL(2, 1, c1, c11, 1)
|
||||
#define RSYSL_ETMRSCTLR28() MRSL(2, 1, c1, c12, 1)
|
||||
#define RSYSL_ETMRSCTLR29() MRSL(2, 1, c1, c13, 1)
|
||||
#define RSYSL_ETMRSCTLR30() MRSL(2, 1, c1, c14, 1)
|
||||
#define RSYSL_ETMRSCTLR31() MRSL(2, 1, c1, c15, 1)
|
||||
#define RSYSL_ETMSEQEVR0() MRSL(2, 1, c0, c0, 4)
|
||||
#define RSYSL_ETMSEQEVR1() MRSL(2, 1, c0, c1, 4)
|
||||
#define RSYSL_ETMSEQEVR2() MRSL(2, 1, c0, c2, 4)
|
||||
#define RSYSL_ETMSEQRSTEVR() MRSL(2, 1, c0, c6, 4)
|
||||
#define RSYSL_ETMSEQSTR() MRSL(2, 1, c0, c7, 4)
|
||||
#define RSYSL_ETMSTALLCTLR() MRSL(2, 1, c0, c11, 0)
|
||||
#define RSYSL_ETMSTATR() MRSL(2, 1, c0, c3, 0)
|
||||
#define RSYSL_ETMSYNCPR() MRSL(2, 1, c0, c13, 0)
|
||||
#define RSYSL_ETMTRACEIDR() MRSL(2, 1, c0, c0, 1)
|
||||
#define RSYSL_ETMTSCTLR() MRSL(2, 1, c0, c12, 0)
|
||||
#define RSYSL_ETMVICTLR() MRSL(2, 1, c0, c0, 2)
|
||||
#define RSYSL_ETMVIIECTLR() MRSL(2, 1, c0, c1, 2)
|
||||
#define RSYSL_ETMVISSCTLR() MRSL(2, 1, c0, c2, 2)
|
||||
#define RSYSL_ETMSSCCR0() MRSL(2, 1, c1, c0, 2)
|
||||
#define RSYSL_ETMSSCCR1() MRSL(2, 1, c1, c1, 2)
|
||||
#define RSYSL_ETMSSCCR2() MRSL(2, 1, c1, c2, 2)
|
||||
#define RSYSL_ETMSSCCR3() MRSL(2, 1, c1, c3, 2)
|
||||
#define RSYSL_ETMSSCCR4() MRSL(2, 1, c1, c4, 2)
|
||||
#define RSYSL_ETMSSCCR5() MRSL(2, 1, c1, c5, 2)
|
||||
#define RSYSL_ETMSSCCR6() MRSL(2, 1, c1, c6, 2)
|
||||
#define RSYSL_ETMSSCCR7() MRSL(2, 1, c1, c7, 2)
|
||||
#define RSYSL_ETMSSCSR0() MRSL(2, 1, c1, c8, 2)
|
||||
#define RSYSL_ETMSSCSR1() MRSL(2, 1, c1, c9, 2)
|
||||
#define RSYSL_ETMSSCSR2() MRSL(2, 1, c1, c10, 2)
|
||||
#define RSYSL_ETMSSCSR3() MRSL(2, 1, c1, c11, 2)
|
||||
#define RSYSL_ETMSSCSR4() MRSL(2, 1, c1, c12, 2)
|
||||
#define RSYSL_ETMSSCSR5() MRSL(2, 1, c1, c13, 2)
|
||||
#define RSYSL_ETMSSCSR6() MRSL(2, 1, c1, c14, 2)
|
||||
#define RSYSL_ETMSSCSR7() MRSL(2, 1, c1, c15, 2)
|
||||
#define RSYSL_ETMSSPCICR0() MRSL(2, 1, c1, c0, 3)
|
||||
#define RSYSL_ETMSSPCICR1() MRSL(2, 1, c1, c1, 3)
|
||||
#define RSYSL_ETMSSPCICR2() MRSL(2, 1, c1, c2, 3)
|
||||
#define RSYSL_ETMSSPCICR3() MRSL(2, 1, c1, c3, 3)
|
||||
#define RSYSL_ETMSSPCICR4() MRSL(2, 1, c1, c4, 3)
|
||||
#define RSYSL_ETMSSPCICR5() MRSL(2, 1, c1, c5, 3)
|
||||
#define RSYSL_ETMSSPCICR6() MRSL(2, 1, c1, c6, 3)
|
||||
#define RSYSL_ETMSSPCICR7() MRSL(2, 1, c1, c7, 3)
|
||||
|
||||
/* 64 bit registers */
|
||||
#define RSYSQ_ETMACATR0() MRSQ(2, 1, c2, c0, 2)
|
||||
#define RSYSQ_ETMACATR1() MRSQ(2, 1, c2, c2, 2)
|
||||
#define RSYSQ_ETMACATR2() MRSQ(2, 1, c2, c4, 2)
|
||||
#define RSYSQ_ETMACATR3() MRSQ(2, 1, c2, c6, 2)
|
||||
#define RSYSQ_ETMACATR4() MRSQ(2, 1, c2, c8, 2)
|
||||
#define RSYSQ_ETMACATR5() MRSQ(2, 1, c2, c10, 2)
|
||||
#define RSYSQ_ETMACATR6() MRSQ(2, 1, c2, c12, 2)
|
||||
#define RSYSQ_ETMACATR7() MRSQ(2, 1, c2, c14, 2)
|
||||
#define RSYSQ_ETMACATR8() MRSQ(2, 1, c2, c0, 3)
|
||||
#define RSYSQ_ETMACATR9() MRSQ(2, 1, c2, c2, 3)
|
||||
#define RSYSQ_ETMACATR10() MRSQ(2, 1, c2, c4, 3)
|
||||
#define RSYSQ_ETMACATR11() MRSQ(2, 1, c2, c6, 3)
|
||||
#define RSYSQ_ETMACATR12() MRSQ(2, 1, c2, c8, 3)
|
||||
#define RSYSQ_ETMACATR13() MRSQ(2, 1, c2, c10, 3)
|
||||
#define RSYSQ_ETMACATR14() MRSQ(2, 1, c2, c12, 3)
|
||||
#define RSYSQ_ETMACATR15() MRSQ(2, 1, c2, c14, 3)
|
||||
#define RSYSQ_ETMCIDCVR0() MRSQ(2, 1, c3, c0, 0)
|
||||
#define RSYSQ_ETMCIDCVR1() MRSQ(2, 1, c3, c2, 0)
|
||||
#define RSYSQ_ETMCIDCVR2() MRSQ(2, 1, c3, c4, 0)
|
||||
#define RSYSQ_ETMCIDCVR3() MRSQ(2, 1, c3, c6, 0)
|
||||
#define RSYSQ_ETMCIDCVR4() MRSQ(2, 1, c3, c8, 0)
|
||||
#define RSYSQ_ETMCIDCVR5() MRSQ(2, 1, c3, c10, 0)
|
||||
#define RSYSQ_ETMCIDCVR6() MRSQ(2, 1, c3, c12, 0)
|
||||
#define RSYSQ_ETMCIDCVR7() MRSQ(2, 1, c3, c14, 0)
|
||||
#define RSYSQ_ETMACVR0() MRSQ(2, 1, c2, c0, 0)
|
||||
#define RSYSQ_ETMACVR1() MRSQ(2, 1, c2, c2, 0)
|
||||
#define RSYSQ_ETMACVR2() MRSQ(2, 1, c2, c4, 0)
|
||||
#define RSYSQ_ETMACVR3() MRSQ(2, 1, c2, c6, 0)
|
||||
#define RSYSQ_ETMACVR4() MRSQ(2, 1, c2, c8, 0)
|
||||
#define RSYSQ_ETMACVR5() MRSQ(2, 1, c2, c10, 0)
|
||||
#define RSYSQ_ETMACVR6() MRSQ(2, 1, c2, c12, 0)
|
||||
#define RSYSQ_ETMACVR7() MRSQ(2, 1, c2, c14, 0)
|
||||
#define RSYSQ_ETMACVR8() MRSQ(2, 1, c2, c0, 1)
|
||||
#define RSYSQ_ETMACVR9() MRSQ(2, 1, c2, c2, 1)
|
||||
#define RSYSQ_ETMACVR10() MRSQ(2, 1, c2, c4, 1)
|
||||
#define RSYSQ_ETMACVR11() MRSQ(2, 1, c2, c6, 1)
|
||||
#define RSYSQ_ETMACVR12() MRSQ(2, 1, c2, c8, 1)
|
||||
#define RSYSQ_ETMACVR13() MRSQ(2, 1, c2, c10, 1)
|
||||
#define RSYSQ_ETMACVR14() MRSQ(2, 1, c2, c12, 1)
|
||||
#define RSYSQ_ETMACVR15() MRSQ(2, 1, c2, c14, 1)
|
||||
#define RSYSQ_ETMVMIDCVR0() MRSQ(2, 1, c3, c0, 1)
|
||||
#define RSYSQ_ETMVMIDCVR1() MRSQ(2, 1, c3, c2, 1)
|
||||
#define RSYSQ_ETMVMIDCVR2() MRSQ(2, 1, c3, c4, 1)
|
||||
#define RSYSQ_ETMVMIDCVR3() MRSQ(2, 1, c3, c6, 1)
|
||||
#define RSYSQ_ETMVMIDCVR4() MRSQ(2, 1, c3, c8, 1)
|
||||
#define RSYSQ_ETMVMIDCVR5() MRSQ(2, 1, c3, c10, 1)
|
||||
#define RSYSQ_ETMVMIDCVR6() MRSQ(2, 1, c3, c12, 1)
|
||||
#define RSYSQ_ETMVMIDCVR7() MRSQ(2, 1, c3, c14, 1)
|
||||
#define RSYSQ_ETMDVCVR0() MRSQ(2, 1, c2, c0, 4)
|
||||
#define RSYSQ_ETMDVCVR1() MRSQ(2, 1, c2, c4, 4)
|
||||
#define RSYSQ_ETMDVCVR2() MRSQ(2, 1, c2, c8, 4)
|
||||
#define RSYSQ_ETMDVCVR3() MRSQ(2, 1, c2, c12, 4)
|
||||
#define RSYSQ_ETMDVCVR4() MRSQ(2, 1, c2, c0, 5)
|
||||
#define RSYSQ_ETMDVCVR5() MRSQ(2, 1, c2, c4, 5)
|
||||
#define RSYSQ_ETMDVCVR6() MRSQ(2, 1, c2, c8, 5)
|
||||
#define RSYSQ_ETMDVCVR7() MRSQ(2, 1, c2, c12, 5)
|
||||
#define RSYSQ_ETMDVCMR0() MRSQ(2, 1, c2, c0, 6)
|
||||
#define RSYSQ_ETMDVCMR1() MRSQ(2, 1, c2, c4, 6)
|
||||
#define RSYSQ_ETMDVCMR2() MRSQ(2, 1, c2, c8, 6)
|
||||
#define RSYSQ_ETMDVCMR3() MRSQ(2, 1, c2, c12, 6)
|
||||
#define RSYSQ_ETMDVCMR4() MRSQ(2, 1, c2, c0, 7)
|
||||
#define RSYSQ_ETMDVCMR5() MRSQ(2, 1, c2, c4, 7)
|
||||
#define RSYSQ_ETMDVCMR6() MRSQ(2, 1, c2, c8, 7)
|
||||
#define RSYSQ_ETMDVCMR7() MRSQ(2, 1, c2, c12, 7)
|
||||
|
||||
/* 32 and 64 bit registers */
|
||||
#define WSYS_ETMAUXCTLR(val) MSR(val, 2, 1, c0, c6, 0)
|
||||
#define WSYS_ETMACATR0(val) MSR(val, 2, 1, c2, c0, 2)
|
||||
#define WSYS_ETMACATR1(val) MSR(val, 2, 1, c2, c2, 2)
|
||||
#define WSYS_ETMACATR2(val) MSR(val, 2, 1, c2, c4, 2)
|
||||
#define WSYS_ETMACATR3(val) MSR(val, 2, 1, c2, c6, 2)
|
||||
#define WSYS_ETMACATR4(val) MSR(val, 2, 1, c2, c8, 2)
|
||||
#define WSYS_ETMACATR5(val) MSR(val, 2, 1, c2, c10, 2)
|
||||
#define WSYS_ETMACATR6(val) MSR(val, 2, 1, c2, c12, 2)
|
||||
#define WSYS_ETMACATR7(val) MSR(val, 2, 1, c2, c14, 2)
|
||||
#define WSYS_ETMACATR8(val) MSR(val, 2, 1, c2, c0, 3)
|
||||
#define WSYS_ETMACATR9(val) MSR(val, 2, 1, c2, c2, 3)
|
||||
#define WSYS_ETMACATR10(val) MSR(val, 2, 1, c2, c4, 3)
|
||||
#define WSYS_ETMACATR11(val) MSR(val, 2, 1, c2, c6, 3)
|
||||
#define WSYS_ETMACATR12(val) MSR(val, 2, 1, c2, c8, 3)
|
||||
#define WSYS_ETMACATR13(val) MSR(val, 2, 1, c2, c10, 3)
|
||||
#define WSYS_ETMACATR14(val) MSR(val, 2, 1, c2, c12, 3)
|
||||
#define WSYS_ETMACATR15(val) MSR(val, 2, 1, c2, c14, 3)
|
||||
#define WSYS_ETMACVR0(val) MSR(val, 2, 1, c2, c0, 0)
|
||||
#define WSYS_ETMACVR1(val) MSR(val, 2, 1, c2, c2, 0)
|
||||
#define WSYS_ETMACVR2(val) MSR(val, 2, 1, c2, c4, 0)
|
||||
#define WSYS_ETMACVR3(val) MSR(val, 2, 1, c2, c6, 0)
|
||||
#define WSYS_ETMACVR4(val) MSR(val, 2, 1, c2, c8, 0)
|
||||
#define WSYS_ETMACVR5(val) MSR(val, 2, 1, c2, c10, 0)
|
||||
#define WSYS_ETMACVR6(val) MSR(val, 2, 1, c2, c12, 0)
|
||||
#define WSYS_ETMACVR7(val) MSR(val, 2, 1, c2, c14, 0)
|
||||
#define WSYS_ETMACVR8(val) MSR(val, 2, 1, c2, c0, 1)
|
||||
#define WSYS_ETMACVR9(val) MSR(val, 2, 1, c2, c2, 1)
|
||||
#define WSYS_ETMACVR10(val) MSR(val, 2, 1, c2, c4, 1)
|
||||
#define WSYS_ETMACVR11(val) MSR(val, 2, 1, c2, c6, 1)
|
||||
#define WSYS_ETMACVR12(val) MSR(val, 2, 1, c2, c8, 1)
|
||||
#define WSYS_ETMACVR13(val) MSR(val, 2, 1, c2, c10, 1)
|
||||
#define WSYS_ETMACVR14(val) MSR(val, 2, 1, c2, c12, 1)
|
||||
#define WSYS_ETMACVR15(val) MSR(val, 2, 1, c2, c14, 1)
|
||||
#define WSYS_ETMCCCTLR(val) MSR(val, 2, 1, c0, c14, 0)
|
||||
#define WSYS_ETMCIDCCTLR0(val) MSR(val, 2, 1, c3, c0, 2)
|
||||
#define WSYS_ETMCIDCVR0(val) MSR(val, 2, 1, c3, c0, 0)
|
||||
#define WSYS_ETMCIDCVR1(val) MSR(val, 2, 1, c3, c2, 0)
|
||||
#define WSYS_ETMCIDCVR2(val) MSR(val, 2, 1, c3, c4, 0)
|
||||
#define WSYS_ETMCIDCVR3(val) MSR(val, 2, 1, c3, c6, 0)
|
||||
#define WSYS_ETMCIDCVR4(val) MSR(val, 2, 1, c3, c8, 0)
|
||||
#define WSYS_ETMCIDCVR5(val) MSR(val, 2, 1, c3, c10, 0)
|
||||
#define WSYS_ETMCIDCVR6(val) MSR(val, 2, 1, c3, c12, 0)
|
||||
#define WSYS_ETMCIDCVR7(val) MSR(val, 2, 1, c3, c14, 0)
|
||||
#define WSYS_ETMCNTCTLR0(val) MSR(val, 2, 1, c0, c4, 5)
|
||||
#define WSYS_ETMCNTCTLR1(val) MSR(val, 2, 1, c0, c5, 5)
|
||||
#define WSYS_ETMCNTCTLR2(val) MSR(val, 2, 1, c0, c6, 5)
|
||||
#define WSYS_ETMCNTCTLR3(val) MSR(val, 2, 1, c0, c7, 5)
|
||||
#define WSYS_ETMCNTRLDVR0(val) MSR(val, 2, 1, c0, c0, 5)
|
||||
#define WSYS_ETMCNTRLDVR1(val) MSR(val, 2, 1, c0, c1, 5)
|
||||
#define WSYS_ETMCNTRLDVR2(val) MSR(val, 2, 1, c0, c2, 5)
|
||||
#define WSYS_ETMCNTRLDVR3(val) MSR(val, 2, 1, c0, c3, 5)
|
||||
#define WSYS_ETMCNTVR0(val) MSR(val, 2, 1, c0, c8, 5)
|
||||
#define WSYS_ETMCNTVR1(val) MSR(val, 2, 1, c0, c9, 5)
|
||||
#define WSYS_ETMCNTVR2(val) MSR(val, 2, 1, c0, c10, 5)
|
||||
#define WSYS_ETMCNTVR3(val) MSR(val, 2, 1, c0, c11, 5)
|
||||
#define WSYS_ETMCONFIGR(val) MSR(val, 2, 1, c0, c4, 0)
|
||||
#define WSYS_ETMEVENTCTL0R(val) MSR(val, 2, 1, c0, c8, 0)
|
||||
#define WSYS_ETMEVENTCTL1R(val) MSR(val, 2, 1, c0, c9, 0)
|
||||
#define WSYS_ETMEXTINSELR(val) MSR(val, 2, 1, c0, c8, 4)
|
||||
#define WSYS_ETMIMSPEC0(val) MSR(val, 2, 1, c0, c0, 7)
|
||||
#define WSYS_ETMOSLAR(val) MSR(val, 2, 1, c1, c0, 4)
|
||||
#define WSYS_ETMPRGCTLR(val) MSR(val, 2, 1, c0, c1, 0)
|
||||
#define WSYS_ETMRSCTLR10(val) MSR(val, 2, 1, c1, c10, 0)
|
||||
#define WSYS_ETMRSCTLR11(val) MSR(val, 2, 1, c1, c11, 0)
|
||||
#define WSYS_ETMRSCTLR12(val) MSR(val, 2, 1, c1, c12, 0)
|
||||
#define WSYS_ETMRSCTLR13(val) MSR(val, 2, 1, c1, c13, 0)
|
||||
#define WSYS_ETMRSCTLR14(val) MSR(val, 2, 1, c1, c14, 0)
|
||||
#define WSYS_ETMRSCTLR15(val) MSR(val, 2, 1, c1, c15, 0)
|
||||
#define WSYS_ETMRSCTLR2(val) MSR(val, 2, 1, c1, c2, 0)
|
||||
#define WSYS_ETMRSCTLR3(val) MSR(val, 2, 1, c1, c3, 0)
|
||||
#define WSYS_ETMRSCTLR4(val) MSR(val, 2, 1, c1, c4, 0)
|
||||
#define WSYS_ETMRSCTLR5(val) MSR(val, 2, 1, c1, c5, 0)
|
||||
#define WSYS_ETMRSCTLR6(val) MSR(val, 2, 1, c1, c6, 0)
|
||||
#define WSYS_ETMRSCTLR7(val) MSR(val, 2, 1, c1, c7, 0)
|
||||
#define WSYS_ETMRSCTLR8(val) MSR(val, 2, 1, c1, c8, 0)
|
||||
#define WSYS_ETMRSCTLR9(val) MSR(val, 2, 1, c1, c9, 0)
|
||||
#define WSYS_ETMRSCTLR16(val) MSR(val, 2, 1, c1, c0, 1)
|
||||
#define WSYS_ETMRSCTLR17(val) MSR(val, 2, 1, c1, c1, 1)
|
||||
#define WSYS_ETMRSCTLR18(val) MSR(val, 2, 1, c1, c2, 1)
|
||||
#define WSYS_ETMRSCTLR19(val) MSR(val, 2, 1, c1, c3, 1)
|
||||
#define WSYS_ETMRSCTLR20(val) MSR(val, 2, 1, c1, c4, 1)
|
||||
#define WSYS_ETMRSCTLR21(val) MSR(val, 2, 1, c1, c5, 1)
|
||||
#define WSYS_ETMRSCTLR22(val) MSR(val, 2, 1, c1, c6, 1)
|
||||
#define WSYS_ETMRSCTLR23(val) MSR(val, 2, 1, c1, c7, 1)
|
||||
#define WSYS_ETMRSCTLR24(val) MSR(val, 2, 1, c1, c8, 1)
|
||||
#define WSYS_ETMRSCTLR25(val) MSR(val, 2, 1, c1, c9, 1)
|
||||
#define WSYS_ETMRSCTLR26(val) MSR(val, 2, 1, c1, c10, 1)
|
||||
#define WSYS_ETMRSCTLR27(val) MSR(val, 2, 1, c1, c11, 1)
|
||||
#define WSYS_ETMRSCTLR28(val) MSR(val, 2, 1, c1, c12, 1)
|
||||
#define WSYS_ETMRSCTLR29(val) MSR(val, 2, 1, c1, c13, 1)
|
||||
#define WSYS_ETMRSCTLR30(val) MSR(val, 2, 1, c1, c14, 1)
|
||||
#define WSYS_ETMRSCTLR31(val) MSR(val, 2, 1, c1, c15, 1)
|
||||
#define WSYS_ETMSEQEVR0(val) MSR(val, 2, 1, c0, c0, 4)
|
||||
#define WSYS_ETMSEQEVR1(val) MSR(val, 2, 1, c0, c1, 4)
|
||||
#define WSYS_ETMSEQEVR2(val) MSR(val, 2, 1, c0, c2, 4)
|
||||
#define WSYS_ETMSEQRSTEVR(val) MSR(val, 2, 1, c0, c6, 4)
|
||||
#define WSYS_ETMSEQSTR(val) MSR(val, 2, 1, c0, c7, 4)
|
||||
#define WSYS_ETMSTALLCTLR(val) MSR(val, 2, 1, c0, c11, 0)
|
||||
#define WSYS_ETMSYNCPR(val) MSR(val, 2, 1, c0, c13, 0)
|
||||
#define WSYS_ETMTRACEIDR(val) MSR(val, 2, 1, c0, c0, 1)
|
||||
#define WSYS_ETMTSCTLR(val) MSR(val, 2, 1, c0, c12, 0)
|
||||
#define WSYS_ETMVICTLR(val) MSR(val, 2, 1, c0, c0, 2)
|
||||
#define WSYS_ETMVIIECTLR(val) MSR(val, 2, 1, c0, c1, 2)
|
||||
#define WSYS_ETMVISSCTLR(val) MSR(val, 2, 1, c0, c2, 2)
|
||||
#define WSYS_ETMVMIDCVR0(val) MSR(val, 2, 1, c3, c0, 1)
|
||||
#define WSYS_ETMVMIDCVR1(val) MSR(val, 2, 1, c3, c2, 1)
|
||||
#define WSYS_ETMVMIDCVR2(val) MSR(val, 2, 1, c3, c4, 1)
|
||||
#define WSYS_ETMVMIDCVR3(val) MSR(val, 2, 1, c3, c6, 1)
|
||||
#define WSYS_ETMVMIDCVR4(val) MSR(val, 2, 1, c3, c8, 1)
|
||||
#define WSYS_ETMVMIDCVR5(val) MSR(val, 2, 1, c3, c10, 1)
|
||||
#define WSYS_ETMVMIDCVR6(val) MSR(val, 2, 1, c3, c12, 1)
|
||||
#define WSYS_ETMVMIDCVR7(val) MSR(val, 2, 1, c3, c14, 1)
|
||||
#define WSYS_ETMDVCVR0(val) MSR(val, 2, 1, c2, c0, 4)
|
||||
#define WSYS_ETMDVCVR1(val) MSR(val, 2, 1, c2, c4, 4)
|
||||
#define WSYS_ETMDVCVR2(val) MSR(val, 2, 1, c2, c8, 4)
|
||||
#define WSYS_ETMDVCVR3(val) MSR(val, 2, 1, c2, c12, 4)
|
||||
#define WSYS_ETMDVCVR4(val) MSR(val, 2, 1, c2, c0, 5)
|
||||
#define WSYS_ETMDVCVR5(val) MSR(val, 2, 1, c2, c4, 5)
|
||||
#define WSYS_ETMDVCVR6(val) MSR(val, 2, 1, c2, c8, 5)
|
||||
#define WSYS_ETMDVCVR7(val) MSR(val, 2, 1, c2, c12, 5)
|
||||
#define WSYS_ETMDVCMR0(val) MSR(val, 2, 1, c2, c0, 6)
|
||||
#define WSYS_ETMDVCMR1(val) MSR(val, 2, 1, c2, c4, 6)
|
||||
#define WSYS_ETMDVCMR2(val) MSR(val, 2, 1, c2, c8, 6)
|
||||
#define WSYS_ETMDVCMR3(val) MSR(val, 2, 1, c2, c12, 6)
|
||||
#define WSYS_ETMDVCMR4(val) MSR(val, 2, 1, c2, c0, 7)
|
||||
#define WSYS_ETMDVCMR5(val) MSR(val, 2, 1, c2, c4, 7)
|
||||
#define WSYS_ETMDVCMR6(val) MSR(val, 2, 1, c2, c8, 7)
|
||||
#define WSYS_ETMDVCMR7(val) MSR(val, 2, 1, c2, c12, 7)
|
||||
#define WSYS_ETMSSCCR0(val) MSR(val, 2, 1, c1, c0, 2)
|
||||
#define WSYS_ETMSSCCR1(val) MSR(val, 2, 1, c1, c1, 2)
|
||||
#define WSYS_ETMSSCCR2(val) MSR(val, 2, 1, c1, c2, 2)
|
||||
#define WSYS_ETMSSCCR3(val) MSR(val, 2, 1, c1, c3, 2)
|
||||
#define WSYS_ETMSSCCR4(val) MSR(val, 2, 1, c1, c4, 2)
|
||||
#define WSYS_ETMSSCCR5(val) MSR(val, 2, 1, c1, c5, 2)
|
||||
#define WSYS_ETMSSCCR6(val) MSR(val, 2, 1, c1, c6, 2)
|
||||
#define WSYS_ETMSSCCR7(val) MSR(val, 2, 1, c1, c7, 2)
|
||||
#define WSYS_ETMSSCSR0(val) MSR(val, 2, 1, c1, c8, 2)
|
||||
#define WSYS_ETMSSCSR1(val) MSR(val, 2, 1, c1, c9, 2)
|
||||
#define WSYS_ETMSSCSR2(val) MSR(val, 2, 1, c1, c10, 2)
|
||||
#define WSYS_ETMSSCSR3(val) MSR(val, 2, 1, c1, c11, 2)
|
||||
#define WSYS_ETMSSCSR4(val) MSR(val, 2, 1, c1, c12, 2)
|
||||
#define WSYS_ETMSSCSR5(val) MSR(val, 2, 1, c1, c13, 2)
|
||||
#define WSYS_ETMSSCSR6(val) MSR(val, 2, 1, c1, c14, 2)
|
||||
#define WSYS_ETMSSCSR7(val) MSR(val, 2, 1, c1, c15, 2)
|
||||
#define WSYS_ETMSSPCICR0(val) MSR(val, 2, 1, c1, c0, 3)
|
||||
#define WSYS_ETMSSPCICR1(val) MSR(val, 2, 1, c1, c1, 3)
|
||||
#define WSYS_ETMSSPCICR2(val) MSR(val, 2, 1, c1, c2, 3)
|
||||
#define WSYS_ETMSSPCICR3(val) MSR(val, 2, 1, c1, c3, 3)
|
||||
#define WSYS_ETMSSPCICR4(val) MSR(val, 2, 1, c1, c4, 3)
|
||||
#define WSYS_ETMSSPCICR5(val) MSR(val, 2, 1, c1, c5, 3)
|
||||
#define WSYS_ETMSSPCICR6(val) MSR(val, 2, 1, c1, c6, 3)
|
||||
#define WSYS_ETMSSPCICR7(val) MSR(val, 2, 1, c1, c7, 3)
|
||||
|
||||
#endif
|
||||
|
|
@ -560,6 +560,18 @@ config QTI_DDR_STATS_LOG
|
|||
frequency residency and counts. The driver outputs information using
|
||||
sysfs.
|
||||
|
||||
config MSM_JTAGV8
|
||||
bool "Debug and ETM trace support across power collapse for ARMv8"
|
||||
default y if CORESIGHT_SOURCE_ETM4X
|
||||
depends on QCOM_SCM=y
|
||||
help
|
||||
Enables support for debugging (specifically breakpoints) and ETM
|
||||
processor tracing across power collapse both for JTag and OS hosted
|
||||
software running on ARMv8 target. Enabling this will ensure debug
|
||||
and ETM registers are saved and restored across power collapse.
|
||||
If unsure, say 'N' here to avoid potential power, performance and
|
||||
memory penalty.
|
||||
|
||||
config QCOM_FSA4480_I2C
|
||||
bool "Fairchild FSA4480 chip with I2C"
|
||||
select REGMAP_I2C
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o
|
|||
obj-$(CONFIG_QCOM_LAHAINA_LLCC) += llcc-lahaina.o
|
||||
obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o
|
||||
obj-$(CONFIG_QCOM_DCC_V2) += dcc_v2.o
|
||||
obj-$(CONFIG_MSM_JTAGV8) += jtagv8.o jtagv8-etm.o
|
||||
obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o
|
||||
obj-$(CONFIG_QCOM_LLCC_PERFMON) += llcc_perfmon.o
|
||||
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
|
||||
|
|
|
|||
1724
drivers/soc/qcom/jtagv8-etm.c
Normal file
1724
drivers/soc/qcom/jtagv8-etm.c
Normal file
File diff suppressed because it is too large
Load diff
1002
drivers/soc/qcom/jtagv8.c
Normal file
1002
drivers/soc/qcom/jtagv8.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -140,6 +140,10 @@ enum cpuhp_state {
|
|||
CPUHP_AP_DUMMY_TIMER_STARTING,
|
||||
CPUHP_AP_ARM_XEN_STARTING,
|
||||
CPUHP_AP_ARM_CORESIGHT_STARTING,
|
||||
#ifdef CONFIG_CORESIGHT_QGKI
|
||||
CPUHP_AP_ARM_SAVE_RESTORE_CORESIGHT4_STARTING,
|
||||
CPUHP_AP_ARM_MM_CORESIGHT4_STARTING,
|
||||
#endif
|
||||
CPUHP_AP_ARM64_ISNDEP_STARTING,
|
||||
CPUHP_AP_SMPCFD_DYING,
|
||||
CPUHP_AP_X86_TBOOT_DYING,
|
||||
|
|
|
|||
47
include/soc/qcom/jtag.h
Normal file
47
include/soc/qcom/jtag.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2012-2015, 2017-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_JTAG_H
|
||||
#define __MACH_JTAG_H
|
||||
|
||||
#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM) || \
|
||||
defined(CONFIG_MSM_JTAGV8)
|
||||
extern void msm_jtag_save_state(void);
|
||||
extern void msm_jtag_restore_state(void);
|
||||
extern void msm_jtag_etm_save_state(void);
|
||||
extern void msm_jtag_etm_restore_state(void);
|
||||
extern bool msm_jtag_fuse_apps_access_disabled(void);
|
||||
#else
|
||||
static inline void msm_jtag_save_state(void) {}
|
||||
static inline void msm_jtag_restore_state(void) {}
|
||||
static inline void msm_jtag_etm_save_state(void) {}
|
||||
static inline void msm_jtag_etm_restore_state(void){}
|
||||
static inline bool msm_jtag_fuse_apps_access_disabled(void) { return false; }
|
||||
#endif
|
||||
#ifdef CONFIG_MSM_JTAGV8
|
||||
extern int msm_jtag_save_register(struct notifier_block *nb);
|
||||
extern int msm_jtag_save_unregister(struct notifier_block *nb);
|
||||
extern int msm_jtag_restore_register(struct notifier_block *nb);
|
||||
extern int msm_jtag_restore_unregister(struct notifier_block *nb);
|
||||
#else
|
||||
static inline int msm_jtag_save_register(struct notifier_block *nb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int msm_jtag_save_unregister(struct notifier_block *nb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int msm_jtag_restore_register(struct notifier_block *nb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int msm_jtag_restore_unregister(struct notifier_block *nb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue