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drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
This workaround for bdw and chv, is also needed for kbl A0.
References: HSD#1911519, BSID#569
Signed-off-by: Mika Kuoppala <[email protected]>
Reviewed-by: Matthew Auld <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 066d462888)
Signed-off-by: Mika Kuoppala <[email protected]>
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1 changed files with 17 additions and 0 deletions
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@ -1275,6 +1275,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
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{
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int ret;
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struct drm_device *dev = engine->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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/* WaDisableCtxRestoreArbitration:skl,bxt */
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@ -1288,6 +1289,22 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
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return ret;
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index = ret;
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/* WaClearSlmSpaceAtContextSwitch:kbl */
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/* Actual scratch location is at 128 bytes offset */
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if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
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uint32_t scratch_addr
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= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
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wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
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wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
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PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_QW_WRITE));
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wa_ctx_emit(batch, index, scratch_addr);
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wa_ctx_emit(batch, index, 0);
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wa_ctx_emit(batch, index, 0);
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wa_ctx_emit(batch, index, 0);
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}
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/* Pad to end of cacheline */
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while (index % CACHELINE_DWORDS)
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wa_ctx_emit(batch, index, MI_NOOP);
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