A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: Add DPC property for SM6150

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Add "dynamic-power-coefficient" property to all cores.
The "capacity-dmips-mhz" and "dynamic-power-coefficient"
are used to build Energy Model which in turn used by EAS to
take placement decisions.

Change-Id: Ieed91b03a482e3e23af6b63656bb52245f149379
This commit is contained in:
Shreyas K K 2021-02-12 13:20:26 +05:30
commit 704b584258
1 changed files with 8 additions and 0 deletions
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8
qcom/sm6150.dtsi
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@ -49,6 +49,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -74,6 +75,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -94,6 +96,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -113,6 +116,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -132,6 +136,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -151,6 +156,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -170,6 +176,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
@ -189,6 +196,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1 2>;