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irqchip/exiu: Add support for Socionext Synquacer EXIU controller

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The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.

The EXIU has per-interrupt level/edge and polarity controls, and
mask bits that keep the outgoing lines de-asserted, even though
the controller may still latch interrupt conditions that occur
while the line is masked.

Signed-off-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
This commit is contained in:
Ard Biesheuvel 2017-11-06 18:34:37 +00:00 • committed by Marc Zyngier
commit 706cffc1b9
3 changed files with 231 additions and 0 deletions
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3
arch/arm64/Kconfig.platforms
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@ -161,6 +161,9 @@ config ARCH_SEATTLE
config ARCH_SHMOBILE
bool
config ARCH_SYNQUACER
bool "Socionext SynQuacer SoC Family"
config ARCH_RENESAS
bool "Renesas SoC Platforms"
select ARCH_SHMOBILE