From 8c7b756a467fb8ad5cf53835408e11c10bca52af Mon Sep 17 00:00:00 2001 From: Urvashi Agrawal Date: Fri, 28 Feb 2020 13:14:36 -0800 Subject: [PATCH] msm: kgsl: Add the list of protected registers for A660 Add the list of protected registers for A660 GPU. Change-Id: If0d1990449ba2ea73c9b813fd2f97db89d8062f1 Signed-off-by: Urvashi Agrawal --- drivers/gpu/msm/adreno-gpulist.h | 42 +++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index e43e1b97dc9c..55682388d73f 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -1489,6 +1489,46 @@ static const struct adreno_reglist a660_hwcg_regs[] = { {A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, {A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, }; + +/* A660 protected register list */ +static const struct a6xx_protected_regs a660_protected_regs[] = { + { A6XX_CP_PROTECT_REG + 0, 0x00000, 0x004ff, 0 }, + { A6XX_CP_PROTECT_REG + 1, 0x00501, 0x00506, 0 }, + { A6XX_CP_PROTECT_REG + 2, 0x0050b, 0x007ff, 0 }, + { A6XX_CP_PROTECT_REG + 3, 0x0050e, 0x0050e, 1 }, + { A6XX_CP_PROTECT_REG + 4, 0x00510, 0x00510, 1 }, + { A6XX_CP_PROTECT_REG + 5, 0x00534, 0x00534, 1 }, + { A6XX_CP_PROTECT_REG + 6, 0x00800, 0x00882, 1 }, + { A6XX_CP_PROTECT_REG + 7, 0x008a0, 0x008a8, 1 }, + { A6XX_CP_PROTECT_REG + 8, 0x008ab, 0x008cf, 1 }, + { A6XX_CP_PROTECT_REG + 9, 0x008d0, 0x0098c, 0 }, + { A6XX_CP_PROTECT_REG + 10, 0x00900, 0x0094d, 1 }, + { A6XX_CP_PROTECT_REG + 11, 0x0098d, 0x00bff, 1 }, + { A6XX_CP_PROTECT_REG + 12, 0x00e00, 0x00e01, 1 }, + { A6XX_CP_PROTECT_REG + 13, 0x00e03, 0x00e0f, 1 }, + { A6XX_CP_PROTECT_REG + 14, 0x03c00, 0x03cc3, 1 }, + { A6XX_CP_PROTECT_REG + 15, 0x03cc4, 0x05cc3, 0 }, + { A6XX_CP_PROTECT_REG + 16, 0x08630, 0x087ff, 1 }, + { A6XX_CP_PROTECT_REG + 17, 0x08e00, 0x08e00, 1 }, + { A6XX_CP_PROTECT_REG + 18, 0x08e08, 0x08e08, 1 }, + { A6XX_CP_PROTECT_REG + 19, 0x08e50, 0x08e6f, 1 }, + { A6XX_CP_PROTECT_REG + 20, 0x08e80, 0x090ff, 1 }, + { A6XX_CP_PROTECT_REG + 21, 0x09624, 0x097ff, 1 }, + { A6XX_CP_PROTECT_REG + 22, 0x09e60, 0x09e71, 1 }, + { A6XX_CP_PROTECT_REG + 23, 0x09e78, 0x09fff, 1 }, + { A6XX_CP_PROTECT_REG + 24, 0x0a630, 0x0a7ff, 1 }, + { A6XX_CP_PROTECT_REG + 25, 0x0ae02, 0x0ae02, 1 }, + { A6XX_CP_PROTECT_REG + 26, 0x0ae50, 0x0af7f, 1 }, + { A6XX_CP_PROTECT_REG + 27, 0x0b604, 0x0b604, 1 }, + { A6XX_CP_PROTECT_REG + 28, 0x0b608, 0x0b60e, 1 }, + { A6XX_CP_PROTECT_REG + 29, 0x0be02, 0x0be03, 1 }, + { A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0bf7f, 1 }, + { A6XX_CP_PROTECT_REG + 31, 0x0d000, 0x0d5ff, 1 }, + { A6XX_CP_PROTECT_REG + 32, 0x0f000, 0x0fbff, 1 }, + { A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 }, + { A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 }, +}; + static const struct adreno_a6xx_core adreno_gpu_core_a660 = { { DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID), @@ -1514,7 +1554,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = { .vbif_count = ARRAY_SIZE(a650_gbif_regs), .hang_detect_cycles = 0xcfffff, .veto_fal10 = true, - .protected_regs = a620_protected_regs, + .protected_regs = a660_protected_regs, .disable_tseskip = true, .highest_bank_bit = 15, .pdc_in_aop = true,