From a281748567a662aa17f8a1ab64f454636e0ad1af Mon Sep 17 00:00:00 2001
From: Tao Zhang <taozha@qti.qualcomm.com>
Date: Thu, 27 May 2021 18:08:59 +0800
Subject: [PATCH] ARM: dts: msm: Add apss dl cti0 for shima

Add app dl cti0 to device tree for DCC LLCC timeout on shima.

Change-Id: I8f8bd5626a848c015631849b1790e18582109c22
---
 qcom/shima-coresight.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi
index 471a736d4b05..23f47fd675cd 100644
--- a/qcom/shima-coresight.dtsi
+++ b/qcom/shima-coresight.dtsi
@@ -3598,6 +3598,18 @@
 		clock-names = "apb_pclk";
 	};
 
+	cti0_apss_dl: cti@7862000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x7862000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_dl_cti0";
+
+		clocks = <&aopcc QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
 	snoc: snoc {
 		compatible = "qcom,coresight-dummy";
 		coresight-name = "coresight-snoc";