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Merge "ARM: dts: msm: STMMAC changes for SA8195"

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qctecmdr 2021-02-26 02:48:45 -08:00 • committed by Gerrit - the friendly Code Review server
commit 70e73cdc6d
1 changed files with 136 additions and 0 deletions
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136
qcom/sa8195p-adp-common.dtsi
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@ -1,4 +1,5 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-scshrike.h>
#include "sa8195p-cnss.dtsi"
@ -49,4 +50,139 @@
qcom,npu@9800000 {
status = "ok"
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xC>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3E800>;
snps,low_credit = <0xFFC18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3E800>;
snps,low_credit = <0xFFC18000>;
};
};
ethqos_hw: qcom,ethernet@00020000 {
compatible = "qcom,stmmac-ethqos";
qcom,arm-smmu;
emac-core-version = <0x20010001>;
reg = <0x20000 0x10000>,
<0x36000 0x100>,
<0x3D00000 0x300000>;
reg-names = "stmmaceth", "rgmii","tlmm-central-base";
clocks = <&gcc GCC_EMAC_AXI_CLK>,
<&gcc GCC_EMAC_SLV_AHB_CLK>,
<&gcc GCC_EMAC_PTP_CLK>,
<&gcc GCC_EMAC_RGMII_CLK>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
snps,ptp-ref-clk-rate = <250000000>;
snps,ptp-req-clk-rate = <96000000>;
interrupts-extended = <&intc 0 689 4>, <&intc 0 700 4>,
<&tlmm 124 2>;
interrupt-names = "macirq", "eth_lpi",
"phy-intr";
snps,tso;
rx-fifo-depth = <16384>;
tx-fifo-depth = <32768>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>;
qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>;
gdsc_emac-supply = <&emac_gdsc>;
pinctrl-names = "dev-emac-mdc",
"dev-emac-mdio",
"dev-emac-rgmii_txd0_state",
"dev-emac-rgmii_txd1_state",
"dev-emac-rgmii_txd2_state",
"dev-emac-rgmii_txd3_state",
"dev-emac-rgmii_txc_state",
"dev-emac-rgmii_tx_ctl_state",
"dev-emac-rgmii_rxd0_state",
"dev-emac-rgmii_rxd1_state",
"dev-emac-rgmii_rxd2_state",
"dev-emac-rgmii_rxd3_state",
"dev-emac-rgmii_rxc_state",
"dev-emac-rgmii_rx_ctl_state",
"dev-emac-phy_intr",
"dev-emac-phy_reset_state",
"dev-emac_pin_pps_0";
pinctrl-0 = <&emac_mdc>;
pinctrl-1 = <&emac_mdio>;
pinctrl-2 = <&emac_rgmii_txd0>;
pinctrl-3 = <&emac_rgmii_txd1>;
pinctrl-4 = <&emac_rgmii_txd2>;
pinctrl-5 = <&emac_rgmii_txd3>;
pinctrl-6 = <&emac_rgmii_txc>;
pinctrl-7 = <&emac_rgmii_tx_ctl>;
pinctrl-8 = <&emac_rgmii_rxd0>;
pinctrl-9 = <&emac_rgmii_rxd1>;
pinctrl-10 = <&emac_rgmii_rxd2>;
pinctrl-11 = <&emac_rgmii_rxd3>;
pinctrl-12 = <&emac_rgmii_rxc>;
pinctrl-13 = <&emac_rgmii_rx_ctl>;
pinctrl-14 = <&emac_phy_intr>;
pinctrl-15 = <&emac_phy_reset_state>;
pinctrl-16 = <&emac_pin_pps_0>;
snps,reset-delays-us = <0 11000 70000>;
phy-mode = "rgmii";
ethqos_emb_smmu: ethqos_emb_smmu {
compatible = "qcom,emac-smmu-embedded";
iommus = <&apps_smmu 0x7C0 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>;
};
};
};