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KVM: MIPS: VZ support, Octeon III, and TLBR
Add basic support for the MIPS Virtualization Module (generally known as MIPS VZ) in KVM. We primarily support the ImgTec P5600, P6600, I6400, and Cavium Octeon III cores so far. Support is included for the following VZ / guest hardware features: - MIPS32 and MIPS64, r5 (VZ requires r5 or later) and r6 - TLBs with GuestID (IMG cores) or Root ASID Dealias (Octeon III) - Shared physical root/guest TLB (IMG cores) - FPU / MSA - Cop0 timer (up to 1GHz for now due to soft timer limit) - Segmentation control (EVA) - Hardware page table walker (HTW) both for root and guest TLB Also included is a proper implementation of the TLBR instruction for the trap & emulate MIPS KVM implementation. Preliminary MIPS architecture changes are applied directly with Ralf's ack. -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJY5XPkAAoJEGwLaZPeOHZ6aLcQAI43z58kkUopHJVfXtUbS+p0 Bno+oi6XKwEL0AD361A6jflbfxaSHQocilhCBvGKf7c7Rm/oRWrAxrXDnNEDi59s U7tH8KATdzgySu8mZOJNp8a0VcWS08yAbwOeZcqASPowBARPhlga3DCQdC6mWePi rlfHzRi2hBNKOc1q3KmGKDfiwi4x3dcLQYd9O8RmdpAjW5bfem0mJ76w9LRkPZHz YiCxnHYa0n4sNscT7HREe+P9/MzD2MQY04m+jhSMo/IHYPec9ap8kFN+de/4P1cT J2yTscywsQlC56E/pcRT5X0TYAZz/rsDhmRnIKRYuJBrGIXV8BKdYyqmBrxC7o6/ K4HvXJtMzkyG/xGj5l4TqTgTlPH0k4iu/bBWvyRjd40v3ZpSq5GqNG+6VX1QfYDW ZNa0fviC9uHqbfHijHs9IV1Kdb4bII/xd2eotCUy8jKbikd6FJWUT/XqQB4NGQpW PZtgPXVs958vWLG1qrdh2dSMpGR21uPwp9NsqGim/3raQOlDeTUK+x384urqLcU/ pQT2WROmXw8H9qPPKpkCs9xdhp0ja2TotTJcqH+mNk+r3QzWa4N95rpd9MZKtbyc YaQqC5FWru79ZfO53n2PsZidWyHHUS1rxYuYkopeGC7pgmoUdKdHwkzkvFdWLXHE Ol8lksYDC5aHiWD6V8Sh =smiL -----END PGP SIGNATURE----- Merge tag 'kvm_mips_4.12_1' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/kvm-mips From: James Hogan <[email protected]> KVM: MIPS: VZ support, Octeon III, and TLBR Add basic support for the MIPS Virtualization Module (generally known as MIPS VZ) in KVM. We primarily support the ImgTec P5600, P6600, I6400, and Cavium Octeon III cores so far. Support is included for the following VZ / guest hardware features: - MIPS32 and MIPS64, r5 (VZ requires r5 or later) and r6 - TLBs with GuestID (IMG cores) or Root ASID Dealias (Octeon III) - Shared physical root/guest TLB (IMG cores) - FPU / MSA - Cop0 timer (up to 1GHz for now due to soft timer limit) - Segmentation control (EVA) - Hardware page table walker (HTW) both for root and guest TLB Also included is a proper implementation of the TLBR instruction for the trap & emulate MIPS KVM implementation. Preliminary MIPS architecture changes are applied directly with Ralf's ack.
This commit is contained in:
Radim Krčmář
commit
715958f921
29 changed files with 5010 additions and 367 deletions
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@ -115,12 +115,17 @@ will access the virtual machine's physical address space; offset zero
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corresponds to guest physical address zero. Use of mmap() on a VM fd
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is discouraged if userspace memory allocation (KVM_CAP_USER_MEMORY) is
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available.
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You most certainly want to use 0 as machine type.
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You probably want to use 0 as machine type.
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In order to create user controlled virtual machines on S390, check
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KVM_CAP_S390_UCONTROL and use the flag KVM_VM_S390_UCONTROL as
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privileged user (CAP_SYS_ADMIN).
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To use hardware assisted virtualization on MIPS (VZ ASE) rather than
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the default trap & emulate implementation (which changes the virtual
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memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the
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flag KVM_VM_MIPS_VZ.
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4.3 KVM_GET_MSR_INDEX_LIST
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@ -2068,11 +2073,23 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_ENTRYLO0 | 64
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MIPS | KVM_REG_MIPS_CP0_ENTRYLO1 | 64
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MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64
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MIPS | KVM_REG_MIPS_CP0_CONTEXTCONFIG| 32
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MIPS | KVM_REG_MIPS_CP0_USERLOCAL | 64
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MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64
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MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
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MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN | 32
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MIPS | KVM_REG_MIPS_CP0_SEGCTL0 | 64
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MIPS | KVM_REG_MIPS_CP0_SEGCTL1 | 64
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MIPS | KVM_REG_MIPS_CP0_SEGCTL2 | 64
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MIPS | KVM_REG_MIPS_CP0_PWBASE | 64
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MIPS | KVM_REG_MIPS_CP0_PWFIELD | 64
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MIPS | KVM_REG_MIPS_CP0_PWSIZE | 64
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MIPS | KVM_REG_MIPS_CP0_WIRED | 32
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MIPS | KVM_REG_MIPS_CP0_PWCTL | 32
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MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
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MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
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MIPS | KVM_REG_MIPS_CP0_BADINSTR | 32
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MIPS | KVM_REG_MIPS_CP0_BADINSTRP | 32
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MIPS | KVM_REG_MIPS_CP0_COUNT | 32
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MIPS | KVM_REG_MIPS_CP0_ENTRYHI | 64
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MIPS | KVM_REG_MIPS_CP0_COMPARE | 32
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@ -2089,6 +2106,7 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_CONFIG4 | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG5 | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG7 | 32
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MIPS | KVM_REG_MIPS_CP0_XCONTEXT | 64
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MIPS | KVM_REG_MIPS_CP0_ERROREPC | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH1 | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH2 | 64
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@ -2096,6 +2114,7 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH4 | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH5 | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH6 | 64
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MIPS | KVM_REG_MIPS_CP0_MAAR(0..63) | 64
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MIPS | KVM_REG_MIPS_COUNT_CTL | 64
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MIPS | KVM_REG_MIPS_COUNT_RESUME | 64
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MIPS | KVM_REG_MIPS_COUNT_HZ | 64
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@ -2162,6 +2181,10 @@ hardware, host kernel, guest, and whether XPA is present in the guest, i.e.
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with the RI and XI bits (if they exist) in bits 63 and 62 respectively, and
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the PFNX field starting at bit 30.
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MIPS MAARs (see KVM_REG_MIPS_CP0_MAAR(*) above) have the following id bit
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patterns:
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0x7030 0000 0001 01 <reg:8>
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MIPS KVM control registers (see above) have the following id bit patterns:
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0x7030 0000 0002 <reg:16>
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@ -4210,3 +4233,68 @@ This capability, if KVM_CHECK_EXTENSION indicates that it is
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available, means that that the kernel can support guests using the
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hashed page table MMU defined in Power ISA V3.00 (as implemented in
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the POWER9 processor), including in-memory segment tables.
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8.5 KVM_CAP_MIPS_VZ
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Architectures: mips
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This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that
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it is available, means that full hardware assisted virtualization capabilities
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of the hardware are available for use through KVM. An appropriate
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KVM_VM_MIPS_* type must be passed to KVM_CREATE_VM to create a VM which
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utilises it.
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If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is
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available, it means that the VM is using full hardware assisted virtualization
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capabilities of the hardware. This is useful to check after creating a VM with
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KVM_VM_MIPS_DEFAULT.
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The value returned by KVM_CHECK_EXTENSION should be compared against known
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values (see below). All other values are reserved. This is to allow for the
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possibility of other hardware assisted virtualization implementations which
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may be incompatible with the MIPS VZ ASE.
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0: The trap & emulate implementation is in use to run guest code in user
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mode. Guest virtual memory segments are rearranged to fit the guest in the
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user mode address space.
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1: The MIPS VZ ASE is in use, providing full hardware assisted
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virtualization, including standard guest virtual memory segments.
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8.6 KVM_CAP_MIPS_TE
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Architectures: mips
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This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that
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it is available, means that the trap & emulate implementation is available to
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run guest code in user mode, even if KVM_CAP_MIPS_VZ indicates that hardware
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assisted virtualisation is also available. KVM_VM_MIPS_TE (0) must be passed
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to KVM_CREATE_VM to create a VM which utilises it.
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If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is
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available, it means that the VM is using trap & emulate.
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8.7 KVM_CAP_MIPS_64BIT
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Architectures: mips
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This capability indicates the supported architecture type of the guest, i.e. the
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supported register and address width.
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The values returned when this capability is checked by KVM_CHECK_EXTENSION on a
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kvm VM handle correspond roughly to the CP0_Config.AT register field, and should
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be checked specifically against known values (see below). All other values are
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reserved.
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0: MIPS32 or microMIPS32.
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Both registers and addresses are 32-bits wide.
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It will only be possible to run 32-bit guest code.
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1: MIPS64 or microMIPS64 with access only to 32-bit compatibility segments.
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Registers are 64-bits wide, but addresses are 32-bits wide.
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64-bit guest code may run but cannot access MIPS64 memory segments.
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It will also be possible to run 32-bit guest code.
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2: MIPS64 or microMIPS64 with access to all address segments.
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Both registers and addresses are 64-bits wide.
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It will be possible to run 64-bit or 32-bit guest code.
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@ -28,6 +28,11 @@ S390:
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property inside the device tree's /hypervisor node.
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For more information refer to Documentation/virtual/kvm/ppc-pv.txt
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MIPS:
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KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall
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number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and
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the return value is placed in $2 (v0).
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KVM Hypercalls Documentation
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===========================
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The template for each hypercall is:
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