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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

Browse source 
Conflicts:
	drivers/net/ethernet/rocker/rocker.c

The rocker commit was two overlapping changes, one to rename
the ->vport member to ->pport, and another making the bitmask
expression use '1ULL' instead of plain '1'.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2015-03-03 21:16:48 -05:00
commit 71a83a6db6
1279 changed files with 49670 additions and 20358 deletions
Download patch file Download diff file Expand all files Collapse all files

1
include/linux/bcm47xx_wdt.h
View file

@ -16,6 +16,7 @@ struct bcm47xx_wdt {
struct watchdog_device wdd;
struct notifier_block notifier;
struct notifier_block restart_handler;
struct timer_list soft_timer;
atomic_t soft_ticks;

37
include/linux/ceph/ceph_fs.h
View file

@ -158,17 +158,6 @@ enum {
};
/* pool operations */
enum {
POOL_OP_CREATE = 0x01,
POOL_OP_DELETE = 0x02,
POOL_OP_AUID_CHANGE = 0x03,
POOL_OP_CREATE_SNAP = 0x11,
POOL_OP_DELETE_SNAP = 0x12,
POOL_OP_CREATE_UNMANAGED_SNAP = 0x21,
POOL_OP_DELETE_UNMANAGED_SNAP = 0x22,
};
struct ceph_mon_request_header {
__le64 have_version;
__le16 session_mon;
@ -191,31 +180,6 @@ struct ceph_mon_statfs_reply {
struct ceph_statfs st;
} __attribute__ ((packed));
const char *ceph_pool_op_name(int op);
struct ceph_mon_poolop {
struct ceph_mon_request_header monhdr;
struct ceph_fsid fsid;
__le32 pool;
__le32 op;
__le64 auid;
__le64 snapid;
__le32 name_len;
} __attribute__ ((packed));
struct ceph_mon_poolop_reply {
struct ceph_mon_request_header monhdr;
struct ceph_fsid fsid;
__le32 reply_code;
__le32 epoch;
char has_data;
char data[0];
} __attribute__ ((packed));
struct ceph_mon_unmanaged_snap {
__le64 snapid;
} __attribute__ ((packed));
struct ceph_osd_getmap {
struct ceph_mon_request_header monhdr;
struct ceph_fsid fsid;
@ -307,6 +271,7 @@ enum {
CEPH_SESSION_RECALL_STATE,
CEPH_SESSION_FLUSHMSG,
CEPH_SESSION_FLUSHMSG_ACK,
CEPH_SESSION_FORCE_RO,
};
extern const char *ceph_session_op_name(int op);

3
include/linux/ceph/libceph.h
View file

@ -30,8 +30,9 @@
#define CEPH_OPT_MYIP (1<<2) /* specified my ip */
#define CEPH_OPT_NOCRC (1<<3) /* no data crc on writes */
#define CEPH_OPT_NOMSGAUTH (1<<4) /* not require cephx message signature */
#define CEPH_OPT_TCP_NODELAY (1<<5) /* TCP_NODELAY on TCP sockets */
#define CEPH_OPT_DEFAULT (0)
#define CEPH_OPT_DEFAULT (CEPH_OPT_TCP_NODELAY)
#define ceph_set_opt(client, opt) \
(client)->options->flags |= CEPH_OPT_##opt;

4
include/linux/ceph/messenger.h
View file

@ -57,6 +57,7 @@ struct ceph_messenger {
atomic_t stopping;
bool nocrc;
bool tcp_nodelay;
/*
* the global_seq counts connections i (attempt to) initiate
@ -264,7 +265,8 @@ extern void ceph_messenger_init(struct ceph_messenger *msgr,
struct ceph_entity_addr *myaddr,
u64 supported_features,
u64 required_features,
bool nocrc);
bool nocrc,
bool tcp_nodelay);
extern void ceph_con_init(struct ceph_connection *con, void *private,
const struct ceph_connection_operations *ops,

9
include/linux/ceph/mon_client.h
View file

@ -40,7 +40,7 @@ struct ceph_mon_request {
};
/*
* ceph_mon_generic_request is being used for the statfs, poolop and
* ceph_mon_generic_request is being used for the statfs and
* mon_get_version requests which are being done a bit differently
* because we need to get data back to the caller
*/
@ -50,7 +50,6 @@ struct ceph_mon_generic_request {
struct rb_node node;
int result;
void *buf;
int buf_len;
struct completion completion;
struct ceph_msg *request; /* original request */
struct ceph_msg *reply; /* and reply */
@ -117,10 +116,4 @@ extern int ceph_monc_open_session(struct ceph_mon_client *monc);
extern int ceph_monc_validate_auth(struct ceph_mon_client *monc);
extern int ceph_monc_create_snapid(struct ceph_mon_client *monc,
u32 pool, u64 *snapid);
extern int ceph_monc_delete_snapid(struct ceph_mon_client *monc,
u32 pool, u64 snapid);
#endif

220
include/linux/clk-private.h
View file

@ -1,220 +0,0 @@
/*
* linux/include/linux/clk-private.h
*
* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_CLK_PRIVATE_H
#define __LINUX_CLK_PRIVATE_H
#include <linux/clk-provider.h>
#include <linux/kref.h>
#include <linux/list.h>
/*
* WARNING: Do not include clk-private.h from any file that implements struct
* clk_ops. Doing so is a layering violation!
*
* This header exists only to allow for statically initialized clock data. Any
* static clock data must be defined in a separate file from the logic that
* implements the clock operations for that same data.
*/
#ifdef CONFIG_COMMON_CLK
struct module;
struct clk {
const char *name;
const struct clk_ops *ops;
struct clk_hw *hw;
struct module *owner;
struct clk *parent;
const char **parent_names;
struct clk **parents;
u8 num_parents;
u8 new_parent_index;
unsigned long rate;
unsigned long new_rate;
struct clk *new_parent;
struct clk *new_child;
unsigned long flags;
unsigned int enable_count;
unsigned int prepare_count;
unsigned long accuracy;
int phase;
struct hlist_head children;
struct hlist_node child_node;
struct hlist_node debug_node;
unsigned int notifier_count;
#ifdef CONFIG_DEBUG_FS
struct dentry *dentry;
#endif
struct kref ref;
};
/*
* DOC: Basic clock implementations common to many platforms
*
* Each basic clock hardware type is comprised of a structure describing the
* clock hardware, implementations of the relevant callbacks in struct clk_ops,
* unique flags for that hardware type, a registration function and an
* alternative macro for static initialization
*/
#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \
_parents) \
static struct clk _name = { \
.name = #_name, \
.ops = &_ops, \
.hw = &_name##_hw.hw, \
.parent_names = _parent_names, \
.num_parents = ARRAY_SIZE(_parent_names), \
.parents = _parents, \
.flags = _flags | CLK_IS_BASIC, \
}
#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
_fixed_rate_flags) \
static struct clk _name; \
static const char *_name##_parent_names[] = {}; \
static struct clk_fixed_rate _name##_hw = { \
.hw = { \
.clk = &_name, \
}, \
.fixed_rate = _rate, \
.flags = _fixed_rate_flags, \
}; \
DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \
_name##_parent_names, NULL);
#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
_flags, _reg, _bit_idx, \
_gate_flags, _lock) \
static struct clk _name; \
static const char *_name##_parent_names[] = { \
_parent_name, \
}; \
static struct clk *_name##_parents[] = { \
_parent_ptr, \
}; \
static struct clk_gate _name##_hw = { \
.hw = { \
.clk = &_name, \
}, \
.reg = _reg, \
.bit_idx = _bit_idx, \
.flags = _gate_flags, \
.lock = _lock, \
}; \
DEFINE_CLK(_name, clk_gate_ops, _flags, \
_name##_parent_names, _name##_parents);
#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
_divider_flags, _table, _lock) \
static struct clk _name; \
static const char *_name##_parent_names[] = { \
_parent_name, \
}; \
static struct clk *_name##_parents[] = { \
_parent_ptr, \
}; \
static struct clk_divider _name##_hw = { \
.hw = { \
.clk = &_name, \
}, \
.reg = _reg, \
.shift = _shift, \
.width = _width, \
.flags = _divider_flags, \
.table = _table, \
.lock = _lock, \
}; \
DEFINE_CLK(_name, clk_divider_ops, _flags, \
_name##_parent_names, _name##_parents);
#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
_divider_flags, _lock) \
_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
_divider_flags, NULL, _lock)
#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
_parent_ptr, _flags, _reg, \
_shift, _width, _divider_flags, \
_table, _lock) \
_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
_divider_flags, _table, _lock) \
#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
_reg, _shift, _width, \
_mux_flags, _lock) \
static struct clk _name; \
static struct clk_mux _name##_hw = { \
.hw = { \
.clk = &_name, \
}, \
.reg = _reg, \
.shift = _shift, \
.mask = BIT(_width) - 1, \
.flags = _mux_flags, \
.lock = _lock, \
}; \
DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \
_parents);
#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \
_parent_ptr, _flags, \
_mult, _div) \
static struct clk _name; \
static const char *_name##_parent_names[] = { \
_parent_name, \
}; \
static struct clk *_name##_parents[] = { \
_parent_ptr, \
}; \
static struct clk_fixed_factor _name##_hw = { \
.hw = { \
.clk = &_name, \
}, \
.mult = _mult, \
.div = _div, \
}; \
DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \
_name##_parent_names, _name##_parents);
/**
* __clk_init - initialize the data structures in a struct clk
* @dev: device initializing this clk, placeholder for now
* @clk: clk being initialized
*
* Initializes the lists in struct clk, queries the hardware for the
* parent and rate and sets them both.
*
* Any struct clk passed into __clk_init must have the following members
* populated:
* .name
* .ops
* .hw
* .parent_names
* .num_parents
* .flags
*
* It is not necessary to call clk_register if __clk_init is used directly with
* statically initialized clock data.
*
* Returns 0 on success, otherwise an error code.
*/
int __clk_init(struct device *dev, struct clk *clk);
struct clk *__clk_register(struct device *dev, struct clk_hw *hw);
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PRIVATE_H */

58
include/linux/clk-provider.h
View file

@ -33,6 +33,7 @@
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
struct clk_hw;
struct clk_core;
struct dentry;
/**
@ -174,9 +175,12 @@ struct clk_ops {
unsigned long parent_rate);
long (*round_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate);
long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_hw);
long (*determine_rate)(struct clk_hw *hw,
unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_hw);
int (*set_parent)(struct clk_hw *hw, u8 index);
u8 (*get_parent)(struct clk_hw *hw);
int (*set_rate)(struct clk_hw *hw, unsigned long rate,
@ -216,13 +220,17 @@ struct clk_init_data {
* clk_foo and then referenced by the struct clk instance that uses struct
* clk_foo's clk_ops
*
* @clk: pointer to the struct clk instance that points back to this struct
* clk_hw instance
* @core: pointer to the struct clk_core instance that points back to this
* struct clk_hw instance
*
* @clk: pointer to the per-user struct clk instance that can be used to call
* into the clk API
*
* @init: pointer to struct clk_init_data that contains the init data shared
* with the common clock framework.
*/
struct clk_hw {
struct clk_core *core;
struct clk *clk;
const struct clk_init_data *init;
};
@ -294,6 +302,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
void clk_unregister_gate(struct clk *clk);
struct clk_div_table {
unsigned int val;
@ -352,6 +361,17 @@ struct clk_divider {
#define CLK_DIVIDER_READ_ONLY BIT(5)
extern const struct clk_ops clk_divider_ops;
unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
unsigned int val, const struct clk_div_table *table,
unsigned long flags);
long divider_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate, const struct clk_div_table *table,
u8 width, unsigned long flags);
int divider_get_val(unsigned long rate, unsigned long parent_rate,
const struct clk_div_table *table, u8 width,
unsigned long flags);
struct clk *clk_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
@ -361,6 +381,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock);
void clk_unregister_divider(struct clk *clk);
/**
* struct clk_mux - multiplexer clock
@ -382,6 +403,8 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
* register, and mask of mux bits are in higher 16-bit of this register.
* While setting the mux bits, higher 16-bit should also be updated to
* indicate changing mux bits.
* CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
* frequency.
*/
struct clk_mux {
struct clk_hw hw;
@ -396,7 +419,8 @@ struct clk_mux {
#define CLK_MUX_INDEX_ONE BIT(0)
#define CLK_MUX_INDEX_BIT BIT(1)
#define CLK_MUX_HIWORD_MASK BIT(2)
#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */
#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
#define CLK_MUX_ROUND_CLOSEST BIT(4)
extern const struct clk_ops clk_mux_ops;
extern const struct clk_ops clk_mux_ro_ops;
@ -411,6 +435,8 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
void __iomem *reg, u8 shift, u32 mask,
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
void clk_unregister_mux(struct clk *clk);
void of_fixed_factor_clk_setup(struct device_node *node);
/**
@ -550,15 +576,29 @@ bool __clk_is_prepared(struct clk *clk);
bool __clk_is_enabled(struct clk *clk);
struct clk *__clk_lookup(const char *name);
long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_p);
unsigned long __clk_determine_rate(struct clk_hw *core,
unsigned long rate,
unsigned long min_rate,
unsigned long max_rate);
long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_p);
static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
{
dst->clk = src->clk;
dst->core = src->core;
}
/*
* FIXME clock api without lock protection
*/
int __clk_prepare(struct clk *clk);
void __clk_unprepare(struct clk *clk);
void __clk_reparent(struct clk *clk, struct clk *new_parent);
unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
struct of_device_id;

45
include/linux/clk.h
View file

@ -301,6 +301,46 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
*/
int clk_set_rate(struct clk *clk, unsigned long rate);
/**
* clk_has_parent - check if a clock is a possible parent for another
* @clk: clock source
* @parent: parent clock source
*
* This function can be used in drivers that need to check that a clock can be
* the parent of another without actually changing the parent.
*
* Returns true if @parent is a possible parent for @clk, false otherwise.
*/
bool clk_has_parent(struct clk *clk, struct clk *parent);
/**
* clk_set_rate_range - set a rate range for a clock source
* @clk: clock source
* @min: desired minimum clock rate in Hz, inclusive
* @max: desired maximum clock rate in Hz, inclusive
*
* Returns success (0) or negative errno.
*/
int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
/**
* clk_set_min_rate - set a minimum clock rate for a clock source
* @clk: clock source
* @rate: desired minimum clock rate in Hz, inclusive
*
* Returns success (0) or negative errno.
*/
int clk_set_min_rate(struct clk *clk, unsigned long rate);
/**
* clk_set_max_rate - set a maximum clock rate for a clock source
* @clk: clock source
* @rate: desired maximum clock rate in Hz, inclusive
*
* Returns success (0) or negative errno.
*/
int clk_set_max_rate(struct clk *clk, unsigned long rate);
/**
* clk_set_parent - set the parent clock source for this clock
* @clk: clock source
@ -374,6 +414,11 @@ static inline long clk_round_rate(struct clk *clk, unsigned long rate)
return 0;
}
static inline bool clk_has_parent(struct clk *clk, struct clk *parent)
{
return true;
}
static inline int clk_set_parent(struct clk *clk, struct clk *parent)
{
return 0;

22
include/linux/clk/sunxi.h
View file

@ -1,22 +0,0 @@
/*
* Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_CLK_SUNXI_H_
#define __LINUX_CLK_SUNXI_H_
#include <linux/clk.h>
void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
#endif

2
include/linux/clk/tegra.h
View file

@ -120,6 +120,4 @@ static inline void tegra_cpu_clock_resume(void)
}
#endif
void tegra_clocks_apply_init_table(void);
#endif /* __LINUX_CLK_TEGRA_H_ */

25
include/linux/clk/ti.h
View file

@ -15,6 +15,7 @@
#ifndef __LINUX_CLK_TI_H__
#define __LINUX_CLK_TI_H__
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
/**
@ -217,6 +218,13 @@ struct ti_dt_clk {
/* Maximum number of clock memmaps */
#define CLK_MAX_MEMMAPS 4
/* Static memmap indices */
enum {
TI_CLKM_CM = 0,
TI_CLKM_PRM,
TI_CLKM_SCRM,
};
typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
/**
@ -263,6 +271,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
u8 index);
long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_clk);
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
@ -272,6 +282,8 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
unsigned long *parent_rate);
long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_clk);
u8 omap2_init_dpll_parent(struct clk_hw *hw);
@ -348,4 +360,17 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
#ifdef CONFIG_ATAGS
int omap3430_clk_legacy_init(void);
int omap3430es1_clk_legacy_init(void);
int omap36xx_clk_legacy_init(void);
int am35xx_clk_legacy_init(void);
#else
static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
#endif
#endif

6
include/linux/compiler.h
View file

@ -202,7 +202,7 @@ static __always_inline void data_access_exceeds_word_size(void)
{
}
static __always_inline void __read_once_size(volatile void *p, void *res, int size)
static __always_inline void __read_once_size(const volatile void *p, void *res, int size)
{
switch (size) {
case 1: *(__u8 *)res = *(volatile __u8 *)p; break;
@ -259,10 +259,10 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s
*/
#define READ_ONCE(x) \
({ typeof(x) __val; __read_once_size(&x, &__val, sizeof(__val)); __val; })
({ union { typeof(x) __val; char __c[1]; } __u; __read_once_size(&(x), __u.__c, sizeof(x)); __u.__val; })
#define WRITE_ONCE(x, val) \
({ typeof(x) __val; __val = val; __write_once_size(&x, &__val, sizeof(__val)); __val; })
({ typeof(x) __val = (val); __write_once_size(&(x), &__val, sizeof(__val)); __val; })
#endif /* __KERNEL__ */

103
include/linux/dcache.h
View file

@ -215,13 +215,16 @@ struct dentry_operations {
#define DCACHE_LRU_LIST 0x00080000
#define DCACHE_ENTRY_TYPE 0x00700000
#define DCACHE_MISS_TYPE 0x00000000 /* Negative dentry */
#define DCACHE_DIRECTORY_TYPE 0x00100000 /* Normal directory */
#define DCACHE_AUTODIR_TYPE 0x00200000 /* Lookupless directory (presumed automount) */
#define DCACHE_SYMLINK_TYPE 0x00300000 /* Symlink */
#define DCACHE_FILE_TYPE 0x00400000 /* Other file type */
#define DCACHE_MISS_TYPE 0x00000000 /* Negative dentry (maybe fallthru to nowhere) */
#define DCACHE_WHITEOUT_TYPE 0x00100000 /* Whiteout dentry (stop pathwalk) */
#define DCACHE_DIRECTORY_TYPE 0x00200000 /* Normal directory */
#define DCACHE_AUTODIR_TYPE 0x00300000 /* Lookupless directory (presumed automount) */
#define DCACHE_REGULAR_TYPE 0x00400000 /* Regular file type (or fallthru to such) */
#define DCACHE_SPECIAL_TYPE 0x00500000 /* Other file type (or fallthru to such) */
#define DCACHE_SYMLINK_TYPE 0x00600000 /* Symlink (or fallthru to such) */
#define DCACHE_MAY_FREE 0x00800000
#define DCACHE_FALLTHRU 0x01000000 /* Fall through to lower layer */
extern seqlock_t rename_lock;
@ -423,6 +426,16 @@ static inline unsigned __d_entry_type(const struct dentry *dentry)
return dentry->d_flags & DCACHE_ENTRY_TYPE;
}
static inline bool d_is_miss(const struct dentry *dentry)
{
return __d_entry_type(dentry) == DCACHE_MISS_TYPE;
}
static inline bool d_is_whiteout(const struct dentry *dentry)
{
return __d_entry_type(dentry) == DCACHE_WHITEOUT_TYPE;
}
static inline bool d_can_lookup(const struct dentry *dentry)
{
return __d_entry_type(dentry) == DCACHE_DIRECTORY_TYPE;
@ -443,14 +456,25 @@ static inline bool d_is_symlink(const struct dentry *dentry)
return __d_entry_type(dentry) == DCACHE_SYMLINK_TYPE;
}
static inline bool d_is_reg(const struct dentry *dentry)
{
return __d_entry_type(dentry) == DCACHE_REGULAR_TYPE;
}
static inline bool d_is_special(const struct dentry *dentry)
{
return __d_entry_type(dentry) == DCACHE_SPECIAL_TYPE;
}
static inline bool d_is_file(const struct dentry *dentry)
{
return __d_entry_type(dentry) == DCACHE_FILE_TYPE;
return d_is_reg(dentry) || d_is_special(dentry);
}
static inline bool d_is_negative(const struct dentry *dentry)
{
return __d_entry_type(dentry) == DCACHE_MISS_TYPE;
// TODO: check d_is_whiteout(dentry) also.
return d_is_miss(dentry);
}
static inline bool d_is_positive(const struct dentry *dentry)
@ -458,10 +482,75 @@ static inline bool d_is_positive(const struct dentry *dentry)
return !d_is_negative(dentry);
}
extern void d_set_fallthru(struct dentry *dentry);
static inline bool d_is_fallthru(const struct dentry *dentry)
{
return dentry->d_flags & DCACHE_FALLTHRU;
}
extern int sysctl_vfs_cache_pressure;
static inline unsigned long vfs_pressure_ratio(unsigned long val)
{
return mult_frac(val, sysctl_vfs_cache_pressure, 100);
}
/**
* d_inode - Get the actual inode of this dentry
* @dentry: The dentry to query
*
* This is the helper normal filesystems should use to get at their own inodes
* in their own dentries and ignore the layering superimposed upon them.
*/
static inline struct inode *d_inode(const struct dentry *dentry)
{
return dentry->d_inode;
}
/**
* d_inode_rcu - Get the actual inode of this dentry with ACCESS_ONCE()
* @dentry: The dentry to query
*
* This is the helper normal filesystems should use to get at their own inodes
* in their own dentries and ignore the layering superimposed upon them.
*/
static inline struct inode *d_inode_rcu(const struct dentry *dentry)
{
return ACCESS_ONCE(dentry->d_inode);
}
/**
* d_backing_inode - Get upper or lower inode we should be using
* @upper: The upper layer
*
* This is the helper that should be used to get at the inode that will be used
* if this dentry were to be opened as a file. The inode may be on the upper
* dentry or it may be on a lower dentry pinned by the upper.
*
* Normal filesystems should not use this to access their own inodes.
*/
static inline struct inode *d_backing_inode(const struct dentry *upper)
{
struct inode *inode = upper->d_inode;
return inode;
}
/**
* d_backing_dentry - Get upper or lower dentry we should be using
* @upper: The upper layer
*
* This is the helper that should be used to get the dentry of the inode that
* will be used if this dentry were opened as a file. It may be the upper
* dentry or it may be a lower dentry pinned by the upper.
*
* Normal filesystems should not use this to access their own dentries.
*/
static inline struct dentry *d_backing_dentry(struct dentry *upper)
{
return upper;
}
#endif /* __LINUX_DCACHE_H */

120
include/linux/dmaengine.h
View file

@ -188,25 +188,6 @@ enum dma_ctrl_flags {
DMA_PREP_FENCE = (1 << 5),
};
/**
* enum dma_ctrl_cmd - DMA operations that can optionally be exercised
* on a running channel.
* @DMA_TERMINATE_ALL: terminate all ongoing transfers
* @DMA_PAUSE: pause ongoing transfers
* @DMA_RESUME: resume paused transfer
* @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
* that need to runtime reconfigure the slave channels (as opposed to passing
* configuration data in statically from the platform). An additional
* argument of struct dma_slave_config must be passed in with this
* command.
*/
enum dma_ctrl_cmd {
DMA_TERMINATE_ALL,
DMA_PAUSE,
DMA_RESUME,
DMA_SLAVE_CONFIG,
};
/**
* enum sum_check_bits - bit position of pq_check_flags
*/
@ -298,6 +279,9 @@ enum dma_slave_buswidth {
DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
};
/**
@ -336,9 +320,8 @@ enum dma_slave_buswidth {
* This struct is passed in as configuration data to a DMA engine
* in order to set up a certain channel for DMA transport at runtime.
* The DMA device/engine has to provide support for an additional
* command in the channel config interface, DMA_SLAVE_CONFIG
* and this struct will then be passed in as an argument to the
* DMA engine device_control() function.
* callback in the dma_device structure, device_config and this struct
* will then be passed in as an argument to the function.
*
* The rationale for adding configuration information to this struct is as
* follows: if it is likely that more than one DMA slave controllers in
@ -387,7 +370,7 @@ enum dma_residue_granularity {
/* struct dma_slave_caps - expose capabilities of a slave channel only
*
* @src_addr_widths: bit mask of src addr widths the channel supports
* @dstn_addr_widths: bit mask of dstn addr widths the channel supports
* @dst_addr_widths: bit mask of dstn addr widths the channel supports
* @directions: bit mask of slave direction the channel supported
* since the enum dma_transfer_direction is not defined as bits for each
* type of direction, the dma controller should fill (1 << <TYPE>) and same
@ -398,7 +381,7 @@ enum dma_residue_granularity {
*/
struct dma_slave_caps {
u32 src_addr_widths;
u32 dstn_addr_widths;
u32 dst_addr_widths;
u32 directions;
bool cmd_pause;
bool cmd_terminate;
@ -594,6 +577,14 @@ struct dma_tx_state {
* @fill_align: alignment shift for memset operations
* @dev_id: unique device ID
* @dev: struct device reference for dma mapping api
* @src_addr_widths: bit mask of src addr widths the device supports
* @dst_addr_widths: bit mask of dst addr widths the device supports
* @directions: bit mask of slave direction the device supports since
* the enum dma_transfer_direction is not defined as bits for
* each type of direction, the dma controller should fill (1 <<
* <TYPE>) and same should be checked by controller as well
* @residue_granularity: granularity of the transfer residue reported
* by tx_status
* @device_alloc_chan_resources: allocate resources and return the
* number of allocated descriptors
* @device_free_chan_resources: release DMA channel's resources
@ -608,14 +599,19 @@ struct dma_tx_state {
* The function takes a buffer of size buf_len. The callback function will
* be called after period_len bytes have been transferred.
* @device_prep_interleaved_dma: Transfer expression in a generic way.
* @device_control: manipulate all pending operations on a channel, returns
* zero or error code
* @device_config: Pushes a new configuration to a channel, return 0 or an error
* code
* @device_pause: Pauses any transfer happening on a channel. Returns
* 0 or an error code
* @device_resume: Resumes any transfer on a channel previously
* paused. Returns 0 or an error code
* @device_terminate_all: Aborts all transfers on a channel. Returns 0
* or an error code
* @device_tx_status: poll for transaction completion, the optional
* txstate parameter can be supplied with a pointer to get a
* struct with auxiliary transfer status information, otherwise the call
* will just return a simple status code
* @device_issue_pending: push pending transactions to hardware
* @device_slave_caps: return the slave channel capabilities
*/
struct dma_device {
@ -635,14 +631,19 @@ struct dma_device {
int dev_id;
struct device *dev;
u32 src_addr_widths;
u32 dst_addr_widths;
u32 directions;
enum dma_residue_granularity residue_granularity;
int (*device_alloc_chan_resources)(struct dma_chan *chan);
void (*device_free_chan_resources)(struct dma_chan *chan);
struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
size_t len, unsigned long flags);
struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
unsigned int src_cnt, size_t len, unsigned long flags);
struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
@ -674,31 +675,26 @@ struct dma_device {
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
struct dma_chan *chan, struct dma_interleaved_template *xt,
unsigned long flags);
int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
unsigned long arg);
int (*device_config)(struct dma_chan *chan,
struct dma_slave_config *config);
int (*device_pause)(struct dma_chan *chan);
int (*device_resume)(struct dma_chan *chan);
int (*device_terminate_all)(struct dma_chan *chan);
enum dma_status (*device_tx_status)(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *txstate);
void (*device_issue_pending)(struct dma_chan *chan);
int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
};
static inline int dmaengine_device_control(struct dma_chan *chan,
enum dma_ctrl_cmd cmd,
unsigned long arg)
{
if (chan->device->device_control)
return chan->device->device_control(chan, cmd, arg);
return -ENOSYS;
}
static inline int dmaengine_slave_config(struct dma_chan *chan,
struct dma_slave_config *config)
{
return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
(unsigned long)config);
if (chan->device->device_config)
return chan->device->device_config(chan, config);
return -ENOSYS;
}
static inline bool is_slave_direction(enum dma_transfer_direction direction)
@ -765,34 +761,28 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
src_sg, src_nents, flags);
}
static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
{
if (!chan || !caps)
return -EINVAL;
/* check if the channel supports slave transactions */
if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
return -ENXIO;
if (chan->device->device_slave_caps)
return chan->device->device_slave_caps(chan, caps);
return -ENXIO;
}
static inline int dmaengine_terminate_all(struct dma_chan *chan)
{
return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
if (chan->device->device_terminate_all)
return chan->device->device_terminate_all(chan);
return -ENOSYS;
}
static inline int dmaengine_pause(struct dma_chan *chan)
{
return dmaengine_device_control(chan, DMA_PAUSE, 0);
if (chan->device->device_pause)
return chan->device->device_pause(chan);
return -ENOSYS;
}
static inline int dmaengine_resume(struct dma_chan *chan)
{
return dmaengine_device_control(chan, DMA_RESUME, 0);
if (chan->device->device_resume)
return chan->device->device_resume(chan);
return -ENOSYS;
}
static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
@ -1059,6 +1049,7 @@ struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
const char *name);
struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
void dma_release_channel(struct dma_chan *chan);
int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
#else
static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
{
@ -1093,6 +1084,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
static inline void dma_release_channel(struct dma_chan *chan)
{
}
static inline int dma_get_slave_caps(struct dma_chan *chan,
struct dma_slave_caps *caps)
{
return -ENXIO;
}
#endif
/* --- DMA device --- */

3
include/linux/fs.h
View file

@ -968,9 +968,6 @@ struct file_lock_context {
struct list_head flc_flock;
struct list_head flc_posix;
struct list_head flc_lease;
int flc_flock_cnt;
int flc_posix_cnt;
int flc_lease_cnt;
};
/* The following constant reflects the upper bound of the file/locking space */

5
include/linux/hid-sensor-hub.h
View file

@ -33,6 +33,8 @@
* @units: Measurment unit for this attribute.
* @unit_expo: Exponent used in the data.
* @size: Size in bytes for data size.
* @logical_minimum: Logical minimum value for this attribute.
* @logical_maximum: Logical maximum value for this attribute.
*/
struct hid_sensor_hub_attribute_info {
u32 usage_id;
@ -146,6 +148,7 @@ int sensor_hub_input_get_attribute_info(struct hid_sensor_hub_device *hsdev,
/**
* sensor_hub_input_attr_get_raw_value() - Synchronous read request
* @hsdev: Hub device instance.
* @usage_id: Attribute usage id of parent physical device as per spec
* @attr_usage_id: Attribute usage id as per spec
* @report_id: Report id to look for
@ -160,6 +163,7 @@ int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev,
u32 attr_usage_id, u32 report_id);
/**
* sensor_hub_set_feature() - Feature set request
* @hsdev: Hub device instance.
* @report_id: Report id to look for
* @field_index: Field index inside a report
* @value: Value to set
@ -172,6 +176,7 @@ int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id,
/**
* sensor_hub_get_feature() - Feature get request
* @hsdev: Hub device instance.
* @report_id: Report id to look for
* @field_index: Field index inside a report
* @value: Place holder for return value

4
include/linux/i2c.h
View file

@ -130,8 +130,6 @@ extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client,
* @probe: Callback for device binding
* @remove: Callback for device unbinding
* @shutdown: Callback for device shutdown
* @suspend: Callback for device suspend
* @resume: Callback for device resume
* @alert: Alert callback, for example for the SMBus alert protocol
* @command: Callback for bus-wide signaling (optional)
* @driver: Device driver model driver
@ -174,8 +172,6 @@ struct i2c_driver {
/* driver model interfaces that don't relate to enumeration */
void (*shutdown)(struct i2c_client *);
int (*suspend)(struct i2c_client *, pm_message_t mesg);
int (*resume)(struct i2c_client *);
/* Alert callback, for example for the SMBus alert protocol.
* The format and meaning of the data value depends on the protocol.

1
include/linux/irqchip/mips-gic.h
View file

@ -243,7 +243,6 @@ extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
extern void gic_send_ipi(unsigned int intr);
extern unsigned int plat_ipi_call_int_xlate(unsigned int);
extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
extern unsigned int gic_get_timer_pending(void);
extern int gic_get_c0_compare_int(void);
extern int gic_get_c0_perfcount_int(void);
#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */

8
include/linux/kdb.h
View file

@ -156,8 +156,14 @@ typedef enum {
KDB_REASON_SYSTEM_NMI, /* In NMI due to SYSTEM cmd; regs valid */
} kdb_reason_t;
enum kdb_msgsrc {
KDB_MSGSRC_INTERNAL, /* direct call to kdb_printf() */
KDB_MSGSRC_PRINTK, /* trapped from printk() */
};
extern int kdb_trap_printk;
extern __printf(1, 0) int vkdb_printf(const char *fmt, va_list args);
extern __printf(2, 0) int vkdb_printf(enum kdb_msgsrc src, const char *fmt,
va_list args);
extern __printf(1, 2) int kdb_printf(const char *, ...);
typedef __printf(1, 2) int (*kdb_printf_t)(const char *, ...);

61
include/linux/lguest_launcher.h
View file

@ -8,52 +8,13 @@
*
* The Guest needs devices to do anything useful. Since we don't let it touch
* real devices (think of the damage it could do!) we provide virtual devices.
* We could emulate a PCI bus with various devices on it, but that is a fairly
* complex burden for the Host and suboptimal for the Guest, so we have our own
* simple lguest bus and we use "virtio" drivers. These drivers need a set of
* routines from us which will actually do the virtual I/O, but they handle all
* the net/block/console stuff themselves. This means that if we want to add
* a new device, we simply need to write a new virtio driver and create support
* for it in the Launcher: this code won't need to change.
* We emulate a PCI bus with virtio devices on it; we used to have our own
* lguest bus which was far simpler, but this tests the virtio 1.0 standard.
*
* Virtio devices are also used by kvm, so we can simply reuse their optimized
* device drivers. And one day when everyone uses virtio, my plan will be
* complete. Bwahahahah!
*
* Devices are described by a simplified ID, a status byte, and some "config"
* bytes which describe this device's configuration. This is placed by the
* Launcher just above the top of physical memory:
*/
struct lguest_device_desc {
/* The device type: console, network, disk etc. Type 0 terminates. */
__u8 type;
/* The number of virtqueues (first in config array) */
__u8 num_vq;
/*
* The number of bytes of feature bits. Multiply by 2: one for host
* features and one for Guest acknowledgements.
*/
__u8 feature_len;
/* The number of bytes of the config array after virtqueues. */
__u8 config_len;
/* A status byte, written by the Guest. */
__u8 status;
__u8 config[0];
};
/*D:135
* This is how we expect the device configuration field for a virtqueue
* to be laid out in config space.
*/
struct lguest_vqconfig {
/* The number of entries in the virtio_ring */
__u16 num;
/* The interrupt we get when something happens. */
__u16 irq;
/* The page number of the virtio ring for this device. */
__u32 pfn;
};
/*:*/
/* Write command first word is a request. */
enum lguest_req
@ -62,12 +23,22 @@ enum lguest_req
LHREQ_GETDMA, /* No longer used */
LHREQ_IRQ, /* + irq */
LHREQ_BREAK, /* No longer used */
LHREQ_EVENTFD, /* + address, fd. */
LHREQ_EVENTFD, /* No longer used. */
LHREQ_GETREG, /* + offset within struct pt_regs (then read value). */
LHREQ_SETREG, /* + offset within struct pt_regs, value. */
LHREQ_TRAP, /* + trap number to deliver to guest. */
};
/*
* The alignment to use between consumer and producer parts of vring.
* x86 pagesize for historical reasons.
* This is what read() of the lguest fd populates. trap ==
* LGUEST_TRAP_ENTRY for an LHCALL_NOTIFY (addr is the
* argument), 14 for a page fault in the MMIO region (addr is
* the trap address, insn is the instruction), or 13 for a GPF
* (insn is the instruction).
*/
#define LGUEST_VRING_ALIGN 4096
struct lguest_pending {
__u8 trap;
__u8 insn[7];
__u32 addr;
};
#endif /* _LINUX_LGUEST_LAUNCHER */

43
include/linux/mfd/axp20x.h
View file

@ -124,10 +124,27 @@ enum {
#define AXP288_PMIC_ADC_H 0x56
#define AXP288_PMIC_ADC_L 0x57
#define AXP288_ADC_TS_PIN_CTRL 0x84
#define AXP288_PMIC_ADC_EN 0x84
#define AXP288_FG_TUNE5 0xed
/* Fuel Gauge */
#define AXP288_FG_RDC1_REG 0xba
#define AXP288_FG_RDC0_REG 0xbb
#define AXP288_FG_OCVH_REG 0xbc
#define AXP288_FG_OCVL_REG 0xbd
#define AXP288_FG_OCV_CURVE_REG 0xc0
#define AXP288_FG_DES_CAP1_REG 0xe0
#define AXP288_FG_DES_CAP0_REG 0xe1
#define AXP288_FG_CC_MTR1_REG 0xe2
#define AXP288_FG_CC_MTR0_REG 0xe3
#define AXP288_FG_OCV_CAP_REG 0xe4
#define AXP288_FG_CC_CAP_REG 0xe5
#define AXP288_FG_LOW_CAP_REG 0xe6
#define AXP288_FG_TUNE0 0xe8
#define AXP288_FG_TUNE1 0xe9
#define AXP288_FG_TUNE2 0xea
#define AXP288_FG_TUNE3 0xeb
#define AXP288_FG_TUNE4 0xec
#define AXP288_FG_TUNE5 0xed
/* Regulators IDs */
enum {
@ -236,4 +253,26 @@ struct axp20x_dev {
const struct regmap_irq_chip *regmap_irq_chip;
};
#define BATTID_LEN 64
#define OCV_CURVE_SIZE 32
#define MAX_THERM_CURVE_SIZE 25
#define PD_DEF_MIN_TEMP 0
#define PD_DEF_MAX_TEMP 55
struct axp20x_fg_pdata {
char battid[BATTID_LEN + 1];
int design_cap;
int min_volt;
int max_volt;
int max_temp;
int min_temp;
int cap1;
int cap0;
int rdc1;
int rdc0;
int ocv_curve[OCV_CURVE_SIZE];
int tcsz;
int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
};
#endif /* __LINUX_MFD_AXP20X_H */

1
include/linux/mfd/da9063/core.h
View file

@ -36,6 +36,7 @@ enum da9063_models {
enum da9063_variant_codes {
PMIC_DA9063_AD = 0x3,
PMIC_DA9063_BB = 0x5,
PMIC_DA9063_CA = 0x6,
};
/* Interrupts */

68
include/linux/mfd/da9150/core.h Normal file
View file

@ -0,0 +1,68 @@
/*
* DA9150 MFD Driver - Core Data
*
* Copyright (c) 2014 Dialog Semiconductor
*
* Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __DA9150_CORE_H
#define __DA9150_CORE_H
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
/* I2C address paging */
#define DA9150_REG_PAGE_SHIFT 8
#define DA9150_REG_PAGE_MASK 0xFF
/* IRQs */
#define DA9150_NUM_IRQ_REGS 4
#define DA9150_IRQ_VBUS 0
#define DA9150_IRQ_CHG 1
#define DA9150_IRQ_TCLASS 2
#define DA9150_IRQ_TJUNC 3
#define DA9150_IRQ_VFAULT 4
#define DA9150_IRQ_CONF 5
#define DA9150_IRQ_DAT 6
#define DA9150_IRQ_DTYPE 7
#define DA9150_IRQ_ID 8
#define DA9150_IRQ_ADP 9
#define DA9150_IRQ_SESS_END 10
#define DA9150_IRQ_SESS_VLD 11
#define DA9150_IRQ_FG 12
#define DA9150_IRQ_GP 13
#define DA9150_IRQ_TBAT 14
#define DA9150_IRQ_GPIOA 15
#define DA9150_IRQ_GPIOB 16
#define DA9150_IRQ_GPIOC 17
#define DA9150_IRQ_GPIOD 18
#define DA9150_IRQ_GPADC 19
#define DA9150_IRQ_WKUP 20
struct da9150_pdata {
int irq_base;
};
struct da9150 {
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irq_data;
int irq;
int irq_base;
};
/* Device I/O */
u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
#endif /* __DA9150_CORE_H */

1155
include/linux/mfd/da9150/registers.h Normal file
View file

File diff suppressed because it is too large Load diff

1
include/linux/mfd/max77686-private.h
View file

@ -447,7 +447,6 @@ struct max77686_dev {
struct regmap_irq_chip_data *rtc_irq_data;
int irq;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
int irq_masks_cache[MAX77686_IRQ_GROUP_NR];

28
include/linux/mfd/max77686.h
View file

@ -119,12 +119,6 @@ enum max77802_regulators {
MAX77802_REG_MAX,
};
struct max77686_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *of_node;
};
enum max77686_opmode {
MAX77686_OPMODE_NORMAL,
MAX77686_OPMODE_LP,
@ -136,26 +130,4 @@ struct max77686_opmode_data {
int mode;
};
struct max77686_platform_data {
int ono;
int wakeup;
/* ---- PMIC ---- */
struct max77686_regulator_data *regulators;
int num_regulators;
struct max77686_opmode_data *opmode_data;
/*
* GPIO-DVS feature is not enabled with the current version of
* MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
* voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
*/
int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
unsigned int buck3_voltage[8];
unsigned int buck4_voltage[8];
};
#endif /* __LINUX_MFD_MAX77686_H */

13
include/linux/mfd/qcom_rpm.h Normal file
View file

@ -0,0 +1,13 @@
#ifndef __QCOM_RPM_H__
#define __QCOM_RPM_H__
#include <linux/types.h>
struct qcom_rpm;
#define QCOM_RPM_ACTIVE_STATE 0
#define QCOM_RPM_SLEEP_STATE 1
int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count);
#endif

260
include/linux/mfd/rt5033-private.h Normal file
View file

@ -0,0 +1,260 @@
/*
* MFD core driver for Richtek RT5033
*
* Copyright (C) 2014 Samsung Electronics, Co., Ltd.
* Author: Beomho Seo <beomho.seo@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published bythe Free Software Foundation.
*/
#ifndef __RT5033_PRIVATE_H__
#define __RT5033_PRIVATE_H__
enum rt5033_reg {
RT5033_REG_CHG_STAT = 0x00,
RT5033_REG_CHG_CTRL1 = 0x01,
RT5033_REG_CHG_CTRL2 = 0x02,
RT5033_REG_DEVICE_ID = 0x03,
RT5033_REG_CHG_CTRL3 = 0x04,
RT5033_REG_CHG_CTRL4 = 0x05,
RT5033_REG_CHG_CTRL5 = 0x06,
RT5033_REG_RT_CTRL0 = 0x07,
RT5033_REG_CHG_RESET = 0x08,
/* Reserved 0x09~0x18 */
RT5033_REG_RT_CTRL1 = 0x19,
/* Reserved 0x1A~0x20 */
RT5033_REG_FLED_FUNCTION1 = 0x21,
RT5033_REG_FLED_FUNCTION2 = 0x22,
RT5033_REG_FLED_STROBE_CTRL1 = 0x23,
RT5033_REG_FLED_STROBE_CTRL2 = 0x24,
RT5033_REG_FLED_CTRL1 = 0x25,
RT5033_REG_FLED_CTRL2 = 0x26,
RT5033_REG_FLED_CTRL3 = 0x27,
RT5033_REG_FLED_CTRL4 = 0x28,
RT5033_REG_FLED_CTRL5 = 0x29,
/* Reserved 0x2A~0x40 */
RT5033_REG_CTRL = 0x41,
RT5033_REG_BUCK_CTRL = 0x42,
RT5033_REG_LDO_CTRL = 0x43,
/* Reserved 0x44~0x46 */
RT5033_REG_MANUAL_RESET_CTRL = 0x47,
/* Reserved 0x48~0x5F */
RT5033_REG_CHG_IRQ1 = 0x60,
RT5033_REG_CHG_IRQ2 = 0x61,
RT5033_REG_CHG_IRQ3 = 0x62,
RT5033_REG_CHG_IRQ1_CTRL = 0x63,
RT5033_REG_CHG_IRQ2_CTRL = 0x64,
RT5033_REG_CHG_IRQ3_CTRL = 0x65,
RT5033_REG_LED_IRQ_STAT = 0x66,
RT5033_REG_LED_IRQ_CTRL = 0x67,
RT5033_REG_PMIC_IRQ_STAT = 0x68,
RT5033_REG_PMIC_IRQ_CTRL = 0x69,
RT5033_REG_SHDN_CTRL = 0x6A,
RT5033_REG_OFF_EVENT = 0x6B,
RT5033_REG_END,
};
/* RT5033 Charger state register */
#define RT5033_CHG_STAT_MASK 0x20
#define RT5033_CHG_STAT_DISCHARGING 0x00
#define RT5033_CHG_STAT_FULL 0x10
#define RT5033_CHG_STAT_CHARGING 0x20
#define RT5033_CHG_STAT_NOT_CHARGING 0x30
#define RT5033_CHG_STAT_TYPE_MASK 0x60
#define RT5033_CHG_STAT_TYPE_PRE 0x20
#define RT5033_CHG_STAT_TYPE_FAST 0x60
/* RT5033 CHGCTRL1 register */
#define RT5033_CHGCTRL1_IAICR_MASK 0xe0
#define RT5033_CHGCTRL1_MODE_MASK 0x01
/* RT5033 CHGCTRL2 register */
#define RT5033_CHGCTRL2_CV_MASK 0xfc
/* RT5033 CHGCTRL3 register */
#define RT5033_CHGCTRL3_CFO_EN_MASK 0x40
#define RT5033_CHGCTRL3_TIMER_MASK 0x38
#define RT5033_CHGCTRL3_TIMER_EN_MASK 0x01
/* RT5033 CHGCTRL4 register */
#define RT5033_CHGCTRL4_EOC_MASK 0x07
#define RT5033_CHGCTRL4_IPREC_MASK 0x18
/* RT5033 CHGCTRL5 register */
#define RT5033_CHGCTRL5_VPREC_MASK 0x0f
#define RT5033_CHGCTRL5_ICHG_MASK 0xf0
#define RT5033_CHGCTRL5_ICHG_SHIFT 0x04
#define RT5033_CHG_MAX_CURRENT 0x0d
/* RT5033 RT CTRL1 register */
#define RT5033_RT_CTRL1_UUG_MASK 0x02
#define RT5033_RT_HZ_MASK 0x01
/* RT5033 control register */
#define RT5033_CTRL_FCCM_BUCK_MASK 0x00
#define RT5033_CTRL_BUCKOMS_MASK 0x01
#define RT5033_CTRL_LDOOMS_MASK 0x02
#define RT5033_CTRL_SLDOOMS_MASK 0x03
#define RT5033_CTRL_EN_BUCK_MASK 0x04
#define RT5033_CTRL_EN_LDO_MASK 0x05
#define RT5033_CTRL_EN_SAFE_LDO_MASK 0x06
#define RT5033_CTRL_LDO_SLEEP_MASK 0x07
/* RT5033 BUCK control register */
#define RT5033_BUCK_CTRL_MASK 0x1f
/* RT5033 LDO control register */
#define RT5033_LDO_CTRL_MASK 0x1f
/* RT5033 charger property - model, manufacturer */
#define RT5033_CHARGER_MODEL "RT5033WSC Charger"
#define RT5033_MANUFACTURER "Richtek Technology Corporation"
/*
* RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
* AICR mode limits the input current for example,
* the AIRC 100 mode limits the input current to 100 mA.
*/
#define RT5033_AICR_100_MODE 0x20
#define RT5033_AICR_500_MODE 0x40
#define RT5033_AICR_700_MODE 0x60
#define RT5033_AICR_900_MODE 0x80
#define RT5033_AICR_1500_MODE 0xc0
#define RT5033_AICR_2000_MODE 0xe0
#define RT5033_AICR_MODE_MASK 0xe0
/* RT5033 use internal timer need to set time */
#define RT5033_FAST_CHARGE_TIMER4 0x00
#define RT5033_FAST_CHARGE_TIMER6 0x01
#define RT5033_FAST_CHARGE_TIMER8 0x02
#define RT5033_FAST_CHARGE_TIMER9 0x03
#define RT5033_FAST_CHARGE_TIMER12 0x04
#define RT5033_FAST_CHARGE_TIMER14 0x05
#define RT5033_FAST_CHARGE_TIMER16 0x06
#define RT5033_INT_TIMER_ENABLE 0x01
/* RT5033 charger termination enable mask */
#define RT5033_TE_ENABLE_MASK 0x08
/*
* RT5033 charger opa mode. RT50300 have two opa mode charger mode
* and boost mode for OTG
*/
#define RT5033_CHARGER_MODE 0x00
#define RT5033_BOOST_MODE 0x01
/* RT5033 charger termination enable */
#define RT5033_TE_ENABLE 0x08
/* RT5033 charger CFO enable */
#define RT5033_CFO_ENABLE 0x40
/* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN 3650000U
#define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM 25000U
#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX 4400000U
/* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN 350000U
#define RT5033_CHARGER_PRE_CURRENT_STEP_NUM 100000U
#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX 650000U
/* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
#define RT5033_CHARGER_FAST_CURRENT_MIN 700000U
#define RT5033_CHARGER_FAST_CURRENT_STEP_NUM 100000U
#define RT5033_CHARGER_FAST_CURRENT_MAX 2000000U
/*
* RT5033 charger const-charge end of charger current (
* as in CHGCTRL4 register), uA
*/
#define RT5033_CHARGER_EOC_MIN 150000U
#define RT5033_CHARGER_EOC_REF 300000U
#define RT5033_CHARGER_EOC_STEP_NUM1 50000U
#define RT5033_CHARGER_EOC_STEP_NUM2 100000U
#define RT5033_CHARGER_EOC_MAX 600000U
/*
* RT5033 charger pre-charge threshold volt limits
* (as in CHGCTRL5 register), uV
*/
#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN 2300000U
#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM 100000U
#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX 3800000U
/*
* RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
* circuit.
*/
#define RT5033_CHARGER_UUG_ENABLE 0x02
/* RT5033 charger High impedance mode */
#define RT5033_CHARGER_HZ_DISABLE 0x00
#define RT5033_CHARGER_HZ_ENABLE 0x01
/* RT5033 regulator BUCK output voltage uV */
#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 32
/* RT5033 regulator LDO output voltage uV */
#define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U
#define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U
#define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U
#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 32
/* RT5033 regulator SAFE LDO output voltage uV */
#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U
enum rt5033_fuel_reg {
RT5033_FUEL_REG_OCV_H = 0x00,
RT5033_FUEL_REG_OCV_L = 0x01,
RT5033_FUEL_REG_VBAT_H = 0x02,
RT5033_FUEL_REG_VBAT_L = 0x03,
RT5033_FUEL_REG_SOC_H = 0x04,
RT5033_FUEL_REG_SOC_L = 0x05,
RT5033_FUEL_REG_CTRL_H = 0x06,
RT5033_FUEL_REG_CTRL_L = 0x07,
RT5033_FUEL_REG_CRATE = 0x08,
RT5033_FUEL_REG_DEVICE_ID = 0x09,
RT5033_FUEL_REG_AVG_VOLT_H = 0x0A,
RT5033_FUEL_REG_AVG_VOLT_L = 0x0B,
RT5033_FUEL_REG_CONFIG_H = 0x0C,
RT5033_FUEL_REG_CONFIG_L = 0x0D,
/* Reserved 0x0E~0x0F */
RT5033_FUEL_REG_IRQ_CTRL = 0x10,
RT5033_FUEL_REG_IRQ_FLAG = 0x11,
RT5033_FUEL_VMIN = 0x12,
RT5033_FUEL_SMIN = 0x13,
/* Reserved 0x14~0x1F */
RT5033_FUEL_VGCOMP1 = 0x20,
RT5033_FUEL_VGCOMP2 = 0x21,
RT5033_FUEL_VGCOMP3 = 0x22,
RT5033_FUEL_VGCOMP4 = 0x23,
/* Reserved 0x24~0xFD */
RT5033_FUEL_MFA_H = 0xFE,
RT5033_FUEL_MFA_L = 0xFF,
RT5033_FUEL_REG_END,
};
/* RT5033 fuel gauge battery present property */
#define RT5033_FUEL_BAT_PRESENT 0x02
/* RT5033 PMIC interrupts */
#define RT5033_PMIC_IRQ_BUCKOCP 2
#define RT5033_PMIC_IRQ_BUCKLV 3
#define RT5033_PMIC_IRQ_SAFELDOLV 4
#define RT5033_PMIC_IRQ_LDOLV 5
#define RT5033_PMIC_IRQ_OT 6
#define RT5033_PMIC_IRQ_VDDA_UV 7
#endif /* __RT5033_PRIVATE_H__ */

62
include/linux/mfd/rt5033.h Normal file
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@ -0,0 +1,62 @@
/*
* MFD core driver for the RT5033
*
* Copyright (C) 2014 Samsung Electronics
* Author: Beomho Seo <beomho.seo@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published bythe Free Software Foundation.
*/
#ifndef __RT5033_H__
#define __RT5033_H__
#include <linux/regulator/consumer.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/power_supply.h>
/* RT5033 regulator IDs */
enum rt5033_regulators {
RT5033_BUCK = 0,
RT5033_LDO,
RT5033_SAFE_LDO,
RT5033_REGULATOR_NUM,
};
struct rt5033_dev {
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
int irq;
bool wakeup;
};
struct rt5033_battery {
struct i2c_client *client;
struct rt5033_dev *rt5033;
struct regmap *regmap;
struct power_supply psy;
};
/* RT5033 charger platform data */
struct rt5033_charger_data {
unsigned int pre_uamp;
unsigned int pre_uvolt;
unsigned int const_uvolt;
unsigned int eoc_uamp;
unsigned int fast_uamp;
};
struct rt5033_charger {
struct device *dev;
struct rt5033_dev *rt5033;
struct power_supply psy;
struct rt5033_charger_data *chg;
};
#endif /* __RT5033_H__ */

2
include/linux/mlx4/qp.h
View file

@ -427,7 +427,7 @@ struct mlx4_wqe_inline_seg {
enum mlx4_update_qp_attr {
MLX4_UPDATE_QP_SMAC = 1 << 0,
MLX4_UPDATE_QP_VSD = 1 << 2,
MLX4_UPDATE_QP_VSD = 1 << 1,
MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 2) - 1
};

1
include/linux/mtd/mtd.h
View file

@ -227,6 +227,7 @@ struct mtd_info {
int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
int (*_suspend) (struct mtd_info *mtd);
void (*_resume) (struct mtd_info *mtd);
void (*_reboot) (struct mtd_info *mtd);
/*
* If the driver is something smart, like UBI, it may need to maintain
* its own reference counting. The below functions are only for driver.

7
include/linux/mtd/spi-nor.h
View file

@ -56,6 +56,10 @@
/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
/* Status Register bits. */
#define SR_WIP 1 /* Write in progress */
#define SR_WEL 2 /* Write enable latch */
@ -67,6 +71,9 @@
#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
/* Flag Status Register bits */
#define FSR_READY 0x80

1
include/linux/netdevice.h
View file

@ -2341,6 +2341,7 @@ struct gro_remcsum {
static inline void skb_gro_remcsum_init(struct gro_remcsum *grc)
{
grc->offset = 0;
grc->delta = 0;
}

1
include/linux/nfs_fs.h
View file

@ -180,7 +180,6 @@ struct nfs_inode {
/* NFSv4 state */
struct list_head open_states;
struct nfs_delegation __rcu *delegation;
fmode_t delegation_state;
struct rw_semaphore rwsem;
/* pNFS layout information */

19
include/linux/nfs_xdr.h
View file

@ -1167,8 +1167,15 @@ struct nfs41_impl_id {
struct nfstime4 date;
};
struct nfs41_bind_conn_to_session_args {
struct nfs_client *client;
struct nfs4_sessionid sessionid;
u32 dir;
bool use_conn_in_rdma_mode;
};
struct nfs41_bind_conn_to_session_res {
struct nfs4_session *session;
struct nfs4_sessionid sessionid;
u32 dir;
bool use_conn_in_rdma_mode;
};
@ -1185,6 +1192,8 @@ struct nfs41_exchange_id_res {
struct nfs41_create_session_args {
struct nfs_client *client;
u64 clientid;
uint32_t seqid;
uint32_t flags;
uint32_t cb_program;
struct nfs4_channel_attrs fc_attrs; /* Fore Channel */
@ -1192,7 +1201,11 @@ struct nfs41_create_session_args {
};
struct nfs41_create_session_res {
struct nfs_client *client;
struct nfs4_sessionid sessionid;
uint32_t seqid;
uint32_t flags;
struct nfs4_channel_attrs fc_attrs; /* Fore Channel */
struct nfs4_channel_attrs bc_attrs; /* Back Channel */
};
struct nfs41_reclaim_complete_args {
@ -1351,7 +1364,7 @@ struct nfs_commit_completion_ops {
};
struct nfs_commit_info {
spinlock_t *lock;
spinlock_t *lock; /* inode->i_lock */
struct nfs_mds_commit_info *mds;
struct pnfs_ds_commit_info *ds;
struct nfs_direct_req *dreq; /* O_DIRECT request */

9
include/linux/nvme.h
View file

@ -17,7 +17,6 @@
#include <uapi/linux/nvme.h>
#include <linux/pci.h>
#include <linux/miscdevice.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
@ -62,8 +61,6 @@ enum {
NVME_CSTS_SHST_MASK = 3 << 2,
};
#define NVME_VS(major, minor) (major << 16 | minor)
extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
@ -91,9 +88,10 @@ struct nvme_dev {
struct nvme_bar __iomem *bar;
struct list_head namespaces;
struct kref kref;
struct miscdevice miscdev;
struct device *device;
work_func_t reset_workfn;
struct work_struct reset_work;
struct work_struct probe_work;
char name[12];
char serial[20];
char model[40];
@ -105,7 +103,6 @@ struct nvme_dev {
u16 abort_limit;
u8 event_limit;
u8 vwc;
u8 initialized;
};
/*
@ -121,6 +118,7 @@ struct nvme_ns {
unsigned ns_id;
int lba_shift;
int ms;
int pi_type;
u64 mode_select_num_blocks;
u32 mode_select_block_len;
};
@ -138,6 +136,7 @@ struct nvme_iod {
int nents; /* Used in scatterlist */
int length; /* Of data, in bytes */
dma_addr_t first_dma;
struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
struct scatterlist sg[0];
};

117
include/linux/platform_data/bfin_rotary.h Normal file
View file

@ -0,0 +1,117 @@
/*
* board initialization should put one of these structures into platform_data
* and place the bfin-rotary onto platform_bus named "bfin-rotary".
*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _BFIN_ROTARY_H
#define _BFIN_ROTARY_H
/* mode bitmasks */
#define ROT_QUAD_ENC CNTMODE_QUADENC /* quadrature/grey code encoder mode */
#define ROT_BIN_ENC CNTMODE_BINENC /* binary encoder mode */
#define ROT_UD_CNT CNTMODE_UDCNT /* rotary counter mode */
#define ROT_DIR_CNT CNTMODE_DIRCNT /* direction counter mode */
#define ROT_DEBE DEBE /* Debounce Enable */
#define ROT_CDGINV CDGINV /* CDG Pin Polarity Invert */
#define ROT_CUDINV CUDINV /* CUD Pin Polarity Invert */
#define ROT_CZMINV CZMINV /* CZM Pin Polarity Invert */
struct bfin_rotary_platform_data {
/* set rotary UP KEY_### or BTN_### in case you prefer
* bfin-rotary to send EV_KEY otherwise set 0
*/
unsigned int rotary_up_key;
/* set rotary DOWN KEY_### or BTN_### in case you prefer
* bfin-rotary to send EV_KEY otherwise set 0
*/
unsigned int rotary_down_key;
/* set rotary BUTTON KEY_### or BTN_### */
unsigned int rotary_button_key;
/* set rotary Relative Axis REL_### in case you prefer
* bfin-rotary to send EV_REL otherwise set 0
*/
unsigned int rotary_rel_code;
unsigned short debounce; /* 0..17 */
unsigned short mode;
unsigned short pm_wakeup;
unsigned short *pin_list;
};
/* CNT_CONFIG bitmasks */
#define CNTE (1 << 0) /* Counter Enable */
#define DEBE (1 << 1) /* Debounce Enable */
#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
#define CNTMODE_SHIFT 8
#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
#define BNDMODE_SHIFT 12
#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
/* CNT_IMASK bitmasks */
#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
#define UCIE (1 << 1) /* Up count Interrupt Enable */
#define DCIE (1 << 2) /* Down count Interrupt Enable */
#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
/* CNT_STATUS bitmasks */
#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
#define UCII (1 << 1) /* Up count Interrupt Identifier */
#define DCII (1 << 2) /* Down count Interrupt Identifier */
#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
/* CNT_COMMAND bitmasks */
#define W1LCNT 0xf /* Load Counter Register */
#define W1LMIN 0xf0 /* Load Min Register */
#define W1LMAX 0xf00 /* Load Max Register */
#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
/* CNT_DEBOUNCE bitmasks */
#define DPRESCALE 0xf /* Load Counter Register */
#endif

6
include/linux/platform_data/dma-dw.h
View file

@ -13,10 +13,12 @@
#include <linux/device.h>
#define DW_DMA_MAX_NR_MASTERS 4
/**
* struct dw_dma_slave - Controller-specific information about a slave
*
* @dma_dev: required DMA master device. Depricated.
* @dma_dev: required DMA master device
* @src_id: src request line
* @dst_id: dst request line
* @src_master: src master for transfers on allocated channel.
@ -53,7 +55,7 @@ struct dw_dma_platform_data {
unsigned char chan_priority;
unsigned short block_size;
unsigned char nr_masters;
unsigned char data_width[4];
unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
};
#endif /* _PLATFORM_DATA_DMA_DW_H */

7
include/linux/platform_data/dma-mmp_tdma.h
View file

@ -28,6 +28,13 @@ struct sram_platdata {
int granularity;
};
#ifdef CONFIG_ARM
extern struct gen_pool *sram_get_gpool(char *pool_name);
#else
static inline struct gen_pool *sram_get_gpool(char *pool_name)
{
return NULL;
}
#endif
#endif /* __DMA_MMP_TDMA_H */

22
include/linux/rhashtable.h
View file

@ -54,10 +54,11 @@ struct rhash_head {
* @buckets: size * hash buckets
*/
struct bucket_table {
size_t size;
unsigned int locks_mask;
spinlock_t *locks;
struct rhash_head __rcu *buckets[];
size_t size;
unsigned int locks_mask;
spinlock_t *locks;
struct rhash_head __rcu *buckets[] ____cacheline_aligned_in_smp;
};
typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed);
@ -78,12 +79,6 @@ struct rhashtable;
* @locks_mul: Number of bucket locks to allocate per cpu (default: 128)
* @hashfn: Function to hash key
* @obj_hashfn: Function to hash object
* @grow_decision: If defined, may return true if table should expand
* @shrink_decision: If defined, may return true if table should shrink
*
* Note: when implementing the grow and shrink decision function, min/max
* shift must be enforced, otherwise, resizing watermarks they set may be
* useless.
*/
struct rhashtable_params {
size_t nelem_hint;
@ -97,10 +92,6 @@ struct rhashtable_params {
size_t locks_mul;
rht_hashfn_t hashfn;
rht_obj_hashfn_t obj_hashfn;
bool (*grow_decision)(const struct rhashtable *ht,
size_t new_size);
bool (*shrink_decision)(const struct rhashtable *ht,
size_t new_size);
};
/**
@ -192,9 +183,6 @@ int rhashtable_init(struct rhashtable *ht, struct rhashtable_params *params);
void rhashtable_insert(struct rhashtable *ht, struct rhash_head *node);
bool rhashtable_remove(struct rhashtable *ht, struct rhash_head *node);
bool rht_grow_above_75(const struct rhashtable *ht, size_t new_size);
bool rht_shrink_below_30(const struct rhashtable *ht, size_t new_size);
int rhashtable_expand(struct rhashtable *ht);
int rhashtable_shrink(struct rhashtable *ht);

10
include/linux/sched.h
View file

@ -363,9 +363,6 @@ extern void show_regs(struct pt_regs *);
*/
extern void show_stack(struct task_struct *task, unsigned long *sp);
void io_schedule(void);
long io_schedule_timeout(long timeout);
extern void cpu_init (void);
extern void trap_init(void);
extern void update_process_times(int user);
@ -422,6 +419,13 @@ extern signed long schedule_timeout_uninterruptible(signed long timeout);
asmlinkage void schedule(void);
extern void schedule_preempt_disabled(void);
extern long io_schedule_timeout(long timeout);
static inline void io_schedule(void)
{
io_schedule_timeout(MAX_SCHEDULE_TIMEOUT);
}
struct nsproxy;
struct user_namespace;

7
include/linux/sunrpc/metrics.h
View file

@ -89,8 +89,11 @@ void rpc_free_iostats(struct rpc_iostats *);
static inline struct rpc_iostats *rpc_alloc_iostats(struct rpc_clnt *clnt) { return NULL; }
static inline void rpc_count_iostats(const struct rpc_task *task,
struct rpc_iostats *stats) {}
static inline void rpc_count_iostats_metrics(const struct rpc_task *,
struct rpc_iostats *) {}
static inline void rpc_count_iostats_metrics(const struct rpc_task *task,
struct rpc_iostats *stats)
{
}
static inline void rpc_print_iostats(struct seq_file *seq, struct rpc_clnt *clnt) {}
static inline void rpc_free_iostats(struct rpc_iostats *stats) {}

54
include/linux/thermal.h
View file

@ -314,6 +314,8 @@ void thermal_zone_of_sensor_unregister(struct device *dev,
}
#endif
#if IS_ENABLED(CONFIG_THERMAL)
struct thermal_zone_device *thermal_zone_device_register(const char *, int, int,
void *, struct thermal_zone_device_ops *,
const struct thermal_zone_params *, int, int);
@ -340,8 +342,58 @@ struct thermal_instance *get_thermal_instance(struct thermal_zone_device *,
struct thermal_cooling_device *, int);
void thermal_cdev_update(struct thermal_cooling_device *);
void thermal_notify_framework(struct thermal_zone_device *, int);
#else
static inline struct thermal_zone_device *thermal_zone_device_register(
const char *type, int trips, int mask, void *devdata,
struct thermal_zone_device_ops *ops,
const struct thermal_zone_params *tzp,
int passive_delay, int polling_delay)
{ return ERR_PTR(-ENODEV); }
static inline void thermal_zone_device_unregister(
struct thermal_zone_device *tz)
{ }
static inline int thermal_zone_bind_cooling_device(
struct thermal_zone_device *tz, int trip,
struct thermal_cooling_device *cdev,
unsigned long upper, unsigned long lower)
{ return -ENODEV; }
static inline int thermal_zone_unbind_cooling_device(
struct thermal_zone_device *tz, int trip,
struct thermal_cooling_device *cdev)
{ return -ENODEV; }
static inline void thermal_zone_device_update(struct thermal_zone_device *tz)
{ }
static inline struct thermal_cooling_device *
thermal_cooling_device_register(char *type, void *devdata,
const struct thermal_cooling_device_ops *ops)
{ return ERR_PTR(-ENODEV); }
static inline struct thermal_cooling_device *
thermal_of_cooling_device_register(struct device_node *np,
char *type, void *devdata, const struct thermal_cooling_device_ops *ops)
{ return ERR_PTR(-ENODEV); }
static inline void thermal_cooling_device_unregister(
struct thermal_cooling_device *cdev)
{ }
static inline struct thermal_zone_device *thermal_zone_get_zone_by_name(
const char *name)
{ return ERR_PTR(-ENODEV); }
static inline int thermal_zone_get_temp(
struct thermal_zone_device *tz, unsigned long *temp)
{ return -ENODEV; }
static inline int get_tz_trend(struct thermal_zone_device *tz, int trip)
{ return -ENODEV; }
static inline struct thermal_instance *
get_thermal_instance(struct thermal_zone_device *tz,
struct thermal_cooling_device *cdev, int trip)
{ return ERR_PTR(-ENODEV); }
static inline void thermal_cdev_update(struct thermal_cooling_device *cdev)
{ }
static inline void thermal_notify_framework(struct thermal_zone_device *tz,
int trip)
{ }
#endif /* CONFIG_THERMAL */
#ifdef CONFIG_NET
#if defined(CONFIG_NET) && IS_ENABLED(CONFIG_THERMAL)
extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
enum events event);
#else

2
include/linux/vfio.h
View file

@ -26,6 +26,7 @@
* @ioctl: Perform ioctl(2) on device file descriptor, supporting VFIO_DEVICE_*
* operations documented below
* @mmap: Perform mmap(2) on a region of the device file descriptor
* @request: Request for the bus driver to release the device
*/
struct vfio_device_ops {
char *name;
@ -38,6 +39,7 @@ struct vfio_device_ops {
long (*ioctl)(void *device_data, unsigned int cmd,
unsigned long arg);
int (*mmap)(void *device_data, struct vm_area_struct *vma);
void (*request)(void *device_data, unsigned int count);
};
extern int vfio_add_group_dev(struct device *dev,

44
include/linux/virtio_mmio.h
View file

@ -51,23 +51,29 @@
/* Virtio vendor ID - Read Only */
#define VIRTIO_MMIO_VENDOR_ID 0x00c
/* Bitmask of the features supported by the host
/* Bitmask of the features supported by the device (host)
* (32 bits per set) - Read Only */
#define VIRTIO_MMIO_HOST_FEATURES 0x010
#define VIRTIO_MMIO_DEVICE_FEATURES 0x010
/* Host features set selector - Write Only */
#define VIRTIO_MMIO_HOST_FEATURES_SEL 0x014
/* Device (host) features set selector - Write Only */
#define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014
/* Bitmask of features activated by the guest
/* Bitmask of features activated by the driver (guest)
* (32 bits per set) - Write Only */
#define VIRTIO_MMIO_GUEST_FEATURES 0x020
#define VIRTIO_MMIO_DRIVER_FEATURES 0x020
/* Activated features set selector - Write Only */
#define VIRTIO_MMIO_GUEST_FEATURES_SEL 0x024
#define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024
#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
/* Guest's memory page size in bytes - Write Only */
#define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028
#endif
/* Queue selector - Write Only */
#define VIRTIO_MMIO_QUEUE_SEL 0x030
@ -77,12 +83,21 @@
/* Queue size for the currently selected queue - Write Only */
#define VIRTIO_MMIO_QUEUE_NUM 0x038
#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
/* Used Ring alignment for the currently selected queue - Write Only */
#define VIRTIO_MMIO_QUEUE_ALIGN 0x03c
/* Guest's PFN for the currently selected queue - Read Write */
#define VIRTIO_MMIO_QUEUE_PFN 0x040
#endif
/* Ready bit for the currently selected queue - Read Write */
#define VIRTIO_MMIO_QUEUE_READY 0x044
/* Queue notifier - Write Only */
#define VIRTIO_MMIO_QUEUE_NOTIFY 0x050
@ -95,6 +110,21 @@
/* Device status register - Read Write */
#define VIRTIO_MMIO_STATUS 0x070
/* Selected queue's Descriptor Table address, 64 bits in two halves */
#define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080
#define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084
/* Selected queue's Available Ring address, 64 bits in two halves */
#define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090
#define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094
/* Selected queue's Used Ring address, 64 bits in two halves */
#define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0
#define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4
/* Configuration atomicity value */
#define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc
/* The config space is defined by each driver as
* the per-driver configuration space - Read Write */
#define VIRTIO_MMIO_CONFIG 0x100