From 66008f5ae6e4b60671114d35ab558e7787471f0b Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Thu, 5 Nov 2020 16:08:32 +0530 Subject: [PATCH] ARM: dts: msm: Add dmips and dynamic power co-efficient for Yupik Add capacity-dmips-mhz and dynamic power coefficient for Yupik, these are used by Energy aware scheduler for taskplacement decisions. Change-Id: I922e56d3df8f9c1cfb40ab8cfd77366375875006 --- qcom/yupik.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index be693f53cd92..fe0bc64891df 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -63,6 +63,8 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -82,6 +84,8 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -96,6 +100,8 @@ reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -110,6 +116,8 @@ reg = <0x0 0x300>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -124,6 +132,8 @@ reg = <0x0 0x400>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -138,6 +148,8 @@ reg = <0x0 0x500>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -152,6 +164,8 @@ reg = <0x0 0x600>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -166,6 +180,8 @@ reg = <0x0 0x700>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1985>; + dynamic-power-coefficient = <552>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache";