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ARM: dts: msm: Add DCVS device nodes to SM6150

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Add bw_hwmon and memlat device tree nodes to enable DCVS support
to SM6150.

Change-Id: I0b8fcdfa878df1cd8f0492114b65c9378656026b
This commit is contained in:
Shreyas K K 2020-12-18 09:02:00 +05:30 • committed by Gerrit - the friendly Code Review server
commit 71d7e2b857
1 changed files with 256 additions and 0 deletions
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256
qcom/sm6150.dtsi
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@ -14,6 +14,12 @@
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
opp-supported-hw = <ddrtype>;}
/ {
model = "Qualcomm Technologies, Inc. SM6150";
compatible = "qcom,sm6150";
@ -631,6 +637,256 @@
};
};
llcc_bw_opp_table: llcc-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
};
cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
compatible = "qcom,devfreq-icc";
governor = "performance";
interconnects = <&gem_noc MASTER_APPSS_PROC
&gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
compatible = "qcom,bimc-bwmon4";
reg = <0x90b6300 0x300>, <0x90b6200 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_cpu_llcc_bw>;
qcom,count-unit = <0x10000>;
};
ddr_bw_opp_table: ddr-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */
BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
};
cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
compatible = "qcom,devfreq-icc-ddr";
governor = "performance";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {
compatible = "qcom,bimc-bwmon5";
reg = <0x90cd000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_llcc_ddr_bw>;
qcom,count-unit = <0x10000>;
};
cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18321110 0x500>;
reg-names = "ftbl-base";
qcom,ftbl-row-size = <0x20>;
governor = "performance";
interconnects = <&osm_l3 MASTER_OSM_L3_APPS
&osm_l3 SLAVE_OSM_L3_CLUSTER0>;
};
cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
qcom,core-dev-table =
< 576000 300000000 >,
< 1017600 556800000 >,
< 1209660 806400000 >,
< 1516800 940800000 >,
< 1804800 1363200000 >;
};
cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "performance";
interconnects = <&gem_noc MASTER_APPSS_PROC
&gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "performance";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "performance";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
compatible = "qcom,arm-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
qcom,target-dev = <&cpu0_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,stall-cycle-ev = <0xE7>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,target-dev = <&cpu0_cpu_llcc_lat>;
qcom,cachemiss-ev = <0x2A>;
qcom,stall-cycle-ev = <0xE7>;
qcom,core-dev-table =
< 748000 MHZ_TO_MBPS(150, 16) >,
< 1209600 MHZ_TO_MBPS(300, 16) >,
< 1516800 MHZ_TO_MBPS(466, 16) >,
< 1804800 MHZ_TO_MBPS(600, 16) >;
};
cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
qcom,target-dev = <&cpu0_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 748000 MHZ_TO_MBPS( 300, 4) >,
< 1017600 MHZ_TO_MBPS( 451, 4) >,
< 1209600 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1804800 MHZ_TO_MBPS(1017, 4) >;
};
cpu0_computemon: qcom,cpu0-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
qcom,core-dev-table =
< 748800 MHZ_TO_MBPS( 300, 4) >,
< 1209600 MHZ_TO_MBPS( 451, 4) >,
< 1593600 MHZ_TO_MBPS( 547, 4) >,
< 1804800 MHZ_TO_MBPS( 768, 4) >;
};
};
cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18321110 0x500>;
reg-names = "ftbl-base";
qcom,ftbl-row-size = <0x20>;
governor = "performance";
interconnects = <&osm_l3 MASTER_OSM_L3_APPS
&osm_l3 SLAVE_OSM_L3_CLUSTER1>;
};
cpu6_cpu_l3_tbl: qcom,cpu6_cpu_l3_tbl {
qcom,core-dev-table =
< 1017600 556800000 >,
< 1209600 806400000 >,
< 1516800 940800000 >,
< 1708800 1209600000 >,
< 2208000 1363200000 >;
};
cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "performance";
interconnects = <&gem_noc MASTER_APPSS_PROC
&gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "performance";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "performance";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu6_memlat_cpugrp: qcom,cpu6-cpugrp {
compatible = "qcom,arm-memlat-cpugrp";
qcom,cpulist = <&CPU6 &CPU7>;
cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU6 &CPU7>;
qcom,target-dev = <&cpu6_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,stall-cycle-ev = <0x15E>;
qcom,core-dev-table = <&cpu6_cpu_l3_tbl>;
};
cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,target-dev = <&cpu6_cpu_llcc_lat>;
qcom,cachemiss-ev = <0x2A>;
qcom,stall-cycle-ev = <0x15E>;
qcom,core-dev-table =
< 768000 MHZ_TO_MBPS(300, 16) >,
< 1017600 MHZ_TO_MBPS(466, 16) >,
< 1209600 MHZ_TO_MBPS(600, 16) >,
< 1708800 MHZ_TO_MBPS(806, 16) >,
< 2208000 MHZ_TO_MBPS(933, 16) >;
};
cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU6 &CPU7>;
qcom,target-dev = <&cpu6_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 768000 MHZ_TO_MBPS( 451, 4) >,
< 1017600 MHZ_TO_MBPS( 547, 4) >,
< 1209600 MHZ_TO_MBPS(1017, 4) >,
< 1708800 MHZ_TO_MBPS(1555, 4) >,
< 2208000 MHZ_TO_MBPS(1804, 4) >;
};
cpu6_computemon: qcom,cpu6-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
qcom,core-dev-table =
< 1017600 MHZ_TO_MBPS( 300, 4) >,
< 1209600 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1708800 MHZ_TO_MBPS(1017, 4) >,
< 2208000 MHZ_TO_MBPS(1804, 4) >;
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6150-pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;