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mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-28 02:32:09 -04:00
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Merge branch 'mxs/cleanup' into next/multiplatform

Browse source 
This is a dependency for mxs/multiplatform

Signed-off-by: Arnd Bergmann <[email protected]>

Conflicts:
	drivers/clocksource/Makefile
This commit is contained in:
Arnd Bergmann 2013-04-09 15:57:27 +02:00
commit 71f6424023
579 changed files with 6491 additions and 4097 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/clk/clk-vt8500.c
View file

@ -157,7 +157,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
divisor = parent_rate / rate;
/* If prate / rate would be decimal, incr the divisor */
if (rate * divisor < *prate)
if (rate * divisor < parent_rate)
divisor++;
if (divisor == cdev->div_mask + 1)

42
drivers/clk/mxs/clk-imx23.c
View file

@ -15,12 +15,15 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <mach/common.h>
#include <mach/mx23.h>
#include <linux/of_address.h>
#include "clk.h"
#define DIGCTRL MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
#define CLKCTRL MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
static void __iomem *clkctrl;
static void __iomem *digctrl;
#define CLKCTRL clkctrl
#define DIGCTRL digctrl
#define PLLCTRL0 (CLKCTRL + 0x0000)
#define CPU (CLKCTRL + 0x0020)
#define HBUS (CLKCTRL + 0x0030)
@ -48,10 +51,10 @@ static void __init clk_misc_init(void)
u32 val;
/* Gate off cpu clock in WFI for power saving */
__mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
/* Clear BYPASS for SAIF */
__mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ);
writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
/* SAIF has to use frac div for functional operation */
val = readl_relaxed(SAIF);
@ -62,14 +65,14 @@ static void __init clk_misc_init(void)
* Source ssp clock from ref_io than ref_xtal,
* as ref_xtal only provides 24 MHz as maximum.
*/
__mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ);
writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
/*
* 480 MHz seems too high to be ssp clock source directly,
* so set frac to get a 288 MHz ref_io.
*/
__mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC);
__mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
}
static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
@ -101,6 +104,14 @@ int __init mx23_clocks_init(void)
struct device_node *np;
u32 i;
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
digctrl = of_iomap(np, 0);
WARN_ON(!digctrl);
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
clkctrl = of_iomap(np, 0);
WARN_ON(!clkctrl);
clk_misc_init();
clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@ -153,19 +164,12 @@ int __init mx23_clocks_init(void)
return PTR_ERR(clks[i]);
}
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
if (np) {
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
clk_register_clkdev(clks[clk32k], NULL, "timrot");
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
mxs_timer_init();
return 0;
}

42
drivers/clk/mxs/clk-imx28.c
View file

@ -15,11 +15,12 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <mach/common.h>
#include <mach/mx28.h>
#include <linux/of_address.h>
#include "clk.h"
#define CLKCTRL MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
static void __iomem *clkctrl;
#define CLKCTRL clkctrl
#define PLL0CTRL0 (CLKCTRL + 0x0000)
#define PLL1CTRL0 (CLKCTRL + 0x0020)
#define PLL2CTRL0 (CLKCTRL + 0x0040)
@ -53,7 +54,8 @@
#define BP_FRAC0_IO1FRAC 16
#define BP_FRAC0_IO0FRAC 24
#define DIGCTRL MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
static void __iomem *digctrl;
#define DIGCTRL digctrl
#define BP_SAIF_CLKMUX 10
/*
@ -72,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux)
if (clkmux > 0x3)
return -EINVAL;
__mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL);
__mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL);
writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
return 0;
}
@ -83,13 +85,13 @@ static void __init clk_misc_init(void)
u32 val;
/* Gate off cpu clock in WFI for power saving */
__mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
/* 0 is a bad default value for a divider */
__mxs_setl(1 << BP_ENET_DIV_TIME, ENET);
writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
/* Clear BYPASS for SAIF */
__mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ);
writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
/* SAIF has to use frac div for functional operation */
val = readl_relaxed(SAIF0);
@ -109,7 +111,7 @@ static void __init clk_misc_init(void)
* Source ssp clock from ref_io than ref_xtal,
* as ref_xtal only provides 24 MHz as maximum.
*/
__mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ);
writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
/*
* 480 MHz seems too high to be ssp clock source directly,
@ -156,6 +158,14 @@ int __init mx28_clocks_init(void)
struct device_node *np;
u32 i;
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
digctrl = of_iomap(np, 0);
WARN_ON(!digctrl);
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
clkctrl = of_iomap(np, 0);
WARN_ON(!clkctrl);
clk_misc_init();
clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@ -231,20 +241,14 @@ int __init mx28_clocks_init(void)
return PTR_ERR(clks[i]);
}
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
if (np) {
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clks[xbus], NULL, "timrot");
clk_register_clkdev(clks[enet_out], NULL, "enet_out");
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
mxs_timer_init();
return 0;
}